core0 may write the data used by other cpu, this will cause cache inconsistency. so need fulsh dcache before start other cpus. Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com> |
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|---|---|---|
| .. | ||
| CMakeLists.txt | ||
| init.h | ||
| Make.defs | ||
| nx_bringup.c | ||
| nx_smpstart.c | ||
| nx_start.c | ||