115 lines
4.2 KiB
C
115 lines
4.2 KiB
C
/****************************************************************************
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* arch/arm/src/armv6-m/ram_vectors.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV6_M_RAM_VECTORS_H
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#define __ARCH_ARM_SRC_ARMV6_M_RAM_VECTORS_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include "arm_internal.h"
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Vector Table Offset Register (VECTAB). This mask seems to vary among
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* ARMv6-M implementations. It may need to be redefined in some
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* architecture-specific header file. By default, the base address of the
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* new vector table must be aligned to the size of the vector table extended
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* to the next larger power of 2.
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*/
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#ifndef NVIC_VECTAB_TBLOFF_MASK
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# define NVIC_VECTAB_TBLOFF_MASK (0xffffff00)
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#endif
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/* Alignment ****************************************************************/
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#define VECTAB_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
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#ifdef CONFIG_ARCH_RAMVECTORS
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/* This is the size of the vector table (in 4-byte entries). This size
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* includes the (1) the peripheral interrupts, (2) space for 15 Cortex-M
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* exceptions, and (3) IDLE stack pointer which lies at the beginning of the
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* table.
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*/
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#define ARMV6M_VECTAB_SIZE (32 + 16)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
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* ARM-specific implementations of irq_initialize(), irq_attach(), and
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* irq_dispatch. In this case, it is also assumed that the ARM vector
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* table resides in RAM, has the name g_ram_vectors, and has been
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* properly positioned and aligned in memory by the linker script.
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*/
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extern up_vector_t g_ram_vectors[ARMV6M_VECTAB_SIZE]
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locate_data(".ram_vectors") aligned_data(VECTAB_ALIGN);
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arm_ramvec_initialize
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*
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* Description:
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* Copy vectors to RAM an configure the NVIC to use the RAM vectors.
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*
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****************************************************************************/
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void arm_ramvec_initialize(void);
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/****************************************************************************
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* Name: exception_common
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*
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* Description:
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* This is the default, common vector handling entrypoint.
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*
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****************************************************************************/
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void exception_common(void);
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/****************************************************************************
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* Name: arm_ramvec_attach
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*
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* Description:
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* Configure the ram vector table so that IRQ number 'irq' will be
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* dipatched by hardware to 'vector'
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*
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****************************************************************************/
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int arm_ramvec_attach(int irq, up_vector_t vector);
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#endif /* CONFIG_ARCH_RAMVECTORS */
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#endif /* __ARCH_ARM_SRC_ARMV6_M_RAM_VECTORS_H */
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