100 lines
4.1 KiB
C
100 lines
4.1 KiB
C
/****************************************************************************
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* arch/risc-v/src/litex/hardware/litex_memorymap.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_MEMORYMAP_H
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#define __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_MEMORYMAP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifdef CONFIG_LITEX_USE_CUSTOM_MEMORY_MAP
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#include CONFIG_LITEX_CUSTOM_MEMORY_MAP_PATH
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#else
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Base Address ****************************************************/
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#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP
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#define LITEX_CLINT_BASE 0xf0010000
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#define LITEX_PLIC_BASE 0xf0c00000
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#define LITEX_ETHMAC_BASE 0xf0002000
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#define LITEX_ETHPHY_BASE 0xf0002800
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#define LITEX_TIMER0_BASE 0xf0001800
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#define LITEX_UART0_BASE 0xf0001000
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#define LITEX_SDBLOCK2MEM_BASE 0xf0004000
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#define LITEX_SDCORE_BASE 0xf0004800
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#define LITEX_SDIRQ_BASE 0xf0005000
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#define LITEX_SDMEM2BLOCK_BASE 0xf0005800
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#define LITEX_SDPHY_BASE 0xf0006000
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#else
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#define LITEX_CPUTIMER_BASE 0xf0000800
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#define LITEX_ETHMAC_BASE 0xf0001000
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#define LITEX_ETHPHY_BASE 0xf0001800
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#define LITEX_TIMER0_BASE 0xf0006000
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#define LITEX_UART0_BASE 0xf0006800
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#define LITEX_SDBLOCK2MEM_BASE 0xf0003000
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#define LITEX_SDCORE_BASE 0xf0003800
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#define LITEX_SDIRQ_BASE 0xf0004000
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#define LITEX_SDMEM2BLOCK_BASE 0xf0004800
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#define LITEX_SDPHY_BASE 0xf0005000
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#endif
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/* Litex core control block */
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#define LITEX_CTRL_BASE 0xf0000800
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/* GPIO peripheral definitions.
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* - LITEX_GPIO_BASE is the first 32-bit address which contains a block
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* of GPIO registers (peripheral). Each block can contain up to 32 pins.
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* - LITEX_GPIO_OFFSET is the number of bytes between each GPIO peripheral.
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* - LITEX_GPIO_MAX is the number of peripherals enabled in gateware.
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*
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* Each peripheral is referenced by an index in the GPIO driver. E.g Index 0
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* is the first GPIO peripheral at 0xf0008000. Index 1 is at 0xf00080020.
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*/
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#define LITEX_GPIO_BASE 0xf0008000
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#define LITEX_GPIO_OFFSET 0x00000020
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#define LITEX_GPIO_MAX 8
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/* PWM peripheral definitions.
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* - LITEX_PWM_BASE is the first 32-bit address which contains a block
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* of PWM registers (peripheral). Each block controls a single output
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* channel.
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* - LITEX_PWM_OFFSET is the number of bytes between each PWM peripheral.
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* - LITEX_PWM_MAX is the number of peripherals enabled in gateware.
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*
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* Each peripheral is referenced by an index in the PWM driver. E.g Index 0
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* is the first PWM peripheral at 0xF0009800. Index 1 is at 0xF0009008C.
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*/
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#define LITEX_PWM_BASE 0xf0009800
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#define LITEX_PWM_OFFSET 0x0000000c
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#define LITEX_PWM_MAX 4
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#define LITEX_ETHMAC_RXBASE 0x80000000
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#define LITEX_ETHMAC_TXBASE 0x80001000
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#endif /* CONFIG_LITEX_USE_CUSTOM_MEMORY_MAP */
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#endif /* __ARCH_RISCV_SRC_LITEX_HARDWARE_LITEX_MEMORYMAP_H */
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