54b7bf6e36
First commit of ADC for G0. Have it working basically. Need to make changes regarding adccmn stuff. Added changes to make stm32_adc.c compatible with both G0 and other families. Add oversampling support. This is for G0 and L0. Add ADC oversampling to Kconfig. Use adccmn_modifyreg for all, updated hw file to accomodate G0. Style fixes. Move init of oversampling to a function, and call it if OVERSAMPLE is configured. Limited changes to stm32_bringup.c Style fixes to hardware/stm32_adc.h Changed nucleo-g0b1re to run at 64 MHz. Fixed errors in clock setup. Added defines for setting up ADC clock. Added code for STM32G0 ADC clock configuration. Added adc_ckmode_cfg function. ckmode bits were previously neglected, assuming async clock to ADC was used. Added other feedback from pull request #16500. Added feedback from pull request #16500. Changed format of STM32F0L0G0_HAVE_ADC_OVERSAMPLE config. Removed FARs from ioc_set_oversample. Fixed formatting of helps in Kconfig. Adjusted spacing on help content. Simplified adc_common_cfg. CCR_PRESC relies on board.h Fixed formatting Add ADC pinmaps for stm32g0
221 lines
7.3 KiB
C
221 lines
7.3 KiB
C
/****************************************************************************
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* boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* HSI - Internal 16 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - 8 MHz from MCO output of ST-LINK (disabled by default)
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* Main PLL Configuration.
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*
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* PLL source is HSI = 16,000,000
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*
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 1 <= PLLM <= 8
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* 8 <= PLLN <= 86
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* 4 MHz <= PLL_IN <= 16MHz
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* 64 MHz <= PLL_VCO <= 344MHz
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* SYSCLK = PLLRCLK = PLL_VCO / PLLR
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*
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*/
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/* PLL source is HSI, PLLN=50, PLLM=4
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* PLLP enable, PLLQ enable, PLLR enable
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*
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* 2 <= PLLP <= 32
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* 2 <= PLLQ <= 8
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* 2 <= PLLR <= 8
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*
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* PLLR <= 64MHz
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* PLLQ <= 64MHz
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* PLLP <= 64MHz
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*
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* PLL_VCO = (16,000,000 / 2) * 32 = 256 MHz
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*
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* PLLP = PLL_VCO/4 = 256 MHz / 4 = 64 MHz
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* PLLQ = PLL_VCO/4 = 256 MHz / 4 = 64 MHz
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* PLLR = PLL_VCO/4 = 256 MHz / 4 = 64 MHz
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*/
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#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI
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#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \
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RCC_PLLCFG_PLLQEN | \
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RCC_PLLCFG_PLLREN)
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(64)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4)
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4)
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#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 2) * 64)
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#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4)
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#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 4)
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#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 4)
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/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY)
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/* AHB clock (HCLK) is SYSCLK (40MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* ADC1 clock prescaled is SYSCLK (64MHz) / 2 = 32MHz */
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#define STM32_ADC_CLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_SYSCLK
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#define STM32_ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_ADCCLK
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#define STM32_ADC_CCR_PRESC ADC_CCR_PRESC_DIV2
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/* LED definitions **********************************************************/
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/* The Nucleo G0B1RE board has four LEDs. Three of these are controlled by
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* logic on the board and are not available for software control:
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*
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* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
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* communications are in progress between the PC and the
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* ST-LINK/V2-1.
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*
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* LD2 5V_USB_CHG: Green LED is on when board is powered by 5V source.
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*
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* LD3 PWR: red LED indicates that the board is powered.
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*
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* And one can be controlled by software:
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*
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* User LD4: green LED is a user LED connected to the I/O PA5 of the
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* STM32G0B1RE.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
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* any way. The following definition is used to access the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD4 */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
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* the Nucleo G0B1RE. The following definitions describe how NuttX controls
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* the LED:
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*
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* SYMBOL Meaning LED1 state
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* ------------------ ----------------------- ----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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/* The Nucleo G0B1RE supports two buttons; only one button is controllable
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* by software:
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*
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* B1 USER: user button connected to the I/O PC13 of the MCU.
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* B2 RESET: push button connected to NRST is used to RESET the MCU.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* USART */
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/* By default the USART2 is connected to STLINK Virtual COM Port:
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* USART2_RX - PA3
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* USART2_TX - PA2
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*/
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#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_HIGH) /* PA3 */
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#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_HIGH) /* PA2 */
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/* ADC */
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#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
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/* DMA channels *************************************************************/
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/* ADC */
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#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
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#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G0B1RE_INCLUDE_BOARD_H */
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