1. Enable timer and irq finally to make sure timer callback was already
registered. When the CPU resets, the values of some generic timer
registers are undefined. Enabling the timer interrupt in advance may
cause the timer to trigger early while the timer callback is not yet
registered. This results in the timer ISR being executed, which masks
the timer interrupt. Since the timer callback is not registered at
this point, the timer interrupt is not unmasked, further causing the
system scheduler to hang.
2. Remove timer mask for one-shot timer and that's in isr,
irq/fiq is disabled. Masking generic timer is not necessary, and it
may introduce risks, otherwise, mask/unmask must be pair in all
situations.
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
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