As pointed out in #11322 there is a hardware design issue in RISC-V that affects RV64 relocations. The problem is with how address bits are loaded into registers via lui / auipc and sign extension. If the hi20 relocation value happens to have its 32-bit sign bit set, i.e. value is 0x80000000 (but not negative! i.e. negative in 64-bit format) the relocation will fail, as the address is erroneously sign extended: 0x00000000_80000000 becomes 0xffffffff_80000000 which is not correct. Also, make sure the correct opcode is used with PCREL_HI20, it expects AUIPC (not LUI). The C compiler will never emit such code but when hand- writing assembly code this can happen. |
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| arm | ||
| arm64 | ||
| renesas | ||
| risc-v | ||
| sim | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| arch_atomic.c | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Make.defs | ||