245 lines
8.1 KiB
ArmAsm
245 lines
8.1 KiB
ArmAsm
/****************************************************************************
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* arch/arm/src/armv6-m/arm_exception.S
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-FileCopyrightText: 2013 Gregory Nutt. All rights reserved.
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* SPDX-FileCopyrightText: 2012 Michael Smith. All rights reserved.
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* SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#ifdef CONFIG_SMP
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# include "chip.h"
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#endif
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#include "exc_return.h"
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.globl exception_common
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.file "arm_exception.S"
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/****************************************************************************
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* .text
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****************************************************************************/
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/* Common exception handling logic. On entry here, the return stack is on either
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* the PSP or the MSP and looks like the following:
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*
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* REG_XPSR
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* REG_R15
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* REG_R14
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* REG_R12
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* REG_R3
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* REG_R2
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* REG_R1
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* MSP->REG_R0
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*
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* And
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* IPSR contains the IRQ number
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* R14 Contains the EXC_RETURN value
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* We are in handler mode and the current SP is the MSP
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*/
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.text
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.align 2
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.code 16
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.thumb_func
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.syntax unified
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.type exception_common, function
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exception_common:
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.cfi_sections .debug_frame
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.cfi_startproc
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/* Complete the context save */
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/* Get the current stack pointer. The EXC_RETURN value tells us whether
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* the context is on the MSP or PSP.
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*/
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mov r0, r14 /* Copy high register to low register */
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lsls r0, #(31 - EXC_RETURN_PROCESS_BITNO) /* Move to bit 31 */
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bmi 1f /* Test bit 31 */
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mrs r1, msp /* R1=The main stack pointer */
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subs r1, #SW_XCPT_SIZE /* R1=Beginning of context array on the stack */
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msr msp, r1 /* Reserved stack space */
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isb sy
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b 2f
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1:
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mrs r1, psp /* R1=The process stack pointer */
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subs r1, #SW_XCPT_SIZE /* R1=Beginning of context array on the stack */
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/* R1 is the current stack pointer. HW_XCPT_REGS were pushed onto the stack
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* when the interrupt was taken so (R1)+HW_XCPT_SIZE is the value of the
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* stack pointer before the interrupt. The total size of the context save
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* area is XCPTCONTEXT_SIZE = SW_XCPT_SIZE + HW_XCPT_SIZE so (R1)-SW_XCPT_SIZE
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* is the address of the beginning of the context save area.
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*/
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2:
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/* Save SP, PRIMASK, and R4-R7 in the context array */
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movs r2, #XCPTCONTEXT_SIZE /* R2=Size of the context array */
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add r2, r1 /* R2=MSP/PSP before the interrupt was taken */
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/* (ignoring the xPSR[9] alignment bit) */
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mrs r3, primask /* R3=Current PRIMASK setting */
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mov r0, r1 /* Copy the context array pointer */
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stmia r0!, {r2-r7} /* Save the SP, PRIMASK, and R4-R7 in the context array */
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/* Save R8-R11 control and the EXEC_RETURN value in the context array */
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mov r2, r8 /* Copy high registers to low */
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mov r3, r9
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mov r4, r10
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mov r5, r11
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mrs r6, control /* R6=control */
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mov r7, r14
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stmia r0!, {r2-r7} /* Save the high registers r8-r11 control and r14 */
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/* Get the exception number in R0=IRQ, R1=register save area on stack */
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mrs r0, ipsr /* R0=exception number */
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
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* stack pointer. The way that this is done here prohibits nested interrupts!
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* Otherwise, we will use the stack that was current when the interrupt was taken.
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*/
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#if CONFIG_ARCH_INTERRUPTSTACK < 3
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/* If the interrupt stack is disabled, reserve xcpcontext to ensure
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* that signal processing can have a separate xcpcontext to handle
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* signal context (reference: arm_schedulesigaction.c):
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* ----------------------
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* | IRQ XCP context |
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* ----------------------
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* | Signal XCP context |
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* ---------------------- <- SP
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* also the sp should be restore after arm_doirq()
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*/
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mov r2, r14
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lsls r2, #(31 - EXC_RETURN_THREAD_BITNO) /* Move to bit 31 */
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bpl 3f /* Test bit 31 */
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mov r2, r1 /* Reserve signal context */
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subs r2, r2, #XCPTCONTEXT_SIZE
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msr msp, r2 /* We are using the main stack pointer */
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isb sy
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3:
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#endif
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mov fp, r1
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.cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */
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.cfi_offset pc, REG_PC * 4
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.cfi_offset sp, REG_SP * 4
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.cfi_offset lr, REG_LR * 4
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bl arm_doirq /* R0=IRQ, R1=register save area on stack */
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/* On return from arm_doirq, R0 will hold a pointer to register context
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* array to use for the interrupt return.
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*/
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/* Recover R8-R11 and EXEC_RETURN (5 registers) */
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movs r2, #(4*REG_R8) /* R2=Offset to R8 storage */
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adds r1, r0, r2 /* R1=Address of R8 storage */
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ldmia r1!, {r2-r7} /* Recover R8-R11 control and R14 (6 registers)*/
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mov r8, r2 /* Move to position in high registers */
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mov r9, r3
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mov r10, r4
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mov r11, r5
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msr control, r6
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mov r14, r7 /* EXEC_RETURN */
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/* Recover SP (R2), PRIMASK (R3), and R4-R7. Determine the value of
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* the stack pointer as it was on entry to the exception handler.
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*/
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ldmia r0!, {r2-r7} /* Recover R4-R7 + 2 temp values */
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movs r1, #HW_XCPT_SIZE /* R1=Size of hardware-saved portion of the context array */
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subs r1, r2, r1 /* R1=Value of MSP/PSP on exception entry */
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/* Restore the stack pointer. The EXC_RETURN value tells us whether the
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* context is on the MSP or PSP.
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*/
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mov r0, r14 /* Copy high register to low register */
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lsls r0, #(31 - EXC_RETURN_PROCESS_BITNO) /* Move to bit 31 */
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bmi 4f /* Test bit 31 */
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msr msp, r1 /* R1=The main stack pointer */
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isb sy
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b 5f
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4:
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msr psp, r1 /* R1=The process stack pointer */
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isb sy
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5:
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/* Restore the interrupt state */
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msr primask, r3 /* Restore interrupts priority masking*/
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/* Always return with R14 containing the special value that will: (1)
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* return to thread mode, and (2) select the correct stack.
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*/
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bx r14 /* And return */
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.cfi_endproc
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.size exception_common, .-exception_common
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/****************************************************************************
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* Name: g_intstackalloc/g_intstacktop
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*
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* Description:
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* Shouldn't happen
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*
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****************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.bss
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.global g_intstackalloc
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.global g_intstacktop
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.balign 4
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g_intstackalloc:
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.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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g_intstacktop:
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.size g_intstackalloc, .-g_intstackalloc
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#endif
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.end
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