113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/****************************************************************************
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* arch/arm/src/armv6-m/arm_ramvec_initialize.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <debug.h>
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#include <inttypes.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "nvic.h"
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#include "ram_vectors.h"
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#include "chip.h"
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#include "arm_internal.h"
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#ifdef CONFIG_ARCH_RAMVECTORS
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
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* ARM-specific implementations of arm_ramvec_initialize(), irq_attach(), and
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* irq_dispatch. In this case, it is also assumed that the ARM vector
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* table resides in RAM, has the name g_ram_vectors, and has been
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* properly positioned and aligned in memory by the linker script.
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*/
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up_vector_t g_ram_vectors[ARMV6M_VECTAB_SIZE]
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locate_data(".ram_vectors") aligned_data(VECTAB_ALIGN);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_ramvec_initialize
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*
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* Description:
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* Copy vectors to RAM an configure the NVIC to use the RAM vectors.
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*
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****************************************************************************/
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void arm_ramvec_initialize(void)
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{
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const up_vector_t *src;
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up_vector_t *dest;
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int i;
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/* The vector table must be aligned */
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DEBUGASSERT(((uint32_t)g_ram_vectors & ~NVIC_VECTAB_TBLOFF_MASK) == 0);
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/* Copy the ROM vector table at address zero to RAM vector table.
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*
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* This must be done BEFORE the MPU is enable if the MPU is being used to
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* protect against NULL pointer references.
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*/
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src = (const up_vector_t *)getreg32(ARMV6M_SYSCON_VECTAB);
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dest = g_ram_vectors;
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irqinfo("src=%p dest=%p\n", src, dest);
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for (i = 0; i < ARMV6M_VECTAB_SIZE; i++)
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{
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*dest++ = *src++;
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}
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/* Now configure the NVIC to use the new vector table. */
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putreg32((uint32_t)g_ram_vectors, ARMV6M_SYSCON_VECTAB);
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/* The number bits required to align the RAM vector table seem to vary
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* from part-to-part. The following assertion will catch the case where
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* the table alignment is insufficient.
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*/
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irqinfo("NVIC_VECTAB=%08" PRIx32 "\n", getreg32(ARMV6M_SYSCON_VECTAB));
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DEBUGASSERT(getreg32(ARMV6M_SYSCON_VECTAB) == (uint32_t)g_ram_vectors);
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}
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#endif /* CONFIG_ARCH_RAMVECTORS */
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