819 lines
25 KiB
ArmAsm
819 lines
25 KiB
ArmAsm
/****************************************************************************
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* arch/arm/src/armv7-a/arm_head.S
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include "arm.h"
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#include "sctlr.h"
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#include "mmu.h"
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#include "chip.h"
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#include "arm_internal.h"
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#ifndef IDLE_STACK_BASE
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#ifdef CONFIG_BOOT_SDRAM_DATA
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#define IDLE_STACK_BASE IDLE_STACK_VBASE
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#else
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#define IDLE_STACK_BASE _ebss
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#endif
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#endif
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#define IDLE_STACK_TOP (IDLE_STACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
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#ifndef CONFIG_LEGACY_PAGING
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.file "arm_head.S"
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/****************************************************************************
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* Configuration
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****************************************************************************/
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/* There are three operational memory configurations:
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*
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* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case
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* the boot logic must:
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*
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* - Configure SDRAM (if present),
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* - Initialize the .data section in RAM, and
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* - Clear .bss section
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*/
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* Check for the identity mapping: For this configuration, this would be
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* the case where the virtual beginning of FLASH is the same as the physical
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* beginning of FLASH.
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*/
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# if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART)
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# error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined"
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# endif
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# if CONFIG_FLASH_START == CONFIG_FLASH_VSTART
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# define CONFIG_IDENTITY_TEXTMAP 1
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# endif
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/* 2. We boot in FLASH but copy ourselves to SDRAM from better performance.
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* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case
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* the boot logic must:
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*
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* - Configure SDRAM (if present),
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* - Copy ourself to DRAM (after mapping it), and
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* - Clear .bss section (data should be fully initialized)
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*
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* In this case, we assume that the logic within this file executes from FLASH.
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*/
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#elif defined(CONFIG_BOOT_COPYTORAM)
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# error "configuration not implemented"
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/* Check for the identity mapping: For this configuration, this would be
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* the case where the virtual beginning of FLASH is the same as the physical
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* beginning of FLASH.
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*/
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# if !defined(CONFIG_FLASH_START) || !defined(CONFIG_FLASH_VSTART)
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# error "CONFIG_FLASH_START or CONFIG_FLASH_VSTART is not defined"
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# endif
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# if CONFIG_FLASH_START == CONFIG_FLASH_VSTART
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# define CONFIG_IDENTITY_TEXTMAP 1
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# endif
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/* 3. There is bootloader that copies us to SDRAM (but probably not to the beginning)
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* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). In this case SDRAM
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* was initialized by the boot loader, and this boot logic must:
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*
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* - Clear .bss section (data should be fully initialized)
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*/
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#else
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/* Check for the identity mapping: For this configuration, this would be
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* the case where the virtual beginning of RAM is the same as the physical
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* beginning of RAM.
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*/
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# if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
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# error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
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# endif
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# if CONFIG_RAM_START == CONFIG_RAM_VSTART
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# define CONFIG_IDENTITY_TEXTMAP 1
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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/* The ARMv7-A L1 page table can be placed at the beginning or at the end of
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* the RAM space. This decision is based on the placement of the vector
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* area: If the vectors are place in low memory at address 0x0000 0000, then
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* the page table is placed in high memory; if the vectors are placed in
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* high memory at address 0xfff0 0000, then the page table is locating at
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* the beginning of RAM.
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*
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* For the special case where (1) the program executes out of RAM, and (2)
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* the page is located at the beginning of RAM (i.e., the high vector case),
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* then the following macro can easily find the physical address of the
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* section that includes the first part of the text region: Since the page
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* table is closely related to the NuttX base address in this case, we can
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* convert the page table base address to the base address of the section
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* containing both.
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*/
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/* This macro will modify r0, r1, r2 and r14 */
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#ifdef CONFIG_DEBUG_FEATURES
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.macro showprogress, code
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mov r0, #\code
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bl arm_lowputc
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.endm
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#else
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.macro showprogress, code
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.endm
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#endif
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/****************************************************************************
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* Name: __start
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****************************************************************************/
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/* We assume the bootloader has already initialized most of the h/w for
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* us and that only leaves us having to do some os specific things
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* below.
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*/
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.text
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.syntax unified
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.arm
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.global __start
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.type __start, #function
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__start:
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#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
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/* Get cpuindex, cpu0 continue boot, others wait event from cpu0 */
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mrc CP15_MPIDR(r0)
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and r0, r0, #0x3
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cmp r0, #0
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beq __cpu0_start
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#ifdef CONFIG_ARMV7A_SMP_BUSY_WAIT
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ldr r2, =CONFIG_ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
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1:
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ldr r1, [r2, #0]
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cmp r1, #0
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beq 1b
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#else
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wfe
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#endif
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cmp r0, #1
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beq __cpu1_start
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# if CONFIG_SMP_NCPUS > 2
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cmp r0, #2
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beq __cpu2_start
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# endif
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# if CONFIG_SMP_NCPUS > 3
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cmp r0, #3
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beq __cpu3_start
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# endif
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# if CONFIG_SMP_NCPUS > 4
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cmp r0, #4
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beq __cpu4_start
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# endif
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__cpu0_start:
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#endif
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/* Make sure that we are in SYS mode with IRQs and FIQs disabled */
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cpsid if, #PSR_MODE_SYS
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/* The MMU and caches should be disabled */
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mrc CP15_SCTLR(r0)
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bic r0, r0, #(SCTLR_M | SCTLR_C)
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bic r0, r0, #(SCTLR_I)
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mcr CP15_SCTLR(r0)
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isb
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/* Clear the 16K level 1 page table */
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ldr r5, .LCppgtable /* r5=phys. page table */
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#ifndef CONFIG_ARCH_ROMPGTABLE
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mov r0, r5
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mov r1, #0
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add r2, r0, #PGTABLE_SIZE
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.Lpgtableclear:
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #4
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teq r0, r2
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bne .Lpgtableclear
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#ifdef ARMV7A_PGTABLE_MAPPING
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/* If the page table does not lie in the same address space as does the
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* mapped RAM in either case. So we will need to create a special
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* mapping for the page table.
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*
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* Load information needed to map the page table. After the ldmia, we
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* will have
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*
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* R1 = The aligned, physical base address of the page table
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* R2 = The aligned, virtual base address of the page table
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* R3 = The MMU flags to use with the .text space mapping
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* R5 = The physical address of the L1 page table (from above)
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*
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* The value in R1 could have been obtained by simply masking R5.
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*/
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adr r0, .LCptinfo /* Address of page table description */
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ldmia r0, {r1, r2, r3} /* Load the page table description */
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/* A single page is sufficient to map the page table */
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orr r0, r1, r3 /* OR MMU flags into physical address */
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str r0, [r5, r2, lsr #18] /* Map using the virtual address as an index */
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#endif
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/* Load information needed to map the .text region. After the ldmia, we
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* will have:
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*
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* R1 = Aligned, physical address of the start of the .text region
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* R2 = Aligned, virtual address of the start of the .text region
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* R3 = MMU flags associated with the .txt region
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* R4 = The number of 1MB sections in the mapping
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* R5 = The physical address of the L1 page table (from above)
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*/
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adr r0, .LCtextinfo /* Address of text info */
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ldmia r0, {r1, r2, r3, r4} /* Load the text description */
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#ifndef CONFIG_IDENTITY_TEXTMAP
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/* Create identity mapping for first MB of the .text section to support
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* this start-up logic executing out of the physical address space. This
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* identity mapping will be removed by .Lvstart (see below). Of course,
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* we would only do this if the physical-virtual mapping is not already
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* the identity mapping.
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*/
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orr r0, r1, r3 /* OR MMU flags into physical address */
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str r0, [r5, r1, lsr #18] /* Identity mapping */
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#endif
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/* Map the entire .text region. We do this before enabling caches so
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* we know that the data will be in place in the data cache. We map the
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* entire text region because we don't know which parts are needed for
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* start-up.
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*
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* The page table base address is in R5. Each 32-bit page table entry
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* maps 1 MB of address space and is indexed by the lower 20 bits of
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* the virtual address in R2
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*/
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add r2, r5, r2, lsr #18 /* R2=Offset page table address */
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/* Now loop until each page table entry has been written for the .text
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* region.
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*/
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.Lpgtextloop:
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orr r0, r1, r3 /* R0: OR MMU flags into physical address */
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subs r4, r4, #1 /* R4: Decrement the section count */
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str r0, [r2], #4 /* Save page table entry, increment page table address */
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add r1, r1, #(1024*1024) /* R1: Increment the physical address */
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bne .Lpgtextloop /* Loop while R4 is non-zero */
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#if defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_SDRAM_DATA)
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/* If we are executing from FLASH, then we will need additional mappings for
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* the primary RAM region that holds the .data, .bss, stack, and heap memory.
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*
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* Here we expect to have:
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* r5 = Address of the base of the L1 table
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*
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* Load information needed to map the .text region. After the ldmia, we
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* will have:
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*
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* R1 = Aligned, physical address of the start of the .text region
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* R2 = Aligned, virtual address of the start of the .text region
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* R3 = MMU flags associated with the .txt region
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* R4 = The number of 1MB sections in the mapping
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* R5 = The physical address of the L1 page table (from above)
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*/
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adr r0, .LCraminfo /* Address of primary RAM info */
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ldmia r0, {r1, r2, r3, r4} /* Load the primary RAM description */
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add r2, r5, r2, lsr #18 /* R2=Offset page table address */
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/* Loop until each page table entry has been written for the primary RAM
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* region.
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*/
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.Lpgramloop:
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orr r0, r1, r3 /* R0: OR MMU flags into physical address */
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subs r4, r4, #1 /* R4: Decrement the section count */
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str r0, [r2], #4 /* Save page table entry, increment page table address */
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add r1, r1, #(1024*1024) /* R1: Increment the physical address */
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bne .Lpgramloop /* Loop while R4 is non-zero */
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#endif /* CONFIG_BOOT_RUNFROMFLASH && !CONFIG_BOOT_SDRAM_DATA */
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* The following logic will set up the ARMv7-A for normal operation.
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*
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* Here we expect to have:
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* r5 = Address of the base of the L1 table
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*/
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/* Invalidate caches and TLBs.
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*
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* NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
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* support a CP15 operation to invalidate the entire data cache. ...
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* In normal usage the only time the entire data cache has to be
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* invalidated is on reset."
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*
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* The instruction cache is virtually indexed and physically tagged but
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* the data cache is physically indexed and physically tagged. So it
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* should not be an issue if the system comes up with a dirty Dcache;
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* the ICache, however, must be invalidated.
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*/
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mov r0, #0
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mcr CP15_TPIDRPRW(r0) /* Initialize percpu reg TPIDRPRW */
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#ifdef CONFIG_ARM_HAVE_MPCORE
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mcr CP15_TLBIALLIS(r0) /* Invalidate the entire unified TLB */
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mcr CP15_BPIALLIS(r0) /* Invalidate entire branch prediction array */
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mcr CP15_ICIALLUIS(r0) /* Invalidate I-cache */
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#else
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mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */
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mcr CP15_TLBIALL(r0,c6)
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mcr CP15_TLBIALL(r0,c5)
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mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
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mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
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#endif
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isb
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/* Load the page table address.
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*
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* NOTES:
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* - Here we assume that the page table address is aligned to at least
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* least a 16KB boundary (bits 0-13 are zero). No masking is provided
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* to protect against an unaligned page table address.
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* - The ARMv7-A has two page table address registers, TTBR0 and 1.
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* Only TTBR0 is used in this implementation but both are initialized.
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*
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* Here we expect to have:
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* r0 = Zero
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* r5 = Address of the base of the L1 table
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*/
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orr r1, r5, #(TTBR0_RGN_WBWA | TTBR0_IRGN0) /* Select cache properties */
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mcr CP15_TTBR0(r1)
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mcr CP15_TTBR1(r1)
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/* Set the TTB control register (TTBCR) to indicate that we are using
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* TTBR0. r0 still holds the value of zero.
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*
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* N : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
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* PD0 : 0=Perform translation table walks using TTBR0
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* PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
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* EAE : 0=Use 32-bit translation system
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*/
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mcr CP15_TTBCR(r0)
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/* Enable the MMU and caches
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* lr = Resume at .Lvstart with the MMU enabled
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*/
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ldr lr, .LCvstart /* Abs. virtual address */
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/* Configure the domain access register (see mmu.h). Only domain 0 is
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* supported and it uses the permissions in the TLB.
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*/
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mov r0, #DACR_CLIENT(0)
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mcr CP15_DACR(r0) /* Set domain access register */
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/* Configure the system control register (see sctrl.h) */
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mrc CP15_SCTLR(r0) /* Get control register */
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/* Clear bits to reset values. This is only necessary in situations like, for
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* example, we get here via a bootloader and the control register is in some
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* unknown state.
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*
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* SCTLR_M Bit 0: Enable the MMU
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* SCTLR_A Bit 1: Strict alignment disabled (reset value)
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* SCTLR_C Bit 2: DCache disabled (reset value)
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*
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* SCTLR_SW Bit 10: SWP/SWPB not enabled (reset value)
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* SCTLR_I Bit 12: ICache disabled (reset value)
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* SCTLR_V Bit 13: Assume low vectors (reset value)
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
|
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* replacement strategy.
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* SCTLR_HA Bit 17: Not supported by A5
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*
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* SCTLR_EE Bit 25: 0=Little endian (reset value).
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* SCTLR_TRE Bit 28: No memory region remapping (reset value)
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* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
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* SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value).
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*/
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bic r0, r0, #(SCTLR_A | SCTLR_C)
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bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR | SCTLR_HA)
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bic r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
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#ifndef CONFIG_SMP
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/* Set bits to enable the MMU
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*
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* SCTLR_M Bit 0: Enable the MMU
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* SCTLR_Z Bit 11: Program flow prediction control always enabled on A5
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*/
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orr r0, r0, #(SCTLR_M)
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#endif
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#ifndef CONFIG_ARCH_CORTEXA5
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orr r0, r0, #(SCTLR_Z)
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#endif
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|
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#ifndef CONFIG_ARCH_LOWVECTORS
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/* Position vectors to 0xffff0000 if so configured.
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*
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* SCTLR_V Bit 13: High vectors
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*/
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orr r0, r0, #(SCTLR_V)
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#endif
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#if defined(CONFIG_ARMV7A_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5)
|
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/* Round Robin cache replacement
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|
*
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* SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
|
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* replacement strategy.
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*/
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orr r0, r0, #(SCTLR_RR)
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#endif
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|
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/* In SMP configurations, the data cache will not be enabled until later
|
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* after SMP cache coherency has been setup.
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|
*/
|
|
|
|
#if !defined(CONFIG_ARMV7A_DCACHE_DISABLE) && !defined(CONFIG_SMP)
|
|
/* Dcache enable
|
|
*
|
|
* SCTLR_C Bit 2: DCache enable
|
|
*/
|
|
|
|
orr r0, r0, #(SCTLR_C)
|
|
#endif
|
|
|
|
#if !defined(CONFIG_ARMV7A_ICACHE_DISABLE) && !defined(CONFIG_SMP)
|
|
/* Icache enable
|
|
*
|
|
* SCTLR_I Bit 12: ICache enable
|
|
*/
|
|
|
|
orr r0, r0, #(SCTLR_I)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARMV7A_ALIGNMENT_TRAP
|
|
/* Alignment abort enable
|
|
*
|
|
* SCTLR_A Bit 1: Strict alignment enabled
|
|
*/
|
|
|
|
orr r0, r0, #(SCTLR_A)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENDIAN_BIG
|
|
/* Big endian mode
|
|
*
|
|
* SCTLR_EE Bit 25: 1=Big endian.
|
|
*/
|
|
|
|
orr r0, r0, #(SCTLR_EE)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARMV7A_AFE_ENABLE
|
|
/* AP[0:2] Permissions model
|
|
*
|
|
* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
|
|
*
|
|
* When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
|
|
* control. When AFE=0, AP[2:0] control access permissions.
|
|
*/
|
|
|
|
orr r0, r0, #(SCTLR_AFE)
|
|
#endif
|
|
|
|
/* Then write the configured control register */
|
|
|
|
mcr CP15_SCTLR(r0) /* Write control reg */
|
|
isb
|
|
.rept 12 /* Cortex A8 wants lots of NOPs here */
|
|
nop
|
|
.endr
|
|
|
|
/* And "jump" to .Lvstart in the newly mapped virtual address space */
|
|
|
|
mov pc, lr
|
|
|
|
/****************************************************************************
|
|
* PC_Relative Data
|
|
****************************************************************************/
|
|
|
|
/* The physical base address of the page table */
|
|
|
|
.type .LCppgtable, %object
|
|
.LCppgtable:
|
|
.long PGTABLE_BASE_PADDR /* Physical start of page table */
|
|
.size .LCppgtable, . -.LCppgtable
|
|
|
|
#ifdef ARMV7A_PGTABLE_MAPPING
|
|
/* Page table region description. The order of these fields must not
|
|
* change because the values are loaded using ldmia:
|
|
*
|
|
* 1) The aligned, physical base address of the page table
|
|
* 2) The aligned, virtual base address of the page table
|
|
* 3) The MMU flags to use with the .text space mapping
|
|
*/
|
|
|
|
.type .LCptinfo, %object
|
|
.LCptinfo:
|
|
.long (PGTABLE_BASE_PADDR & 0xfff00000) /* Physical base address */
|
|
.long (PGTABLE_BASE_VADDR & 0xfff00000) /* Virtual base address */
|
|
.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
|
|
.size .LCptinfo, . -.LCptinfo
|
|
#endif
|
|
|
|
#ifndef CONFIG_ARCH_ROMPGTABLE
|
|
/* Text region description. The order of these fields must not change
|
|
* because the values are loaded using ldmia:
|
|
*
|
|
* 1) The aligned, physical base address of the .text section
|
|
* 2) The aligned, virtual base address of the .text section
|
|
* 3) The MMU flags to use with the .text space mapping
|
|
* 4) The number of 1MB sections in the .text region
|
|
*
|
|
* Values provided for NUTTX_TEXT_* must all be properly aligned to 1MB
|
|
* address boundaries
|
|
*/
|
|
|
|
.type .LCtextinfo, %object
|
|
.LCtextinfo:
|
|
.LCptextbase:
|
|
.long NUTTX_TEXT_PADDR /* Physical base address */
|
|
.long NUTTX_TEXT_VADDR /* Virtual base address */
|
|
.LCtextflags:
|
|
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
|
.long MMU_ROMFLAGS /* MMU flags text section in FLASH/ROM */
|
|
#else
|
|
.long MMU_MEMFLAGS /* MMU flags for text section in RAM */
|
|
#endif
|
|
.long (NUTTX_TEXT_SIZE >> 20) /* Number of 1MB read-execute sections */
|
|
.size .LCtextinfo, . -.LCtextinfo
|
|
|
|
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
|
/* Primary RAM region description. The order of these fields must not change
|
|
* because the values are loaded using ldmia:
|
|
*
|
|
* 1) The aligned, physical base address of the primary RAM section
|
|
* 2) The aligned, virtual base address of the primary RAM section
|
|
* 3) The MMU flags to use with the primary RAM space mapping
|
|
* 4) The number of 1MB sections in the primary RAM region
|
|
*
|
|
* Values provided for NUTTX_RAM_* must all be properly aligned to 1MB
|
|
* address boundaries
|
|
*/
|
|
|
|
.type .LCraminfo, %object
|
|
.LCraminfo:
|
|
.long NUTTX_RAM_PADDR /* Physical base address */
|
|
.long NUTTX_RAM_VADDR /* Virtual base address */
|
|
.long MMU_MEMFLAGS /* MMU flags for primary RAM section */
|
|
.long (NUTTX_RAM_SIZE >> 20) /* Number of 1MB read-execute sections */
|
|
.size .LCraminfo, . -.LCraminfo
|
|
|
|
#endif /* CONFIG_BOOT_RUNFROMFLASH */
|
|
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
|
|
|
/* The virtual start address of the second phase boot logic */
|
|
|
|
.type .LCvstart, %object
|
|
.LCvstart:
|
|
.long .Lvstart
|
|
.size .LCvstart, . -.LCvstart
|
|
|
|
.size __start, .-__start
|
|
|
|
/****************************************************************************
|
|
* Name: .Lvstart
|
|
***************************************************************************/
|
|
|
|
/* The following is executed after the MMU has been enabled. This uses
|
|
* absolute addresses; this is not position independent.
|
|
*/
|
|
.align 5
|
|
.local .Lvstart
|
|
.type .Lvstart, %function
|
|
|
|
.Lvstart:
|
|
|
|
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_IDENTITY_TEXTMAP)
|
|
/* Remove the temporary mapping (if one was made). The following assumes
|
|
* that the total RAM size is > 1Mb and extends that initial mapping to
|
|
* cover additional RAM sections.
|
|
*/
|
|
|
|
ldr r5, .LCvpgtable /* r5=Virtual page table base address */
|
|
ldr r3, .LCptextbase /* r0=Physical base address of .text section */
|
|
mov r0, #0 /* flags + base = 0 */
|
|
str r3, [r5, r3, lsr #18] /* identity mapping */
|
|
#endif /* !CONFIG_ARCH_ROMPGTABLE && !CONFIG_IDENTITY_TEXTMAP */
|
|
|
|
/* Set up the stack pointer and clear the frame pointer */
|
|
|
|
ldr sp, .Lstackpointer
|
|
bic sp, sp, #7 /* Get the stack pointer with 8-byte alignment */
|
|
mov fp, #0
|
|
|
|
#ifndef CONFIG_BOOT_SDRAM_DATA
|
|
/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
|
|
* ready to use. Other memory, such as SDRAM, must be initialized before
|
|
* it can be used. arm_boot() will perform that memory initialization and
|
|
* .bss and .data can be initialized after arm_boot() returns.
|
|
*/
|
|
|
|
bl arm_data_initialize
|
|
#endif
|
|
|
|
/* Perform early C-level, platform-specific initialization. Logic
|
|
* within arm_boot() must configure SDRAM and call arm_data_initialize().
|
|
*/
|
|
|
|
bl arm_boot
|
|
|
|
/* finish busy wait */
|
|
|
|
#ifdef CONFIG_ARMV7A_SMP_BUSY_WAIT
|
|
ldr r0, =CONFIG_ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
|
|
mov r1, #1
|
|
str r1, [r0]
|
|
dsb sy
|
|
#endif
|
|
|
|
/* Finally branch to the OS entry point */
|
|
|
|
mov lr, #0 /* LR = return address (none) */
|
|
b nx_start /* Branch to nx_start */
|
|
.size .Lvstart, .-.Lvstart
|
|
|
|
/***************************************************************************
|
|
* Name: arm_data_initialize
|
|
***************************************************************************/
|
|
|
|
.global arm_data_initialize
|
|
.weak arm_data_initialize
|
|
.type arm_data_initialize, #function
|
|
|
|
arm_data_initialize:
|
|
|
|
/* Zero BSS */
|
|
|
|
adr r0, .Linitparms
|
|
ldmia r0, {r0, r1}
|
|
|
|
mov r2, #0
|
|
1:
|
|
cmp r0, r1 /* Clear up to _bss_end_ */
|
|
strcc r2, [r0], #4
|
|
bcc 1b
|
|
|
|
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
|
/* If the .data section is in a separate, uninitialized address space,
|
|
* then we will also need to copy the initial values of the .data
|
|
* section from the .text region into that .data region. This would
|
|
* be the case if we are executing from FLASH and the .data section
|
|
* lies in a different physical address region OR if we are support
|
|
* on-demand paging and the .data section lies in a different virtual
|
|
* address region.
|
|
*/
|
|
|
|
adr r3, .Ldatainit
|
|
ldmia r3, {r0, r1, r2}
|
|
|
|
2:
|
|
ldr r3, [r0], #4
|
|
str r3, [r1], #4
|
|
cmp r1, r2
|
|
blt 2b
|
|
#endif
|
|
|
|
/* And return to the caller */
|
|
|
|
bx lr
|
|
.size arm_data_initialize, . - arm_data_initialize
|
|
|
|
/***************************************************************************
|
|
* Text-section constants
|
|
***************************************************************************/
|
|
|
|
/* Text-section constants:
|
|
*
|
|
* _sbss is the start of the BSS region (see linker script)
|
|
* _ebss is the end of the BSS region (see linker script)
|
|
*
|
|
* Typical Configuration:
|
|
* The idle task stack usually starts at the end of BSS and is of size
|
|
* CONFIG_IDLETHREAD_STACKSIZE. The heap continues from there until the
|
|
* end of memory. See g_idle_topstack below.
|
|
*
|
|
* In the case where CONFIG_BOOT_SDRAM_DATA is defined, the IDLE stack is
|
|
* in ISRAM, but the heap is in SDRAM beginning at _ebss and extending
|
|
* to the end of SDRAM.
|
|
*/
|
|
|
|
#ifndef CONFIG_ARCH_ROMPGTABLE
|
|
/* The virtual base address of the page table */
|
|
|
|
.type .LCvpgtable, %object
|
|
.LCvpgtable:
|
|
.long PGTABLE_BASE_VADDR /* Virtual start of page table */
|
|
.size .LCvpgtable, . -.LCvpgtable
|
|
|
|
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
|
|
|
.type .Linitparms, %object
|
|
.Linitparms:
|
|
.long _sbss
|
|
.long _ebss
|
|
.size .Linitparms, . -.Linitparms
|
|
|
|
.Lstackpointer:
|
|
.long IDLE_STACK_TOP
|
|
.size .Lstackpointer, . -.Lstackpointer
|
|
|
|
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
|
.type .Ldatainit, %object
|
|
.Ldatainit:
|
|
.long _eronly /* Where .data defaults are stored in FLASH */
|
|
.long _sdata /* Where .data needs to reside in SDRAM */
|
|
.long _edata
|
|
.size .Ldatainit, . -.Ldatainit
|
|
#endif
|
|
|
|
/***************************************************************************
|
|
* Data section variables
|
|
***************************************************************************/
|
|
|
|
/* This global variable is unsigned long g_idle_topstack and is
|
|
* exported from here only because of its coupling to .Lstackpointer
|
|
* above.
|
|
*/
|
|
|
|
.section .rodata, "a"
|
|
.align 4
|
|
.globl g_idle_topstack
|
|
.type g_idle_topstack, object
|
|
|
|
g_idle_topstack:
|
|
|
|
.long IDLE_STACK_TOP
|
|
.size g_idle_topstack, .-g_idle_topstack
|
|
.end
|
|
#endif
|