161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/arm_initialstate.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <string.h>
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#include <nuttx/arch.h>
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#include "arm.h"
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#include "arm_internal.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_initial_state
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*
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* Description:
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* A new thread is being started and a new TCB has been created. This
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* function is called to initialize the processor specific portions of
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* the new TCB.
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*
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* This function must setup the initial architecture registers and/or
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* stack so that execution will begin at tcb->start on the next context
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* switch.
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*
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****************************************************************************/
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void up_initial_state(struct tcb_s *tcb)
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{
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struct xcptcontext *xcp = &tcb->xcp;
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uint32_t cpsr;
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#ifdef CONFIG_ARCH_KERNEL_STACK
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uint32_t *kstack = xcp->kstack;
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#endif
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/* Initialize the initial exception register context structure */
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memset(xcp, 0, sizeof(struct xcptcontext));
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/* Initialize the idle thread stack */
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if (tcb->pid == IDLE_PROCESS_ID)
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{
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tcb->stack_alloc_ptr = (void *)(g_idle_topstack -
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CONFIG_IDLETHREAD_STACKSIZE);
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tcb->stack_base_ptr = tcb->stack_alloc_ptr;
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tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
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#ifdef CONFIG_STACK_COLORATION
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/* If stack debug is enabled, then fill the stack with a
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* recognizable value that we can use later to test for high
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* water marks.
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*/
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arm_stack_color(tcb->stack_alloc_ptr, 0);
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#endif /* CONFIG_STACK_COLORATION */
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return;
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}
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#ifdef CONFIG_ARCH_KERNEL_STACK
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xcp->kstack = kstack;
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#endif
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/* Initialize the context registers to stack top */
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xcp->regs = (void *)((uint32_t)tcb->stack_base_ptr +
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tcb->adj_stack_size -
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XCPTCONTEXT_SIZE);
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/* Initialize the xcp registers */
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memset(xcp->regs, 0, XCPTCONTEXT_SIZE);
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/* Save the initial stack pointer */
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xcp->regs[REG_SP] = (uint32_t)tcb->stack_base_ptr +
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tcb->adj_stack_size;
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/* Save the task entry point */
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xcp->regs[REG_PC] = (uint32_t)tcb->start;
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/* If this task is running PIC, then set the PIC base register to the
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* address of the allocated D-Space region.
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*/
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#ifdef CONFIG_PIC
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if (tcb->dspace != NULL)
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{
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/* Set the PIC base register (probably R10) to the address of the
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* alloacated D-Space region.
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*/
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xcp->regs[REG_PIC] = (uint32_t)tcb->dspace->region;
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}
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#endif
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/* Set supervisor-mode and disable FIQs, regardless of how NuttX is
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* configured and of what kind of thread is being started. That is
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* because all threads, even user-mode threads will start in kernel
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* trampoline at nxtask_start() or pthread_start(). The thread's
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* privileges will be dropped before transitioning to user code.
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*/
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cpsr = PSR_MODE_SYS;
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/* Enable or disable interrupts, based on user configuration */
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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/* Disable interrupts (both IRQs and FIQs) */
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cpsr |= (PSR_I_BIT | PSR_F_BIT);
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#elif defined(CONFIG_ARCH_TRUSTZONE_SECURE)
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/* In tee, we need to disable the IRQ interrupt to make the A core
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* policy consistent with the M core.
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*/
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cpsr |= PSR_I_BIT;
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#elif !defined(CONFIG_ARCH_HIPRI_INTERRUPT)
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/* Leave IRQs enabled (Also FIQs if CONFIG_ARCH_TRUSTZONE_SECURE or
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* CONFIG_ARCH_HIPRI_INTERRUPT is selected)
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*/
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cpsr |= PSR_F_BIT;
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#endif
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#ifdef CONFIG_ARM_THUMB
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cpsr |= PSR_T_BIT;
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#endif
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xcp->regs[REG_CPSR] = cpsr;
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}
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