904b6ff85b
Made fixes to issues from CI. Nxstyle and defconfig syntax. This is a combination of 6 commits. Adding STM32H5 arch files. With comments addressed. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Remove board/docs changes for PR update. Squash commits into one for PR guideline conformity. trying to fix build issues Fix format from review Nucleo-H563ZI support for NSH. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Fix switch default case placement. NXstyle fixes Renaming files rename stm32h5_gpio.x files rename h5 hsi48 files Rename h5 idle file rename stm32h5_irq.c Rename some rcc functions and stm32h5_rcc.c rename stm32h5_rcc.h Rename stm32h5_pwr.x lowputc renames timerisr renames uart renamed rename serial file rename start Turn off the defines that enable DMA on serial remove DMA Kconfig options Remove H5 documentation. Will add in a future PR. Fix styling and defconfig improper syntax.
309 lines
8.5 KiB
C
309 lines
8.5 KiB
C
/****************************************************************************
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* arch/arm/src/stm32h5/stm32_pwr.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "arm_internal.h"
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#include "stm32_pwr.h"
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#include "stm32_rcc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define PWR_TIMEOUT (10 * CONFIG_BOARD_LOOPSPERMSEC)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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static inline uint32_t stm32h5_pwr_getreg(uint16_t offset)
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{
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return getreg32(STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32h5_pwr_putreg(uint16_t offset, uint16_t value)
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{
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putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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*
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* Input Parameters:
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* writable True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* True: The backup domain was previously writable.
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*
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****************************************************************************/
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bool stm32_pwr_enablebkp(bool writable)
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{
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uint16_t regval;
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bool waswritable;
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/* Get the current state of the PWR disable Backup domain register */
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regval = stm32h5_pwr_getreg(STM32_PWR_DBPCR_OFFSET);
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waswritable = ((regval & PWR_DBPCR_DBP) != 0);
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/* Enable or disable the ability to write */
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if (waswritable && !writable)
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{
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/* Disable backup domain access */
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regval &= ~PWR_DBPCR_DBP;
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stm32h5_pwr_putreg(STM32_PWR_DBPCR_OFFSET, regval);
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}
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else if (!waswritable && writable)
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{
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/* Enable backup domain access */
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regval |= PWR_DBPCR_DBP;
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stm32h5_pwr_putreg(STM32_PWR_DBPCR_OFFSET, regval);
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/* Enable does not happen right away */
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up_udelay(4);
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}
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return waswritable;
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}
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/****************************************************************************
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* Name stm32_pwr_adjustvcore
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*
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* Description:
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* Adjusts the voltage used for digital peripherals (V_CORE) before
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* raising or after decreasing the system clock frequency. Compare
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* [RM0481], section 10.7 Dynamic voltage scaling management.
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*
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* Note: Use only for VCore supplied with internal LDO or SMPS.
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* For supplying VCore externally, use stm32_pwr_adjustvos_ext.
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*
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* Input Parameters:
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* sysclock - The frequency in Hertz the system clock will or has been set
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* to.
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*
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****************************************************************************/
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void stm32_pwr_adjustvcore(unsigned sysclock)
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{
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volatile int timeout;
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uint32_t vos_range;
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uint32_t actvos;
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/* Select the applicable V_CORE voltage range depending on the new system
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* clock frequency.
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*/
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DEBUGASSERT(sysclock <= 250000000);
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if (sysclock > 200000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE0;
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}
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else if (sysclock > 150000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE1;
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}
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else if (sysclock > 100000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE2;
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}
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else
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{
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vos_range = PWR_VOSCR_VOS_RANGE3;
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}
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actvos = (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK);
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modreg32(vos_range, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
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if (vos_range > actvos)
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{
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/* Wait until the new V_CORE voltage range has been applied. */
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for (timeout = PWR_TIMEOUT; timeout; timeout--)
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{
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if (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_VOSRDY)
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{
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break;
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}
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}
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DEBUGASSERT(timeout > 0);
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}
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else if (vos_range < actvos)
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{
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/* Wait until the voltage level for the currently used VOS is ready. */
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for (timeout = PWR_TIMEOUT; timeout; timeout--)
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{
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if (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOSRDY)
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{
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break;
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}
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}
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DEBUGASSERT(timeout > 0);
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}
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else
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{
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/* actvos == vos_range. Do nothing. */
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return;
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}
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}
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/****************************************************************************
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* Name stm32_pwr_adjustvos_ext
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*
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* Description:
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* When changing VCore with an external supply, VOS must
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* incrementally select intermediate levels.
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*
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* When increasing the performance:
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* 1. First, voltage scaling must be incremented (for example when
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* changing from VOS3 to VOS0, lower levels must be selected in the
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* VOS[1:0] bits: VOS2, VOS1, and then VOS0).
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* 2. The external voltage can be increased.
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* 3. The system frequency can be increased.
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*
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* When decreasing the performance:
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* 1. The system frequency MUST be decreased.
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* 2. The external voltage MUST be decreased.
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* 3. The voltage scaling can be decremented (for example when changing
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* from VOS1 to VOS3, lower levels must be selected in the VOS[1:0]
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* bits: VOS2, and then VOS3)
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*
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* Input Parameters:
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* sysclock - The frequency in Hertz the system clock will or has been set
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* to.
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*
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****************************************************************************/
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void stm32_pwr_adjustvos_ext(unsigned sysclock)
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{
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uint32_t vos_range;
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uint32_t vos_range_val;
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uint32_t vos_range_set;
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uint32_t actvos_val;
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/* Select the applicable V_CORE voltage range depending on the new system
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* clock frequency.
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*/
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DEBUGASSERT(sysclock <= 250000000);
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if (sysclock > 200000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE0;
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}
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else if (sysclock > 150000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE1;
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}
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else if (sysclock > 100000000)
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{
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vos_range = PWR_VOSCR_VOS_RANGE2;
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}
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else
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{
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vos_range = PWR_VOSCR_VOS_RANGE3;
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}
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vos_range_val = (vos_range & PWR_VOSCR_VOS_MASK) >> PWR_VOSCR_VOS_SHIFT;
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actvos_val = ((getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK) >>
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PWR_VOSSR_ACTVOS_SHIFT);
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if (vos_range_val > actvos_val)
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{
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/* Gradually Increase VOS Scale */
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for (int i = actvos_val; i < vos_range_val; ++i)
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{
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if (i == 0)
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE2;
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}
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else if (i == 1)
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE1;
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}
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else /* (i == 2) */
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE0;
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}
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modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
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up_udelay(1);
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}
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}
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else if (vos_range_val < actvos_val)
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{
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/* Gradually Decrease VOS Scale */
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for (int i = actvos_val; i > vos_range_val; --i)
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{
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if (i == 1)
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE3;
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}
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else if (i == 2)
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE2;
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}
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else /* (i == 3) */
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{
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vos_range_set = PWR_VOSCR_VOS_RANGE1;
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}
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modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
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up_udelay(1);
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}
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}
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else
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{
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/* actvos == new vos. Do nothing. */
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return;
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}
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}
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