904b6ff85b
Made fixes to issues from CI. Nxstyle and defconfig syntax. This is a combination of 6 commits. Adding STM32H5 arch files. With comments addressed. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Remove board/docs changes for PR update. Squash commits into one for PR guideline conformity. trying to fix build issues Fix format from review Nucleo-H563ZI support for NSH. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Fix switch default case placement. NXstyle fixes Renaming files rename stm32h5_gpio.x files rename h5 hsi48 files Rename h5 idle file rename stm32h5_irq.c Rename some rcc functions and stm32h5_rcc.c rename stm32h5_rcc.h Rename stm32h5_pwr.x lowputc renames timerisr renames uart renamed rename serial file rename start Turn off the defines that enable DMA on serial remove DMA Kconfig options Remove H5 documentation. Will add in a future PR. Fix styling and defconfig improper syntax.
339 lines
13 KiB
C
339 lines
13 KiB
C
/****************************************************************************
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* boards/arm/stm32h5/nucleo-h563zi/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The NUCLEO-H563ZI-Q supports both HSE and LSE crystals (X2 and X3).
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* However, as shipped, the X3 crystal is not populated. Therefore the
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* Nucleo-H563ZI-Q will need to run off the 16MHz HSI clock, or the
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* 32kHz-synced CSI. This configuration uses the CSI.
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*
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* System Clock source : PLL (CSI)
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* SYSCLK(Hz) : 250000000 Determined by PLL1 configuration
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* HCLK(Hz) : 250000000 (STM32_RCC_CFGR_HPRE) (Max 250MHz)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 250MHz)
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* APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 250MHz)
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* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 250MHz)
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* CSI Frequency(Hz) : 4000000 (nominal)
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* PLL1M : 2 (STM32_PLL1CFGR_PLLM)
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* PLL1N : 125 (STM32_PLL1CFGR_PLLN)
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* PLL1P : 0 (STM32_PLL1CFGR_PLLP)
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* PLL1Q : 0 (STM32_PLL1CFGR_PLLQ)
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* PLL1R : 1 (STM32_PLL1CFGR_PLLR)
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* PLL2M : 2 (STM32_PLL2CFGR_PLLM)
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* PLL2N : 125 (STM32_PLL2CFGR_PLLN)
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* PLL2P : 0 (STM32_PLL2CFGR_PLLP)
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* PLL2Q : 0 (STM32_PLL2CFGR_PLLQ)
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* PLL2R : 1 (STM32_PLL2CFGR_PLLR)
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* PLL3M : 2 (STM32_PLL3CFGR_PLLM)
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* PLL3N : 125 (STM32_PLL3CFGR_PLLN)
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* PLL3P : 0 (STM32_PLL3CFGR_PLLP)
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* PLL3Q : 0 (STM32_PLL3CFGR_PLLQ)
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* PLL3R : 1 (STM32_PLL3CFGR_PLLR)
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* Flash Latency(WS) : 5
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*/
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/* HSI - 32 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* CSI - 4 MHz, autotrimmed via LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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* SYSCLK = 250 MHz
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*/
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#define STM32_SYSCLK_FREQUENCY 250000000ul
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#define STM32_HSI_FREQUENCY 32000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_LSE_FREQUENCY 32768
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#define STM32_BOARD_USEHSI 1
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#define STM32_CR_HSIDIV RCC_CR_HSIDIV(1)
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/* prescaler common to all PLL inputs */
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/* 'main' PLL1 config; we use this to generate our system clock */
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/* Use 32 MHz HSI, set M to 2, N to 15, FRAC to 0x1400 (5120)
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* SYSCLK = (32000000 / 2) * (15 + (5120/8192)) = 250000000
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*/
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#define STM32_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN
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#define STM32_PLL1CFGR_PLL1VCOSEL 0
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#define STM32_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_8_16M
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#define STM32_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(2)
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#define STM32_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(15)
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#define STM32_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P(1)
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#define STM32_PLL1CFGR_PLL1P_ENABLED 1
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#define STM32_PLL1DIVR_PLL1Q 0
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#undef STM32_PLL1CFGR_PLL1Q_ENABLED
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#define STM32_PLL1DIVR_PLL1R 0
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#undef STM32_PLL1CFGR_PLL1R_ENABLED
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#define STM32_PLL1FRACR_PLL1FRACN 5120ul
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/* PLL2 config */
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#define STM32_PLL2CFGR_PLL2M RCC_PLL2CFGR_PLL2M(4)
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#define STM32_PLL2CFGR_PLL2FRACEN RCC_PLL2CFGR_PLL2FRACEN
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#define STM32_PLL2CFGR_PLL2VCOSEL RCC_PLL2CFGR_PLL2VCOSEL
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#define STM32_PLL2CFGR_PLL2RGE RCC_PLL2CFGR_PLL2RGE_8_16M
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#define STM32_PLL2DIVR_PLL2N RCC_PLL2DIVR_PLL2N(15)
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#define STM32_PLL2DIVR_PLL2P RCC_PLL2DIVR_PLL2P(1)
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#define STM32_PLL2CFGR_PLL2P_ENABLED
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#define STM32_PLL2DIVR_PLL2Q 0
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#undef STM32_PLL2CFGR_PLL2Q_ENABLED
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#define STM32_PLL2DIVR_PLL2R 0
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#undef STM32_PLL2CFGR_PLL2R_ENABLED
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#define STM32_PLL2FRACR_PLL2FRACN 5120ul
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/* PLL3 config */
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#define STM32_PLL3CFGR_PLL3M RCC_PLL3CFGR_PLL3M(4)
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#define STM32_PLL3CFGR_PLL3FRACEN RCC_PLL3CFGR_PLL3FRACEN
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#define STM32_PLL3CFGR_PLL3VCOSEL RCC_PLL3CFGR_PLL3VCOSEL
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#define STM32_PLL3CFGR_PLL3RGE RCC_PLL3CFGR_PLL3RGE_8_16M
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#define STM32_PLL3DIVR_PLL3N RCC_PLL3DIVR_PLL3N(15)
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#define STM32_PLL3DIVR_PLL3P RCC_PLL3DIVR_PLL3P(1)
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#define STM32_PLL3CFGR_PLL3P_ENABLED
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#define STM32_PLL3DIVR_PLL3Q 0
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#undef STM32_PLL3CFGR_PLL3Q_ENABLED
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#define STM32_PLL3DIVR_PLL3R 0
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#undef STM32_PLL3CFGR_PLL3R_ENABLED
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#define STM32_PLL3FRACR_PLL3FRACN 5120ul
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/* Enable CLK48; get it from HSI48 */
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#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
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# define STM32H5_USE_CLK48 1
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# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
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# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE
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#endif
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/* Enable LSE (for the RTC) */
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#define STM32_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* Configure the APB1 prescaler */
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#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1 /* PCLK1 = HCLK / 1 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK1 /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Configure the APB3 prescaler */
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#define STM32_RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_HCLK1 /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
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#define STM32_APB3_LPTIM1_CLKIN (STM32_PCLK3_FREQUENCY)
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#define STM32_APB3_LPTIM3_CLKIN (STM32_PCLK3_FREQUENCY)
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#define STM32_APB3_LPTIM4_CLKIN (STM32_PCLK3_FREQUENCY)
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#define STM32_APB3_LPTIM5_CLKIN (STM32_PCLK3_FREQUENCY)
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#define STM32_APB3_LPTIM6_CLKIN (STM32_PCLK3_FREQUENCY)
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/* The timer clock frequencies are automatically defined by hardware. If the
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* APB prescaler equals 1, the timer clock frequencies are set to the same
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* frequency as that of the APB domain. Otherwise they are set to twice.
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM12_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM13_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM14_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_LPTIM6_FREQUENCY STM32_HCLK_FREQUENCY
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/* Configure the Kernel clocks */
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/* DMA Channel/Stream Selections ********************************************/
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/* Alternate function pin selections ****************************************/
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/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder
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* bridges SB123 to SB130 are re-worked accordingly).
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*/
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#define GPIO_USART3_RX GPIO_USART3_RX_4 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_4 /* PD8 */
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/* LED definitions **********************************************************/
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/* The Nucleo board has numerous LEDs but only three, LD1 a Green LED,
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* LD2 a Yellow LED, and LD3 a Red LED, that can be controlled by software.
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* The following definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_YELLOW BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-
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* related events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions *******************************************************/
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/* The Nucleo-H563ZI supports one button: Pushbutton B1, labeled "User", is
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* connected to GPIO PC13.
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* A high value will be sensed when the button is pressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_board_initialize
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*
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* Description:
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* All STM32H5 architectures must provide the following entry point.
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* This entry point is called early in the initialization -- after all
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* memory has been configured and mapped but before any devices
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* have been initialized.
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*
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****************************************************************************/
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void stm32_board_initialize(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */
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