926a19217e
Sv39 is the only mode supported for now. However, it should be trivial to extend the driver to support the other modes (including Sv32) as well. The driver is tested with mpfs only, but it should work with any riscv implementation.
220 lines
5 KiB
ArmAsm
Executable file
220 lines
5 KiB
ArmAsm
Executable file
/****************************************************************************
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* arch/risc-v/src/mpfs/mpfs_head.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/csr.h>
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#include <arch/irq.h>
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#include "chip.h"
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#include "mpfs_memorymap.h"
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#include "riscv_internal.h"
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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/* Imported symbols */
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.extern __trap_vec
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.section .text
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.global __start
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__start:
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/* Disable all interrupts (i.e. timer, external) in mie */
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csrw mie, zero
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csrw mip, zero
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/* Initialize the Machine Trap Vector */
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la t0, __trap_vec
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csrw mtvec, t0
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/* Make sure that mtvec is updated before continuing */
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1:
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csrr t1, mtvec
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bne t0, t1, 1b
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/* mscratch must be init to zero- we are not using scratch memory */
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csrw mscratch, zero
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csrw mcause, zero
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csrw mepc, zero
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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/* Skip delegation register, mmu and floating point initializations if E51 */
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csrr a0, mhartid
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beqz a0, .skip_e51
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/* Init delegation registers, mideleg, medeleg, if a U54
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* These are not initialised by the hardware and come up in a random state
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*/
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csrw mideleg, 0
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csrw medeleg, 0
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/* Disable MMU if not done already */
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csrw satp, zero
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fence
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/* invalid all MMU TLB Entry */
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sfence.vma x0, x0
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/* enable FPU and accelerator if present, setting ignored on E51
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* 15,16 = MSTATUS_XS, 17,18 = MSTATUS_MPRV
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* not defined on riscv-v/include/csr.h
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*/
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/* li t0, MSTATUS_FS_DIRTY | (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18) */
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li t0, 0x00006000 | 0x00018000 /* MSTATUS_FS | MSTATUS_XS */
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csrs mstatus, t0
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/* Init floating point control register to zero */
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#ifdef __riscv_flen
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fscsr x0
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#endif
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.skip_e51:
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#ifdef CONFIG_MPFS_BOOTLOADER
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/* Set all but the boot hart into wfi */
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li a1, CONFIG_MPFS_BOOT_HART
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beq a0, a1, .continue_boot
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/* Enable IRQ_M_SOFT */
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li a2, (1U << 3)
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csrw mie, a2 /* Set MSIE bit to receive IPI */
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/* flush the instruction cache */
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fence.i
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.wait_boot:
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wfi
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/* Only start if MIP_MSIP is set. Breakpoints in the debugger (halt)
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* will wakeup wfi, so we will check again that we actually got the soft
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* interrupt
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*/
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csrr a2, mip
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andi a2, a2, (1U << 3) /* MIP_MSIP */
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beqz a2, .wait_boot
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/* Disable and clear all interrupts (the sw interrupt) */
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li a2, 0x00000008 /* MSTATUS_MIE */
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csrc mstatus, a2
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csrw mie, zero
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csrw mip, zero
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#ifdef CONFIG_MPFS_OPENSBI
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jal mpfs_opensbi_prepare_hart
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#else
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/* Jump to app (TODO: remove fixed address) */
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li a1, 0x80000000
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jr a1
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#endif
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.continue_boot:
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#endif
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/* Set stack pointer to the idle thread stack */
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la sp, MPFS_IDLESTACK_TOP
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/* initialize global pointer, global data
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* The __global_pointer is allocated in the linker script.
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* It points to a location between _sdata and _edata as the offsets used in the gp are +/- 2k
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* See https://www.sifive.com/blog/2017/08/28/all-aboard-part-3-linker-relaxation-in-riscv-toolchain/
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* see: http://www.rowleydownload.co.uk/arm/documentation/gnu/as/RISC_002dV_002dDirectives.html
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*/
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/* Jump to __mpfs_start with mhartid in a0 */
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jal __mpfs_start
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/* We shouldn't return from __mpfs_start
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* in case of return, loop forever. nop's added so can be seen in debugger
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*/
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1:
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nop
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nop
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j 1b
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.global _init
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.global _fini
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_init:
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_fini:
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/* These don't have to do anything since we use init_array/fini_array. */
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ret
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