880c8e5d26
Add support for Intel IGB type of network cards. Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
544 lines
32 KiB
C
544 lines
32 KiB
C
/*****************************************************************************
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* drivers/net/igb.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*****************************************************************************/
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#ifndef __DRIVERS_NET_IGB_H
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#define __DRIVERS_NET_IGB_H
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <stdint.h>
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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/* General registers */
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#define IGB_CTRL (0x0000) /* Device Control Register */
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#define IGB_STATUS (0x0008) /* Device Status Register */
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#define IGB_CTRLEXT (0x0018) /* Extended Device Control Register */
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#define IGB_MDIC (0x0020) /* MDI Control Register */
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#define IGB_SERDESCTL (0x0024) /* Serdes_ana */
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#define IGB_FCAL (0x0028) /* Flow Control Address Low */
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#define IGB_FCAH (0x002c) /* Flow Control Address High */
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#define IGB_FCT (0x0030) /* Flow Control Type */
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#define IGB_CONNSW (0x0034) /* Copper/Fiber Switch Control */
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#define IGB_VET (0x0038) /* VLAN Ether Type */
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#define IGB_FCTTV (0x0170) /* Flow Control Transmit Timer Value */
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#define IGB_LEDCTL (0x0e00) /* LED Control */
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#define IGB_I2CCM (0x1028) /* SFP I2C Command */
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#define IGB_I2CPARAMS (0x102c) /* SFP I2C Parameter */
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#define IGB_WDSTP (0x1040) /* Watchdog Setup Register */
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#define IGB_WDSWSTS (0x1044) /* Watchdog Software */
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#define IGB_FRTIMER (0x1048) /* Free Running Timer */
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#define IGB_TCPTIMER (0x104c) /* TCP Timer */
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#define IGB_DCAID (0x5b70) /* DCA Requester ID Information Register */
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#define IGB_SWSM (0x5b50) /* Software Semaphore Register */
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#define IGB_FWSM (0x5b54) /* Firmware Semaphore Register */
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#define IGB_SWFWSYNC (0x5b5c) /* Software-Firmware Synchronization */
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/* Flash/EEPROM Registers */
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#define IGB_EEC (0x00010) /* EEPROM/FLASH Control Register */
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#define IGB_EERD (0x00014) /* EEPROM Read Register */
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#define IGB_FLA (0x0001c) /* Flash Access Register */
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#define IGB_EEMNGCTL (0x01010) /* MNG EEPROM Control Register */
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#define IGB_EEMNGDATA (0x01014) /* MNG EEPROM Read/Write data */
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#define IGB_FLMNGCTL (0x01018) /* MNG Flash Control Register */
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#define IGB_FLMNGDATA (0x0101c) /* MNG Flash Read data */
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#define IGB_FLMNGCNT (0x01020) /* MNG Flash Read Counter */
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#define IGB_EEARBC (0x01024) /* EEPROM Auto Read Bus Control */
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#define IGB_FLASHOP (0x0103c) /* Flash Opcode Register */
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#define IGB_EEDIAG (0x01038) /* EEPROM Diagnostic */
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#define IGB_VPDDIAG (0x01060) /* VPD Diagnostic */
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/* Interrupt registers */
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#define IGB_ICR (0x1500) /* Interrupt Cause Read */
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#define IGB_ICS (0x1504) /* Interrupt Cause Set */
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#define IGB_IMS (0x1508) /* Interrupt Mask Set */
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#define IGB_IMC (0x150c) /* Interrupt Mask Clear */
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#define IGB_IAM (0x1510) /* Interrupt Acknowledge Auto–Mask */
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#define IGB_EICS (0x1520) /* Extended Interrupt Cause Set */
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#define IGB_EIMS (0x1524) /* Extended Interrupt Mask Set/Read */
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#define IGB_EIMC (0x1528) /* Extended Interrupt Mask Clear */
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#define IGB_EIAC (0x152c) /* Extended Interrupt Auto Clear */
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#define IGB_EIAM (0x1530) /* Extended Interrupt Auto Mask */
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#define IGB_EICR (0x1580) /* Extended Interrupt Cause Read */
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#define IGB_IVAR0 (0x1700) /* Interrupt Vector Allocation Registers */
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#define IGB_IVARMSC (0x1740) /* Interrupt Vector Allocation Registers - MISC */
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#define IGB_EITR0 (0x1680) /* Extended Interrupt Throttling Rate 0 - 24 */
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#define IGB_GPIE (0x1514) /* General Purpose Interrupt Enable */
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#define IGB_PBACL (0x5b68) /* MSI-X PBA Clear */
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/* Receive registers */
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#define IGB_RCTL (0x0100) /* Receive Control */
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#define IGB_FCRTL0 (0x2160) /* Flow Control Receive Threshold Low */
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#define IGB_PSRCTL (0x2170) /* Packet Split Receive Control Register */
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#define IGB_FCRTH0 (0x2168) /* Flow Control Receive Threshold High */
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#define IGB_RXPBSIZE (0x2404) /* Rx Packet Buffer Size */
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#define IGB_PBRWAC (0x24e8) /* Rx Packet Buffer wrap around counter */
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#define IGB_FCRTV (0x2460) /* Flow Control Refresh Threshold Value */
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#define IGB_DRXMXOD (0x2540) /* DMA RX Max Total Allow Size Requests */
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#define IGB_RDBAL0 (0xc000) /* Tx Descriptor Base Address Low */
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#define IGB_RDBAH0 (0xc004) /* Rx Descriptor Base Address High */
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#define IGB_RDLEN0 (0xc008) /* Rx Descriptor Length */
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#define IGB_SRRCTL0 (0xc00c) /* Split and Replication Receive Control Register Queue */
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#define IGB_RDH0 (0xc010) /* Rx Descriptor Head */
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#define IGB_RDT0 (0xc018) /* Rx Descriptor Tail */
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#define IGB_RXDCTL0 (0xc028) /* Receive Descriptor Control Queue */
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#define IGB_RXCTL0 (0xc014) /* Receive Queue DCA CTRL Register */
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#define IGB_RXCSUM (0x5000) /* Receive Checksum Control */
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#define IGB_RLPML (0x5004) /* Receive Long packet maximal length */
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#define IGB_RFCTL (0x5008) /* Receive Filter Control Register */
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#define IGB_MTA (0x5200) /* Multicast Table Array (n) */
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#define IGB_RAL (0x5400) /* Receive Address Low */
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#define IGB_RAH (0x5404) /* Receive Address Low */
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#define IGB_PSRTYPE0 (0x5480) /* Packet Split Receive type (n) */
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#define IGB_RPLPSRTYPE (0x54c0) /* Replicated Packet Split Receive type */
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#define IGB_VTCTL (0x5818) /* Next Generation VMDq Control register */
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#define IGB_VFTA0 (0x5600) /* VLAN Filter Table Array (n) */
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#define IGB_MRQC (0x5818) /* Multiple Receive Queues Command */
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#define IGB_RETA (0x5c00) /* Redirection Table */
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#define IGB_RSSRK (0x5c80) /* RSS Random Key Register */
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/* Transmit registers */
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#define IGB_TXPBSIZE (0x3404) /* Transmit Packet Buffer Size */
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#define IGB_PBTWAC (0x34e8) /* Tx Packet Buffer wrap around counter */
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#define IGB_TCTL (0x0400) /* Transmit Control */
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#define IGB_TCTLEXT (0x0404) /* Transmit Control Extended */
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#define IGB_TIPG (0x0410) /* Transmit IPG Register */
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#define IGB_RETXCTL (0x041c) /* Retry Buffer Control */
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#define IGB_DTXCTL (0x3590) /* DMA Tx Control */
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#define IGB_DTXTCPFLGL (0x359c) /* DMA Tx TCP Flags Control Low */
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#define IGB_DTXTCPFLGH (0x35a0) /* DMA Tx TCP Flags Control High */
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#define IGB_DTXMXSZRQ (0x3540) /* DMA Tx Max Total Allow Size Requests */
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#define IGB_DTXMXPKTSZ (0x355c) /* DMA Tx Max Allowable Packet Size */
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#define IGB_TDBAL0 (0xe000) /* Tx Descriptor Base Low */
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#define IGB_TDBAH0 (0xe004) /* Tx Descriptor Base High*/
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#define IGB_TDLEN0 (0xe008) /* Tx Descriptor Ring Length */
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#define IGB_TDH0 (0xe010) /* Tx Descriptor Head */
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#define IGB_TDT0 (0xe018) /* Tx Descriptor Tail */
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#define IGB_TXDCTL0 (0xe028) /* Transmit Descriptor Control Queue */
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#define IGB_TXCTL0 (0xe014) /* Tx DCA CTRL Register Queue */
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#define IGB_TDWBAL0 (0xe038) /* Transmit Descriptor WB Address Low Queue */
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#define IGB_TDWBAH0 (0xe03c) /* Transmit Descriptor WB Address High Queue */
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/* TODO: Filters */
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#define IGB_ETQF0 (0x5cb0) /* EType Queue Filter */
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#define IGB_IMIR0 (0x5a80) /* Immediate Interrupt Rx */
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#define IGB_IMIREXT0 (0x5aa9) /* Immediate Interrupt Rx Extended */
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#define IGB_IMIRVP (0x5ac0) /* Immediate Interrupt Rx VLAN Priority */
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#define IGB_SAQF0 (0x5980) /* Source Address Queue Filter */
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#define IGB_DAQF0 (0x59a0) /* Destination Address Queue Filter */
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#define IGB_SPQF0 (0x59c0) /* Source Port Queue Filter */
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#define IGB_FTQF0 (0x59e0) /* Five-Tuple Queue Filter */
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#define IGB_SYNQF (0x55fc) /* SYN Packet Queue Filter */
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/* TODO: Virtualization */
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/* Statistic registers */
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#define IGB_CRCERRS (0x04000) /* CRC Error Count */
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#define IGB_ALGNERRC (0x04004) /* Alignment Error Count */
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#define IGB_SYMERRS (0x04008) /* Symbol Error Count */
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#define IGB_RXERRC (0x0400c) /* RX Error Count */
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#define IGB_MPC (0x04010) /* Missed Packets Count */
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#define IGB_SCC (0x04014) /* Single Collision Count */
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#define IGB_ECOL (0x04018) /* Excessive Collisions Count */
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#define IGB_MCC (0x0401c) /* Multiple Collision Count */
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#define IGB_LATECOL (0x04020) /* Late Collisions Count */
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#define IGB_COLC (0x04028) /* Collision Count */
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#define IGB_DC (0x04030) /* Defer Count */
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#define IGB_TNCRS (0x04034) /* Transmit with No CRS */
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#define IGB_HTDPMC (0x0403c) /* Host Transmit Discarded Packets by MAC Count */
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#define IGB_RLEC (0x04040) /* Receive Length Error Count */
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#define IGB_CBRDPC (0x04044) /* Circuit Breaker Rx dropped packet */
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#define IGB_XONRXC (0x04048) /* XON Received Count */
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#define IGB_XONTXC (0x0404c) /* XON Transmitted Count */
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#define IGB_XOFFRXC (0x04050) /* XOFF Received Count */
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#define IGB_XOFFTXC (0x04054) /* XOFF Transmitted Count */
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#define IGB_FCRUC (0x04058) /* FC Received Unsupported Count */
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#define IGB_PRC64 (0x0405c) /* Packets Received [64 Bytes] Count */
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#define IGB_PRC127 (0x04060) /* Packets Received [65–127 Bytes] Count */
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#define IGB_PRC255 (0x04064) /* Packets Received [128–255 Bytes] */
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#define IGB_PRC511 (0x04068) /* Packets Received [256–511 Bytes] */
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#define IGB_PRC1023 (0x0406c) /* Packets Received [512–1023 Bytes] */
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#define IGB_PRC1522 (0x04070) /* Packets Received [1024 to Max Bytes] */
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#define IGB_GPRC (0x04074) /* Good Packets Received Count */
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#define IGB_BPRC (0x04078) /* Broadcast Packets Received Count */
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#define IGB_MPRC (0x0407c) /* Multicast Packets Received Count */
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#define IGB_GPTC (0x04080) /* Good Packets Transmitted Count */
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#define IGB_GORCL (0x04088) /* Good Octets Received Count Low */
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#define IGB_GORCH (0x0408c) /* Good Octets Received Count High */
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#define IGB_GOTCL (0x04090) /* Good Octets Transmitted Count Low */
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#define IGB_GOTCH (0x04094) /* Good Octets Transmitted Count High */
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#define IGB_RNBC (0x040a0) /* Receive No Buffers Count */
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#define IGB_RUC (0x040a4) /* Receive Undersize Count */
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#define IGB_RFC (0x040a8) /* Receive Fragment Count */
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#define IGB_ROC (0x040ac) /* Receive Oversize Count */
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#define IGB_RJC (0x040b0) /* Receive Jabber Count */
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#define IGB_MNGPRC (0x040b4) /* Management Packets Received Count */
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#define IGB_MPDC (0x040b8) /* Management Packets Dropped Count */
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#define IGB_MNGPTC (0x040bc) /* Management Packets Transmitted Count */
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#define IGB_BMNGPRC (0x0414c) /* BMC Management Packets Receive Count */
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#define IGB_BMPDC (0x04140) /* BMC Management Packets Dropped Count */
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#define IGB_BMNGPTC (0x04144) /* BMC Management Packets Transmitted Count */
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#define IGB_TORL (0x040c0) /* Total Octets Received */
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#define IGB_TORH (0x040c4) /* Total Octets Received */
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#define IGB_TOTL (0x040c8) /* Total Octets Transmitted */
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#define IGB_TOTH (0x040cc) /* Total Octets Transmitted */
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#define IGB_TPR (0x040d0) /* Total Packets Received */
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#define IGB_TPT (0x040d4) /* Total Packets Transmitted */
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#define IGB_PTC64 (0x040d8) /* Packets Transmitted [64 Bytes] Count */
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#define IGB_PTC127 (0x040dc) /* Packets Transmitted [65–127 Bytes] Count */
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#define IGB_PTC255 (0x040e0) /* Packets Transmitted [128–255 Bytes] Count */
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#define IGB_PTC511 (0x040e4) /* Packets Transmitted [256–511 Bytes] Count */
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#define IGB_PTC1023 (0x040e8) /* Packets Transmitted [512–1023 Bytes] Count */
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#define IGB_PTC1522 (0x040ec) /* Packets Transmitted [Greater than 1024 Bytes] Count */
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#define IGB_MCPTC (0x040f0) /* Multicast Packets Transmitted Count */
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#define IGB_BPTC (0x040f4) /* Broadcast Packets Transmitted Count */
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/* ... missing registers */
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/* Wake Up and Proxying */
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#define IGB_WUC (0x5800) /* Wake Up Control Register */
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#define IGB_WUFC (0x5808) /* Wake Up Filter Control Register */
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#define IGB_WUS (0x5810) /* Wake Up Status Register */
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#define IGB_WUPL (0x5900) /* Wake Up Packet Length */
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#define IGB_WUPM (0x5a00) /* Wake Up Packet Memory */
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#define IGB_FHFT (0x9000) /* Flexible Host Filter Table registers */
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#define IGB_FHFTEXT (0x9a00) /* Flexible Host Filter Table registers extended */
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/* TODO: Management Register */
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/* TODO: PCIe */
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/* Diagnostic */
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#define IGB_RDFH (0x2410) /* RX Data FIFO Head */
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#define IGB_RDFT (0x2418) /* RX Data FIFO Tail */
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#define IGB_RDFHS (0x2420) /* RX Data FIFO Head Saved */
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#define IGB_RDFTS (0x2428) /* RX Data FIFO Tail Saved */
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#define IGB_RDFPC (0x2430) /* Receive Data FIFO Packet Count */
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#define IGB_RPBECCSTS (0x245c) /* Receive Packet buffer ECC control */
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#define IGB_TPBECCSTS (0x345C) /* Transmit Packet buffer ECC control */
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#define IGB_FCSTS0 (0x2464) /* Flow Control Status */
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#define IGB_RDHESTS (0x25c0) /* Rx Descriptor Handler ECC status */
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#define IGB_TDHESTS (0x35c0) /* Tx Descriptor Handler ECC status */
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#define IGB_TDFH (0x3410) /* TX Data FIFO Head */
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#define IGB_TDFT (0x3418) /* TX Data FIFO Tail */
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#define IGB_TDFHS (0x3420) /* TX Data FIFO Head Saved */
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#define IGB_TDFTS (0x3428) /* TX Data FIFO Tail Saved */
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#define IGB_TDFPC (0x3430) /* Transmit Data FIFO Packet Count */
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#define IGB_TDHMP (0x35fc) /* Tx Descriptor Handler Memory Page Number */
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#define IGB_CIRC (0x0f00) /* Circuits Control */
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#define IGB_TXBDC (0x35e0) /* Tx DMA Performance Burst and Descriptor Count */
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#define IGB_TXIDLE (0x35e4) /* Tx DMA Performance Idle Count */
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#define IGB_RXBDC (0x25e0) /* Tx DMA Performance Burst and Descriptor Count */
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#define IGB_RXIDLE (0x25E4) /* Tx DMA Performance Idle Count */
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/* TODO: PCS */
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/* TODO: Time Sync */
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/* TODO: MACSec */
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/* TODO: IPSec */
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/* Device Control Register */
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#define IGB_CTRL_FD (1 << 0) /* Bit 0: Full-Duplex */
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/* Bit 1: Reserved */
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#define IGB_CTRL_GIOMDIS (1 << 2) /* Bit 2: GIO Master Enable Status */
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#define IGB_CTRL_LRST (1 << 3) /* Bit 3: Link Reset */
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/* Bits 4-5: Reserved */
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#define IGB_CTRL_SLU (1 << 6) /* Bit 6: Set Link Up */
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#define IGB_CTRL_ILOS (1 << 7) /* Bit 7: Invert Loss-of-Signal */
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#define IGB_CTRL_SPEED_SHIFT (8) /* Bits 8-9: Speed selection */
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#define IGB_CTRL_SPEED_MASK (3 << IGB_CTRL_SPEED_SHIFT)
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# define IGB_CTRL_SPEED_10MBS (0 << IGB_CTRL_SPEED_SHIFT)
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# define IGB_CTRL_SPEED_100MBS (1 << IGB_CTRL_SPEED_SHIFT)
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# define IGB_CTRL_SPEED_1000MBS (2 << IGB_CTRL_SPEED_SHIFT)
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/* Bit 10: Reserved */
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#define IGB_CTRL_FRCSPD (1 << 11) /* Bit 11: Force Speed */
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#define IGB_CTRL_FRCDPLX (1 << 12) /* Bit 12: Force Duplex */
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/* Bits 13-15: Reserved */
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#define IGB_CTRL_SDP0_GPIEN (1 << 16) /* Bit 16: GPI Detection Enable for SDP0 */
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#define IGB_CTRL_SDP1_GPIEN (1 << 17) /* Bit 17: GPI Detection Enable for SDP1 */
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#define IGB_CTRL_SDP0_DATA (1 << 18) /* Bit 18: SDP0 Data Value */
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#define IGB_CTRL_SDP1_DATA (1 << 19) /* Bit 19: SDP1 Data Value */
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#define IGB_CTRL_ADVD3WUC (1 << 20) /* Bit 20: D3Cold Wakeup Capability Advertisement Enable */
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#define IGB_CTRL_SDP0_WDE (1 << 21) /* Bit 21: SDP0 Used for Watchdog Indication */
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#define IGB_CTRL_SDP0_IODIR (1 << 22) /* Bit 22: SDP0 Pin Directionality */
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#define IGB_CTRL_SDP1_IODIR (1 << 23) /* Bit 23: SDP1 Pin Directionality */
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/* Bits 24-25: Reserved */
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#define IGB_CTRL_RST (1 << 26) /* Bit 26: Device Reset */
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#define IGB_CTRL_RFCE (1 << 27) /* Bit 27: Receive Flow Control Enable */
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#define IGB_CTRL_TFCE (1 << 28) /* Bit 28: Transmit Flow Control Enable */
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/* Bit 29: Reserved */
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#define IGB_CTRL_VME (1 << 30) /* Bit 30: VLAN Mode Enable */
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#define IGB_CTRL_PHYRST (1 << 31) /* Bit 31: PHY Reset */
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/* Device Status Regiuster */
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#define IGB_STATUS_FD (1 << 0) /* Bit 0: Full Duplex */
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#define IGB_STATUS_LU (1 << 1) /* Bit 1: Link Up */
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#define IGB_STATUS_LANID_SHIFT (2) /* Bit 2-3: LAN ID*/
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#define IGB_STATUS_TXOFF (1 << 4) /* Bit 4: Transmission Paused */
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/* Bit 5: Reserved */
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#define IGB_STATUS_SPEED_SHFIT (6) /* Bits 6-7: Link speed setting */
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#define IGB_STATUS_ASDV_SHFIT (8) /* Bits 8-9: Auto-Speed Detection Value. */
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#define IGB_STATUS_PHYRA (10) /* Bit 10: PHY Reset Asserted */
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/* Bits 11-13: Reserved */
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#define IGB_STATUS_NVFS_SHFIT (14) /* Bits 14-17: Num VFs in the IOV capability */
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#define IGB_STATUS_IOVMODE (18) /* Bit 18: VF enable (VFE) bit in the IOV */
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#define IGB_STATUS_GIOM (19) /* Bit 19: GIO Master Disable bit state */
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/* Bits 20-30: Reserved */
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#define IGB_STATUS_DMACGE (31) /* Bit 31: DMA clock gating Enable bit */
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/* Receive Address High */
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#define IGB_RAH_RAH_MASK (0xffff) /* Bits 0-15: Receive address High */
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#define IGB_RAH_ASEL (16) /* Bits 16-17 Address Select */
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#define IGB_RAH_POOLSEL (18) /* Bits 18-25 Pool Select */
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/* Bits 26-30: Reserved */
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#define IGB_RAH_AV (1 << 31) /* Bit 31: Address Valid */
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/* Transmit Control */
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/* Bit 0: Reserved */
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#define IGB_TCTL_EN (1 << 1) /* Bit 1: Transmit Enable */
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/* Bit 2: Reserved */
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#define IGB_TCTL_PSP (1 << 3) /* Bit 3: Pad Short Packets */
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#define IGB_TCTL_CT_SHIFT (4) /* Bits 4-11: Collision Threshold */
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#define IGB_TCTL_COLD_SHIFT (12) /* Bits 12-21: Collision Distance (BST) */
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#define IGB_TCTL_SWXOFF (1 << 22) /* Bit 22: Software XOFF Transmission */
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/* Bit 23: Reserved */
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#define IGB_TCTL_RTLC (1 << 24) /* Bit 24: Re-transmit on Late Collision */
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/* Bits 25-32: Reserved */
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/* Transmit Descriptor Control */
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#define IGB_TXDCTL_PTHRESH_SHIFT (0) /* Bits 0-4: Prefetch Threshold */
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/* Bits 5-7: Reserved */
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#define IGB_TXDCTL_HTHRESH_SHIFT (8) /* Bits 8-12: Host Threshold */
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/* Bits 13-15: Reserved */
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#define IGB_TXDCTL_WTHRESH_SHIFT (16) /* Bits 16-20: Write-Back Threshold */
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/* Bits 21-24: Reserved */
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#define IGB_TXDCTL_ENABLE (1 << 25) /* Bit 25: Transmit Queue Enable */
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/* Bits 27-31: Reserved */
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/* Tx Descriptor Ring Length */
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/* Receive Control */
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/* Bit 0: Reserved */
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#define IGB_RCTL_EN (1 << 1) /* Bit 1: Receiver Enable */
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#define IGB_RCTL_SBP (1 << 2) /* Bit 2: Store Bad Packets */
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#define IGB_RCTL_UPE (1 << 3) /* Bit 3: Unicast Promiscuous Enabled */
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#define IGB_RCTL_MPE (1 << 4) /* Bit 4: Multicast Promiscuous Enabled */
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#define IGB_RCTL_LPE (1 << 5) /* Bit 5: Long Packet Reception Enable */
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#define IGB_RCTL_LBM_SHIFT (6) /* Bits 6-7: Loopback mode */
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/* Bits 8-11: Reserved */
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#define IGB_RCTL_MO_SHIFT (12) /* Bits 12-13: Multicast Offset */
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/* Bit 14: Reserved */
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#define IGB_RCTL_BAM (1 << 15) /* Bit 15: Broadcast Accept Mode */
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#define IGB_RCTL_BSIZE_SHIFT (16) /* Bits 16-17: Receive Buffer Size */
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# define IGB_RCTL_BSIZE_2048 (0 << 16) /* 00b: 2048 bytes */
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# define IGB_RCTL_BSIZE_1024 (1 << 16) /* 01b: 1024 bytes */
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# define IGB_RCTL_BSIZE_512 (2 << 16) /* 10b: 512 bytes */
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# define IGB_RCTL_BSIZE_256 (3 << 16) /* 11b: 256 bytes */
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#define IGB_RCTL_VFE (1 << 18) /* Bit 18: VLAN Filter Enable */
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#define IGB_RCTL_CFIEN (1 << 18) /* Bit 19: Canonical Form Indicator Enable */
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#define IGB_RCTL_CFI (1 << 20) /* Bit 20: Canonical Form Indicator bit value */
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#define IGB_RCTL_PSP (1 << 21) /* Bit 21: Pad Small Receive Packets */
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#define IGB_RCTL_DPF (1 << 22) /* Bit 22: Discard Pause Frames */
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#define IGB_RCTL_PMCF (1 << 23) /* Bit 23: Pass MAC Control Frames */
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/* Bits 24-25: Reserved */
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#define IGB_RCTL_SECRC (1 << 26) /* Bit 26: Strip Ethernet CRC from incoming packet */
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/* Bits 27-31: Reserved */
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/* Receive Descriptor Control */
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#define IGB_RXDCTL_PTHRESH_SHIFT (0) /* Bits 0-4: Prefetch Threshold */
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/* Bits 5-7: Reserved */
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#define IGB_RXDCTL_HTHRESH_SHIFT (8) /* Bits 8-12: Host Threshold */
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/* Bits 13-15: Reserved */
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#define IGB_RXDCTL_WTHRESH_SHIFT (16) /* Bits 16-20: Write-Back Threshold */
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/* Bits 21-24: Reserved */
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#define IGB_RXDCTL_ENABLE (1 << 25) /* Bit 25: Receive Queue Enable */
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#define IGB_RXDCTL_SWFLUSH (1 << 26) /* Bit 26: Receive Software Flush */
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/* Bits 27-31: Reserved */
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/* Interrupt Cause */
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#define IGB_IC_TXDW (1 << 0) /* Bit 0: Transmit Descriptor Written Back */
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/* Bit 1: Reserved */
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#define IGB_IC_LSC (1 << 2) /* Bit 2: Link Status Change */
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/* Bit 3: Reserved */
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#define IGB_IC_RXDMT0 (1 << 4) /* Bit 4: Receive Descriptor Minimum Threshold Reached */
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#define IGB_IC_MACSEC (1 << 5) /* Bit 5: Sets the MACSec interrupt */
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#define IGB_IC_RXMISS (1 << 6) /* Bit 6: Receiver Miss Interrupt */
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#define IGB_IC_RXDW (1 << 7) /* Bit 7: Receiver Descriptor Write Back interrupt */
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#define IGB_IC_VMMB (1 << 8) /* Bit 8: Sets the VM mailbox interrupt. */
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/* Bits 9-10: Reserved */
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/* Bits 11-14: General Purpose Interrupts */
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#define IGB_IC_PTRAP (1 << 15) /* Bit 15: Probe trap interrupt */
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/* Bits 16-17: Reserved */
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#define IGB_IC_MNG (1 << 18) /* Bit 18: Management Event interrupt */
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/* Bit 19: Reserved */
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#define IGB_IC_OMED (1 << 20) /* Bit 20: Sets the Other Media Energy Detected Interrupt */
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/* Bit 21: Reserved */
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#define IGB_IC_FER (1 << 22) /* Bit 22: Fatal Error interrupt */
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#define IGB_IC_NFER (1 << 23) /* Bit 23: Sets the Non Fatal Error Interrupt */
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#define IGB_IC_CSRTO (1 << 24) /* Bit 24: Sets the CSR access time out indication interrupt */
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#define IGB_IC_SCE (1 << 25) /* Bit 25: Set the Storm Control Event Interrupt */
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#define IGB_IC_SWD (1 << 26) /* Bit 26: Software Watchdog interrupt */
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/* Bit 27: Reserved */
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#define IGB_IC_DOUTSYNC (1 << 28) /* Bit 28: Sets the DMA Tx Out of Sync Interrupt. */
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/* Bit 29: Reserved */
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#define IGB_IC_TCPTIM (1 << 30) /* Bit 30: Sets the TCP timer interrupt */
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||
/* Bit 31: Reserved */
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/* Extended Interrupt Mask for Non-MSI-X Mode */
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||
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#define IGB_EIMS_NOMSIX_RXTX0 (1 << 0)
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#define IGB_EIMS_NOMSIX_RXTX1 (1 << 1)
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#define IGB_EIMS_NOMSIX_RXTX2 (1 << 2)
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#define IGB_EIMS_NOMSIX_RXTX3 (1 << 3)
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#define IGB_EIMS_NOMSIX_TCPTIM (1 << 30)
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#define IGB_EIMS_NOMSIX_OTHER (1 << 31)
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/* Extended Interrupt Mask for MSI-X Mode */
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||
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#define IGB_EIMS_MSIX_0 (1 << 0)
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#define IGB_EIMS_MSIX_1 (1 << 1)
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#define IGB_EIMS_MSIX_2 (1 << 2)
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#define IGB_EIMS_MSIX_3 (1 << 3)
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#define IGB_EIMS_MSIX_4 (1 << 4)
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||
|
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/* Interrupt Vector Allocation Registers */
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||
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||
#define IGB_IVAR0_RXQ0_SHIFT (0) /* Bits 0-4: MSI-X vector assigned to RxQ0 */
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#define IGB_IVAR0_RXQ0_VAL (1 << 7) /* Bit 7: Valid bit for RxQ0 */
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#define IGB_IVAR0_TXQ0_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to TxQ0 */
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#define IGB_IVAR0_TXQ0_VAL (1 << 7) /* Bit 7: Valid bit for TxQ0 */
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||
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||
/* Interrupt Vector Allocation Registers - Misc */
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||
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||
#define IGB_IVARMSC_TCPTIM (0) /* Bits 0-5: MSI-X vectorassigned to TCP timer interrupt */
|
||
/* Bits 5-6: Reserved */
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||
#define IGB_IVARMSC_TCPTIM_VAL (1 << 7) /* Bit 7: Enable bit for TCP timer interrupt */
|
||
#define IGB_IVARMSC_OTHER_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to Other Cause */
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||
/* Bits 13-14: Reserved */
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||
#define IGB_IVARMSC_OTHER_VAL (1 << 15) /* Bit 15: Enable bit for Other Cause */
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||
/* Bits 20-30: Reserved */
|
||
|
||
/* General Purpose Interrupt Enable */
|
||
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||
#define IGB_GPIE_NSICR (1 << 0) /* Bit 0: Non Selective Interrupt Clear on Read */
|
||
/* Bits 1-3: Reserved */
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||
#define IGB_GPIE_MSIX (1 << 4) /* Bit 4: MSI-X mode */
|
||
/* Bits 5-6: Reserved */
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||
#define IGB_GPIE_LLINTERVAL_SHIFT (7) /* Bits 7-11: Low Latency Credits Increment Rate */
|
||
/* Bits 12-29: Reserved */
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||
#define IGB_GPIE_EIAME (1 << 30) /* Bit 30: Extended Interrupt Auto Mask Enable */
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||
#define IGB_GPIE_PBASUPPORT (1 << 31) /* Bit 31: PBA Support */
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||
|
||
/* Transmit Descriptor Command Field */
|
||
|
||
#define IGB_TDESC_CMD_EOP (1 << 0) /* Bit 0: End Of Packet */
|
||
#define IGB_TDESC_CMD_IFCS (1 << 1) /* Bit 1: Insert FCS */
|
||
#define IGB_TDESC_CMD_IC (1 << 2) /* Bit 2: Insert Checksum */
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#define IGB_TDESC_CMD_RS (1 << 3) /* Bit 3: Report Status */
|
||
#define IGB_TDESC_CMD_DEXT (1 << 5) /* Bit 5: Extension (0b for legacy mode) */
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||
#define IGB_TDESC_CMD_VLE (1 << 6) /* Bit 6: VLAN Packet Enable */
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||
|
||
/* Transmit Descriptor Status Field */
|
||
|
||
#define IGB_TDESC_STATUS_DD (1 << 0) /* Bit 0: Descriptor Done */
|
||
|
||
/* Transmit Descriptor Special Field */
|
||
|
||
#define IGB_TDESC_SPEC_VLAN_SHIFT (0) /* Bits 0-11: VLAN Identifier */
|
||
#define IGB_TDESC_SPEC_CFI (1 << 12) /* Bit 12: Canonical Form Indicator */
|
||
#define IGB_TDESC_SPEC_PRI_SHIFT (13) /* Bits 13-15: User Priority */
|
||
|
||
/* Receive Descriptor Status Field */
|
||
|
||
#define IGB_RDESC_STATUS_DD (1 << 0) /* Bit 0: Descriptor Done */
|
||
#define IGB_RDESC_STATUS_EOP (1 << 1) /* Bit 1: End of Packet */
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||
#define IGB_RDESC_STATUS_VP (1 << 3) /* Bit 3: Packet is 802.1Q (matched VET) */
|
||
#define IGB_RDESC_STATUS_UDPCS (1 << 4) /* Bit 4: UDP checksum or IP payload checksum calculated on packet */
|
||
#define IGB_RDESC_STATUS_L4CS (1 << 5) /* Bit 5: L4 (UDP or TCP) checksum calculated on packet */
|
||
#define IGB_RDESC_STATUS_IPCS (1 << 6) /* Bit 6: IP Checksum Calculated on Packet */
|
||
#define IGB_RDESC_STATUS_PIF (1 << 7) /* Bit 7: Passed in-exact filter */
|
||
|
||
/* Receive Descriptor Errors Field */
|
||
|
||
#define IGB_RDESC_ERRORS_L4E (1 << 5) /* Bit 5: TCP/UDP Checksum Error */
|
||
#define IGB_RDESC_ERRORS_IPE (1 << 6) /* Bit 6: IP Checksum Error */
|
||
#define IGB_RDESC_ERRORS_RXE (1 << 7) /* Bit 7: RX Data Error */
|
||
|
||
/* Receive Descriptor Special Field */
|
||
|
||
#define IGB_RDESC_SPEC_VLAN_SHIFT (0) /* Bits 0-11: VLAN Identifier */
|
||
#define IGB_RDESC_SPEC_CFI (1 << 12) /* Bit 12: Canonical Form Indicator */
|
||
#define IGB_RDESC_SPEC_PRI_SHIFT (13) /* Bits 13-15: User Priority */
|
||
|
||
/*****************************************************************************
|
||
* Public Types
|
||
*****************************************************************************/
|
||
|
||
/* Legacy TX descriptor */
|
||
|
||
begin_packed_struct struct igb_tx_leg_s
|
||
{
|
||
uint64_t addr;
|
||
uint16_t len;
|
||
uint8_t cso;
|
||
uint8_t cmd;
|
||
uint8_t status;
|
||
uint8_t css;
|
||
uint16_t special;
|
||
} end_packed_struct;
|
||
|
||
/* Legacy RX descriptor */
|
||
|
||
begin_packed_struct struct igb_rx_leg_s
|
||
{
|
||
uint64_t addr;
|
||
uint16_t len;
|
||
uint16_t checksum;
|
||
uint8_t status;
|
||
uint8_t errors;
|
||
uint16_t special;
|
||
} end_packed_struct;
|
||
|
||
#endif /* __DRIVERS_NET_IGB!_H */
|