Luchian Mihai
c2f9368c7e
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7.9 KiB
Text
345 lines
No EOL
7.9 KiB
Text
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config ARCH_ARM7TDMI
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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---help---
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The Arm7TDMI-S is an excellent workhorse processor capable of a wide
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array of applications. Traditionally used in mobile handsets, the
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processor is now broadly in many non-mobile applications.
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config ARCH_ARM920T
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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The ARM9 processor family is built around the ARM9TDMI processor and
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incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family
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includes the ARM920T and ARM922T cached processor macrocells:
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- Dual 16k caches for applications running Symbian OS, Palm OS,
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Linux and Windows CE,
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- Dual 8k caches for applications running Symbian OS, Palm OS, Linux
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and Windows CE Applications
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config ARCH_ARM926EJS
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm926EJ-S is the entry point processor capable of supporting full
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Operating Systems including Linux, WindowsCE, and Symbian.
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The ARM9E processor family enables single processor solutions for
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microcontroller, DSP and Java applications. The ARM9E family of
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products are DSP-enhanced 32-bit RISC processors, for applications
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requiring a mix of DSP and microcontroller performance. The family
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includes the ARM926EJ-S, ARM946E-S, ARM966E-S, and ARM968E-S
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processor macrocells. They include signal processing extensions to
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enhance 16-bit fixed point performance using a single-cycle 32 x 16
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multiply-accumulate (MAC) unit, and implement the 16-bit Thumb
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instruction set. The ARM926EJ-S processor also includes ARM Jazelle
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technology which enables the direct execution of Java bytecodes in
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hardware.
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config ARCH_ARM1136J
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1136J(F)-S is very similar to Arm926EJ-S, but includes an
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extended pipeline, basic SIMD (Single Instruction Multiple Data)
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instructions, and improved frequency and performance.
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config ARCH_ARM1156T2
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1156T2(F)-S is the highest-performance processor in the real-time
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Classic Arm family.
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config ARCH_ARM1176JZ
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1176JZ(F)-S is the highest-performance single-core processor in
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the Classic Arm family. It also introduced TrustZone technology to
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enable secure execution outside of the reach of malicious code.
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config ARCH_ARMV6M
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bool
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default n
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select ARCH_HAVE_CPUINFO
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config ARCH_CORTEXM0
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV6M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_RESET
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select ARCH_HAVE_HARDFAULT_DEBUG
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config ARCH_ARMV7M
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_DEBUG
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select ARCH_HAVE_PERF_EVENTS
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config ARCH_CORTEXM3
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV7M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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config ARCH_CORTEXM4
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV7M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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config ARCH_CORTEXM7
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV7M
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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config ARCH_ARMV7A
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_DEBUG
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select ARCH_HAVE_PERF_EVENTS
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select ARM_HAVE_WFE_SEV
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config ARCH_CORTEXA5
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bool
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default n
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select ARCH_ARMV7A
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_MPCORE
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config ARCH_CORTEXA7
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bool
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default n
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select ARCH_ARMV7A
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_FPU
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select ARM_HAVE_MPCORE
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config ARCH_CORTEXA8
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bool
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default n
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select ARCH_ARMV7A
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEXA9
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bool
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default n
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select ARCH_ARMV7A
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_TESTSET
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select ARM_HAVE_MPCORE
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config ARCH_ARMV7R
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_PERF_EVENTS
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config ARCH_CORTEXR4
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bool
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default n
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select ARCH_ARMV7R
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEXR5
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bool
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default n
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select ARCH_ARMV7R
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEXR7
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bool
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default n
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select ARCH_ARMV7R
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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config ARCH_CORTEXR52
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bool
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default n
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select ARCH_ARMV8R
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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config ARCH_ARMV8M
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_DEBUG
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select ARCH_HAVE_PERF_EVENTS
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config ARCH_CORTEXM23
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV8M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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config ARCH_CORTEXM33
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV8M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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select ARCH_HAVE_SECUREFAULT_DEBUG if ARCH_TRUSTZONE_SECURE
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config ARCH_CORTEXM35P
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV8M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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select ARCH_HAVE_SECUREFAULT_DEBUG if ARCH_TRUSTZONE_SECURE
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config ARCH_CORTEXM55
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV8M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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select ARCH_HAVE_SECUREFAULT_DEBUG if ARCH_TRUSTZONE_SECURE
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config ARCH_CORTEXM85
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bool
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default n
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select ARM_THUMB
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select ARCH_ARMV8M
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_HARDFAULT_DEBUG
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select ARCH_HAVE_MEMFAULT_DEBUG
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select ARCH_HAVE_BUSFAULT_DEBUG
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select ARCH_HAVE_USAGEFAULT_DEBUG
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select ARCH_HAVE_SECUREFAULT_DEBUG if ARCH_TRUSTZONE_SECURE
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config ARCH_ARMV8R
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_PERF_EVENTS
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select ONESHOT
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select ALARM_ARCH |