Luchian Mihai
c2f9368c7e
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222 lines
4.9 KiB
Text
222 lines
4.9 KiB
Text
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "ARMv7-A Configuration Options"
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config ARMV7A_HAVE_GICv2
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bool
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_HIPRI_INTERRUPT
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default n
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---help---
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Selected by the configuration tool if the architecture supports the
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Generic Interrupt Controller (GIC)
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if ARMV7A_HAVE_GICv2
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config ARMV7A_GICv2_DUMP
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bool "Dump the gic register"
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default DEBUG_IRQ_INFO
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config ARMV7A_GIC_EOIMODE
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bool "Enable GIC EOImode"
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default n
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---help---
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Enable GICC_CTLR.EOImode, this will separates the priority drop and interrupt
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deactivation operations.
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config ARMV7A_GICV2_LEGACY_IRQ0
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int "pci legacy irq0 default val"
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default 35
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---help---
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The qemu pci legacy irq0 default is 35. -1 means disable
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config ARMV7A_GICv2M
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bool "gic support msi irq"
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depends on PCI_MSIX
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default n
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endif # ARMV7A_HAVE_GICv2
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config ARMV7A_HAVE_GTM
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports the
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Global Timer (GTM)
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config ARMV7A_HAVE_PTM
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports the
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per-processor Private Timers (PTMs)
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config ARMV7A_HAVE_L2CC
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports any
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kind of L2 cache.
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config ARMV7A_SMP_BUSY_WAIT
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bool "Busy wait when SMP boot"
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default n
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depends on SMP
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---help---
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Enables busy wait when SMP boot
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config ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
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hex "Busy wait flag address"
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depends on ARMV7A_SMP_BUSY_WAIT
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config ARMV7A_HAVE_L2CC_PL310
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bool
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default n
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select ARMV7A_HAVE_L2CC
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---help---
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Set by architecture-specific code if the hardware supports a PL310
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r3p2 L2 cache (only version r3p2 is supported).
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if ARMV7A_HAVE_L2CC
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menu "L2 Cache Configuration"
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config ARMV7A_L2CC_PL310
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bool "ARMv7-A L2CC P310 Support"
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default n
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depends on ARMV7A_HAVE_L2CC_PL310
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select ARCH_L2CACHE
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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secondary cache, also referred to as a Level 2 or L2 cache, is a
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method of improving the system performance when significant memory
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traffic is generated by the processor.
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if ARCH_L2CACHE
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if ARMV7A_L2CC_PL310
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config PL310_LOCKDOWN_BY_MASTER
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bool "PL310 Lockdown by Master"
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default n
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config PL310_LOCKDOWN_BY_LINE
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bool "PL310 Lockdown by Line"
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default n
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config PL310_ADDRESS_FILTERING
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bool "PL310 Address Filtering by Line"
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default n
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config PL310_TRCR
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bool "PL310 TRCR set by usr"
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default n
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if PL310_TRCR
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config PL310_TRCR_TSETLAT
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int "PL310 TRCR setup latency"
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default 1
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config PL310_TRCR_TRDLAT
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int "PL310 TRCR read access latency"
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default 1
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config PL310_TRCR_TWRLAT
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int "PL310 TRCR write access latency"
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default 1
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endif # PL310_TRCR
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config PL310_DRCR
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bool "PL310 DRCR set by usr"
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default n
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if PL310_DRCR
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config PL310_DRCR_DSETLAT
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int "PL310 DRCR setup latency"
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default 1
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config PL310_DRCR_DRDLAT
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int "PL310 DRCR read access latency"
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default 1
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config PL310_DRCR_DWRLAT
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int "PL310 DRCR write access latency"
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default 1
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endif # PL310_DRCR
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endif # ARMV7A_L2CC_PL310
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choice
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prompt "L2 Cache Associativity"
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default ARMV7A_ASSOCIATIVITY_8WAY
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depends on ARCH_L2CACHE
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---help---
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This choice specifies the associativity of L2 cache in terms of the
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number of ways. This value could be obtained by querying cache
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configuration registers. However, by defining a configuration
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setting instead, we can avoid using RAM memory to hold information
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about properties of the memory.
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config ARMV7A_ASSOCIATIVITY_8WAY
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bool "8-Way Associativity"
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config ARMV7A_ASSOCIATIVITY_16WAY
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bool "16-Way Associativity"
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endchoice # L2 Cache Associativity
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choice
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prompt "L2 Cache Way Size"
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default ARMV7A_WAYSIZE_16KB
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depends on ARCH_L2CACHE
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---help---
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This choice specifies size of each way. This value can be obtained
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by querying cache configuration registers. However, by defining a
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configuration setting instead, we can avoid using RAM memory to hold
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information
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config ARMV7A_WAYSIZE_16KB
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bool "16 KiB"
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config ARMV7A_WAYSIZE_32KB
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bool "32 KiB"
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config ARMV7A_WAYSIZE_64KB
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bool "64 KiB"
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config ARMV7A_WAYSIZE_128KB
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bool "128 KiB"
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config ARMV7A_WAYSIZE_256KB
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bool "256 KiB"
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config ARMV7A_WAYSIZE_512KB
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bool "512 KiB"
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endchoice # L2 Cache Associativity
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endif # ARCH_L2CACHE
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endmenu # L2 Cache Configuration
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endif # ARMV7A_HAVE_L2CC
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config ARMV7A_ALIGNMENT_TRAP
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bool "Enable Alignment Check at __start"
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default n
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config ARMV7A_CACHE_ROUND_ROBIN
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bool "Enable Cache Round Robin Replacement Policy at __start"
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default n
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config ARMV7A_DCACHE_DISABLE
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bool "Disable DCACHE at __start"
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default n
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config ARMV7A_ICACHE_DISABLE
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bool "Disable ICACHE at __start"
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default n
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config ARMV7A_AFE_ENABLE
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bool "Enable Access Flag at __start"
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default n
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