48a5419005
Add caps member to coresight_desc_s for etr and fix etr compilation error Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
137 lines
5 KiB
C
137 lines
5 KiB
C
/****************************************************************************
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* include/nuttx/coresight/coresight_tmc.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_CORESIGHT_CORESIGHT_TMC_H
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#define __INCLUDE_NUTTX_CORESIGHT_CORESIGHT_TMC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/mutex.h>
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#include <nuttx/coresight/coresight.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* TMC ETR Capability bit definitions. These need to be set by software. */
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#define TMC_ETR_SG (0x1U << 0)
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/* ETR has separate read/write cache encodings. */
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#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
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/* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
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* retained when TMC leaves Disabled state, allowing us to continue
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* the tracing from a point where we stopped. This also implies that
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* the RRP/RWP/STS.Full should always be programmed to the correct
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* value. Unfortunately this is not advertised by the hardware,
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* so we have to rely on PID of the IP to detect the functionality.
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*/
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#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
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/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
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#define TMC_600_ETR_CAPS \
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(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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enum tmc_config_type_e
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{
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TMC_CONFIG_TYPE_ETB,
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TMC_CONFIG_TYPE_ETR,
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TMC_CONFIG_TYPE_ETF,
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};
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enum tmc_mem_intf_width_e
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{
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TMC_MEM_INTF_WIDTH_32BITS = 1,
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TMC_MEM_INTF_WIDTH_64BITS = 2,
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TMC_MEM_INTF_WIDTH_128BITS = 4,
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TMC_MEM_INTF_WIDTH_256BITS = 8,
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};
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enum tmc_etr_mode_e
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{
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TMC_ETR_MODE_FLAT, /* Uses contiguous flat buffer. */
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TMC_ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism. */
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TMC_ETR_MODE_CATU, /* Use SG mechanism in CATU. */
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};
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struct coresight_tmc_dev_s
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{
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struct coresight_dev_s csdev;
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enum tmc_config_type_e config_type; /* Device type: ETB/ETR/ETF. */
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enum tmc_mem_intf_width_e mmwidth; /* Width of the memory interface databus, in bytes. */
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uint32_t trigger_cntr; /* Amount of words to store after a trigger. */
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uint32_t size; /* RAM buffer size. */
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uint32_t burst_size; /* Max burst size used in ETR devices. */
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FAR uint32_t *buf; /* Pointer to the RAM buf. */
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uint32_t len; /* Valid data len in RAM buffer. */
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mutex_t lock; /* Mutex for driver's open/close. */
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uint32_t caps; /* Capalilities current etr device has. */
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enum tmc_etr_mode_e mode; /* ETR buffer mode. */
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uint32_t offset; /* Data offset in ETR buffer. */
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uint8_t opencnt; /* TMC device's open count. */
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};
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: tmc_register
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*
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* Description:
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* Register a TMC devices.
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*
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* Input Parameters:
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* desc - A description of this coresight device.
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*
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* Returned Value:
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* Pointer to a TMC device on success; NULL on failure.
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*
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****************************************************************************/
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FAR struct coresight_tmc_dev_s *
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tmc_register(FAR const struct coresight_desc_s *desc);
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/****************************************************************************
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* Name: tmc_unregister
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*
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* Description:
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* Unregister a TMC devices.
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*
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* Input Parameters:
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* tmcdev - Pointer to the TMC device.
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*
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****************************************************************************/
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void tmc_unregister(FAR struct coresight_tmc_dev_s *tmcdev);
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#endif //__INCLUDE_NUTTX_CORESIGHT_CORESIGHT_TMC_H
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