fb14b54b83
If atomic_try_cmpxchg_xxxx runs on LL/SC architectures (e.g.ARMv7, ARMv8, RISC-V), the weak CAS expands to a single LDREX/STREX pair. If the CPU takes an IRQ/FIQ/SVC between the two instructions, hardware performs an implicit CLREX and the following STREX returns 1, therefore atomic_try_cmpxchg_xxxx return failure even though *addr* still holds the expected value. So let's retry atomic_try_cmpxchg_xxxx in this case. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> |
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| libbuiltin | ||
| libc | ||
| libdsp | ||
| libm | ||
| libnx | ||
| libxx | ||
| CMakeLists.txt | ||