Xiang Xiao fc16cfaefe Correct the code alignment found in review ... Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>		2022-04-26 11:34:28 +03:00
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include	RISC-V: Combine 3 variables that depend on CPU amount into one	2022-04-12 01:59:35 +08:00
src	Correct the code alignment found in review	2022-04-26 11:34:28 +03:00
Kconfig	arch: risc-v: Do not enable FPU for K210 with QEMU	2022-04-22 14:52:04 +08:00