STM32F0: Add support for HSI48
This commit is contained in:
Gregory Nutt
parent
a98cdc7a45
commit
20ddbd7368
7 changed files with 360 additions and 20 deletions
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@ -466,6 +466,7 @@ config STM32F0_STM32F07X
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config STM32F0_STM32F09X
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bool
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default n
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select STM32F0_HAVE_HSI48
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config STM32F0_VALUELINE
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bool
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@ -528,6 +529,7 @@ config STM32F0_LOWVOLTLINE
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config STM32F0_USBLINE
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bool
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default n
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select STM32F0_HAVE_HSI48
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select STM32F0_HAVE_USART3
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select STM32F0_HAVE_USART4
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select STM32F0_HAVE_TIM1
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@ -576,6 +578,10 @@ config STM32F0_HAVE_CCM
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bool
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default n
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config STM32F0_HAVE_HSI48
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bool
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default n
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config STM32F0_HAVE_USBDEV
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bool
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default n
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@ -588,10 +594,6 @@ config STM32F0_HAVE_HRTIM1
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bool
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default n
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config STM32F0_HAVE_LTDC
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bool
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default n
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config STM32F0_HAVE_USART3
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bool
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default n
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@ -87,6 +87,10 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y)
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CHIP_CSRCS += stm32f0_irqprio.c
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endif
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ifeq ($(CONFIG_STM32F0_HAVE_HSI48),y)
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CHIP_CSRCS += stm32f0_hsi48.c
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endif
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ifeq ($(CONFIG_STM32F0_SPI0),y)
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CHIP_CSRCS += stm32f0_spi.c
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else
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@ -55,6 +55,8 @@
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#define STM32F0_RCC_CSR_OFFSET 0x0024 /* Control/status register */
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#define STM32F0_RCC_AHBRSTR_OFFSET 0x0028 /* AHB Reset register */
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#define STM32F0_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */
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#define STM32F0_RCC_CFGR3_OFFSET 0x0030 /* Clock configuration register 3 */
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#define STM32F0_RCC_CR2_OFFSET 0x0034 /* Clock control register 2 */
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/* Register Addresses ***************************************************************/
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@ -70,6 +72,8 @@
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#define STM32F0_RCC_CSR (STM32F0_RCC_BASE+STM32F0_RCC_CSR_OFFSET)
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#define STM32F0_RCC_AHBRSTR (STM32F0_RCC_BASE+STM32F0_RCC_AHBRSTR_OFFSET)
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#define STM32F0_RCC_CFGR2 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR2_OFFSET)
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#define STM32F0_RCC_CFGR3 (STM32F0_RCC_BASE+STM32F0_RCC_CFGR3_OFFSET)
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#define STM32F0_RCC_CR2 (STM32F0_RCC_BASE+STM32F0_RCC_CR2_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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@ -149,16 +153,18 @@
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/* Bit 22-23: Reserved */
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#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
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#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)
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# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */
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# define RCC_CFGR_HSI14 (1 << RCC_CFGR_MCO_SHIFT) /* 0001: Internal RC 14MHz oscillator */
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# define RCC_CFGR_LSI (2 << RCC_CFGR_MCO_SHIFT) /* 0010: Internal Low Speed (LSI) oscillator */
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# define RCC_CFGR_LSE (2 << RCC_CFGR_MCO_SHIFT) /* 0011: External Low Speed (LSE) oscillator */
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# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 0100: System clock selected */
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# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 0101: Internal 8 MHz RC oscillator clock selected */
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# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 0110: External 4-32 MHz oscillator clock selected */
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# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 0111: PLL clock selected (divided by 1 or 2 depending on PLLNODIV */
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# define RCC_CFGR_PLL2CLK (8 << RCC_CFGR_MCO_SHIFT) /* 1000: Internal RC 48MHz (HSI48) oscillator */
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#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller Clock Output Prescaler, not available on STM32F05x */
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# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0000: No clock */
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# define RCC_CFGR_HSI14 (1 << RCC_CFGR_MCO_SHIFT) /* 0001: Internal RC 14MHz oscillator */
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# define RCC_CFGR_LSI (2 << RCC_CFGR_MCO_SHIFT) /* 0010: Internal Low Speed (LSI) oscillator */
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# define RCC_CFGR_LSE (2 << RCC_CFGR_MCO_SHIFT) /* 0011: External Low Speed (LSE) oscillator */
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# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 0100: System clock selected */
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# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 0101: Internal 8 MHz RC oscillator clock selected */
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# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 0110: External 4-32 MHz oscillator clock selected */
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# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 0111: PLL clock selected (divided by 1 or 2
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* depending on PLLNODIV) */
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# define RCC_CFGR_PLL2CLK (8 << RCC_CFGR_MCO_SHIFT) /* 1000: Internal RC 48MHz (HSI48) oscillator */
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#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller Clock Output Prescaler,
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* not available on STM32F05x */
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#define RCC_CFGR_MCOPRE_MASK (3 << RCC_CFGR_MCOPRE_SHIFT)
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# define RCC_CFGR_MCOPRE_div1 (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: MCO is divided by 1 */
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# define RCC_CFGR_MCOPRE_div2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: MCO is divided by 2 */
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@ -345,4 +351,42 @@
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# define RCC_CFGR2_PREDIV1d15 (14 << RCC_CFGR2_PREDIV1_SHIFT)
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# define RCC_CFGR2_PREDIV1d16 (15 << RCC_CFGR2_PREDIV1_SHIFT)
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/* Clock configuration register 3 */
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#define RCC_CFGR3_USART1SW_SHIFT (0) /* Bits 0-1: USART1 clock source selection */
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#define RCC_CFGR3_USART1SW_MASK (3 << RCC_CFGR3_USART1SW_SHIFT)
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# define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK is USART1 clock source */
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# define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* SYSCLK is USART1 clock */
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# define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE is USART1 clock */
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# define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI is USART1 clock */
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#define RCC_CFGR3_CECSW (1 << 6) /* Bit 6: HDMI CEC clock source selection */
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#define RCC_CFGR3_USBSW (1 << 7) /* Bit 7: USB clock source selection */
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#define RCC_CFGR3_ADCSW (1 << 8) /* Bit 8: ADC clock source selection */
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#define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */
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#define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT)
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# define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK is USART2 clock source */
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# define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* SYSCLK is USART2 clock */
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# define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE is USART2 clock */
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# define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) /* HSI is USART2 clock */
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#define RCC_CFGR3_USART3SW_SHIFT (18) /* Bits 18-19: USART3 clock source selection */
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#define RCC_CFGR3_USART3SW_MASK (3 << RCC_CFGR3_USART3SW_SHIFT)
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# define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK is USART3 clock source */
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# define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* SYSCLK is USART3 clock */
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# define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE is USART3 clock */
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# define RCC_CFGR3_USART3SW_HSI (3 << RCC_CFGR3_USART3SW_SHIFT) /* HSI is USART3 clock */
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/* Clock control register 2 */
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#define RCC_CR2_HSI14ON (1 << 0) /* Bit 0: HSI14 clock enable */
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#define RCC_CR2_HSI14RDY (1 << 1) /* Bit 1: HSI14 clock ready flag */
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#define RCC_CR2_HSI14DIS (1 << 2) /* Bit 2: HSI14 clock request from ADC disable */
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#define RCC_CR2_HSI14TRIM_SHIFT (3) /* Bits 3-7: HSI14 clock trimming */
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#define RCC_CR2_HSI14TRIM_MASK (31 << RCC_CR2_HSI14TRIM_SHIFT)
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#define RCC_CR2_HSI14CAL_SHIFT (8) /* Bits 8-15: HSI14 clock calibration */
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#define RCC_CR2_HSI14CAL_MASK (0xff << RCC_CR2_HSI14CAL_SHIFT)
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#define RCC_CR2_HSI48ON (1 << 16) /* Bit 16: HSI48 clock enable */
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#define RCC_CR2_HSI48RDY (1 << 17) /* Bit 17: HSI48 clock ready flag */
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#define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */
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#define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT)
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#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_RCC_H */
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@ -108,10 +108,8 @@
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#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET)
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#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET)
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#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET)
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET)
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#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET)
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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183
arch/arm/src/stm32f0/stm32f0_hsi48.c
Normal file
183
arch/arm/src/stm32f0/stm32f0_hsi48.c
Normal file
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@ -0,0 +1,183 @@
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/****************************************************************************
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* arch/arm/src/stm32f0/stm32f0_hsi48.c
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "chip/stm32f0_rcc.h"
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#include "chip/stm32f0_crs.h"
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#include "stm32f0_hsi48.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32f0_enable_hsi48
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*
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* Description:
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* On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock
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* signal is generated from an internal 48 MHz RC oscillator and can be
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* used directly as a system clock or divided and be used as PLL input.
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*
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* The internal 48MHz RC oscillator is mainly dedicated to provide a high
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* precision clock to the USB peripheral by means of a special Clock
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* Recovery System (CRS) circuitry, which could use the USB SOF signal or
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* the LSE or an external signal to automatically adjust the oscillator
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* frequency on-fly, in a very small steps. This oscillator can also be
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* used as a system clock source when the system is in run mode; it will
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* be disabled as soon as the system enters in Stop or Standby mode. When
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* the CRS is not used, the HSI48 RC oscillator runs on its default
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* frequency which is subject to manufacturing process variations.
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*
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* Input Parameters:
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* Identifies the syncrhonization source for the HSI48. When used as the
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* USB source clock, this must be set to SYNCSRC_USB.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
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{
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uint32_t regval;
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/* Enable the HSI48 clock.
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*
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* The HSI48 RC can be switched on and off using the HSI48ON bit in the
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* Clock control register (RCC_CR).
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*
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* The USB clock may be derived from either the PLL clock or from the
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* HSI48 clock. This oscillator will be also automatically enabled (by
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* hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock
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* source for the USB and the peripheral is
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* enabled.
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*/
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regval = getreg32(STM32F0_RCC_CR2);
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regval |= RCC_CR2_HSI48ON;
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putreg32(regval, STM32F0_RCC_CR2);
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if (syncsrc == SYNCSRC_USB)
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{
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/* Select the HSI48 as the USB clock source */
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regval = getreg32(STM32F0_RCC_CFGR3);
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regval &= ~RCC_CFGR3_USBSW;
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putreg32(regval, STM32F0_RCC_CFGR3);
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}
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/* Wait for the HSI48 clock to stabilize */
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while ((getreg32(STM32F0_RCC_CR2) & RCC_CR2_HSI48RDY) == 0);
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/* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
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* register, can be the signal from the external CRS_SYNC pin, the LSE
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* clock or the USB SOF signal.
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*/
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regval = getreg32(STM32F0_CRS_CFGR);
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regval &= ~CRS_CFGR_SYNCSRC_MASK;
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switch (syncsrc)
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{
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default:
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case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */
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regval |= CRS_CFGR_SYNCSRC_GPIO;
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break;
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case SYNCSRC_LSE: /* LSE selected as SYNC signal source */
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regval |= CRS_CFGR_SYNCSRC_LSE;
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break;
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case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */
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regval |= CRS_CFGR_SYNCSRC_USBSOF;
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break;
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}
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putreg32(regval, STM32F0_CRS_CFGR);
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/* Set the AUTOTRIMEN bit the the CRS_CR register to enables the automatic
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* hardware adjustment of TRIM bits according to the measured frequency
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* error between the selected SYNC event.
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*/
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regval = getreg32(STM32F0_CRS_CR);
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regval |= CRS_CR_AUTOTRIMEN;
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putreg32(regval, STM32F0_CRS_CR);
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}
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/****************************************************************************
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* Name: stm32f0_disable_hsi48
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*
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* Description:
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* Disable the HSI48 clock.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void stm32f0_disable_hsi48(void)
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{
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uint32_t regval;
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/* Disable the HSI48 clock */
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regval = getreg32(STM32F0_RCC_CR2);
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regval &= ~RCC_CR2_HSI48ON;
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putreg32(regval, STM32F0_RCC_CR2);
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/* Set other registers to the default settings. */
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regval = getreg32(STM32F0_CRS_CFGR);
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regval &= ~CRS_CFGR_SYNCSRC_MASK;
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putreg32(regval, STM32F0_CRS_CFGR);
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regval = getreg32(STM32F0_CRS_CR);
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regval &= ~CRS_CR_AUTOTRIMEN;
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putreg32(regval, STM32F0_CRS_CR);
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}
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109
arch/arm/src/stm32f0/stm32f0_hsi48.h
Normal file
109
arch/arm/src/stm32f0/stm32f0_hsi48.h
Normal file
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@ -0,0 +1,109 @@
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/************************************************************************************
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* arch/arm/src/stm32f0/stm32f0_rcc.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.orgr>
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* Alan Carvalho de Assis <acassis@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H
|
||||
#define __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_STM32F0_HAVE_HSI48
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
enum syncsrc_e
|
||||
{
|
||||
SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */
|
||||
SYNCSRC_LSE, /* LSE selected as SYNC signal source */
|
||||
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32f0_enable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* On STM32F04x, STM32F07x and STM32F09x devices only, the HSI48 clock
|
||||
* signal is generated from an internal 48 MHz RC oscillator and can be
|
||||
* used directly as a system clock or divided and be used as PLL input.
|
||||
*
|
||||
* The internal 48MHz RC oscillator is mainly dedicated to provide a high
|
||||
* precision clock to the USB peripheral by means of a special Clock
|
||||
* Recovery System (CRS) circuitry, which could use the USB SOF signal or
|
||||
* the LSE or an external signal to automatically adjust the oscillator
|
||||
* frequency on-fly, in a very small steps. This oscillator can also be
|
||||
* used as a system clock source when the system is in run mode; it will
|
||||
* be disabled as soon as the system enters in Stop or Standby mode. When
|
||||
* the CRS is not used, the HSI48 RC oscillator runs on its default
|
||||
* frequency which is subject to manufacturing process variations.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Identifies the syncrhonization source for the HSI48. When used as the
|
||||
* USB source clock, this must be set to SYNCSRC_USB.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32f0_enable_hsi48(enum syncsrc_e syncsrc);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32f0_disable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* Disable the HSI48 clock.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32f0_disable_hsi48(void);
|
||||
|
||||
#endif /* CONFIG_STM32F0_HAVE_HSI48 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0_STM32F0_HSI48_H */
|
||||
|
|
@ -34,8 +34,8 @@
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RRC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0_STM32F0_RRC_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32F0_STM32F0_RCC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue