arch/arm/max326xx: add max32690 icc updates
Add updates for MAX32690 Instruction Cache Controller to enhance device support in NuttX architecture.
This commit is contained in:
Ramin Seyed-Moussavi
Alan C. Assis
parent
e99c516a91
commit
381d3fe64f
4 changed files with 151 additions and 7 deletions
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@ -29,7 +29,12 @@ include armv7-m/Make.defs
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CHIP_CSRCS = max326_start.c max326_irq.c max326_clrpend.c
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ifeq ($(CONFIG_MAX326XX_ICC),y)
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CHIP_CSRCS += max326_icc.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_icc.c
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endif
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32690),y)
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CHIP_CSRCS += max32690_icc.c
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endif
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endif
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ifeq ($(CONFIG_RTC_DRIVER),y)
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@ -43,10 +43,20 @@
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/* Register Addresses *******************************************************/
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#define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET)
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#define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET)
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#define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
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#define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET)
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/* The MAX32690 has two ICC controllers because it includes a
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* second integrated RISC-V core.
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*/
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#if defined(CONFIG_ARCH_FAMILY_MAX32690)
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#define MAX326_ICC0_ID (MAX326_ICC0_BASE + MAX326_ICC_ID_OFFSET)
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#define MAX326_ICC0_MEMCFG (MAX326_ICC0_BASE + MAX326_ICC_MEMCFG_OFFSET)
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#define MAX326_ICC0_CTRLSTAT (MAX326_ICC0_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
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#define MAX326_ICC0_INVDTALL (MAX326_ICC0_BASE + MAX326_ICC_INVDTALL_OFFSET)
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#else
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#define MAX326_ICC_ID (MAX326_ICC_BASE + MAX326_ICC_ID_OFFSET)
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#define MAX326_ICC_MEMCFG (MAX326_ICC_BASE + MAX326_ICC_MEMCFG_OFFSET)
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#define MAX326_ICC_CTRLSTAT (MAX326_ICC_BASE + MAX326_ICC_CTRLSTAT_OFFSET)
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#define MAX326_ICC_INVDTALL (MAX326_ICC_BASE + MAX326_ICC_INVDTALL_OFFSET)
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#endif
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/* Register Bit-field Definitions *******************************************/
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/max326xx/common/max326_icc.c
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* arch/arm/src/max326xx/max32660/max32660_icc.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -57,11 +57,13 @@ void max326_icc_enable(bool enable)
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max326_icc_enableclk();
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putreg32(1, MAX326_ICC_INVDTALL);
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/* Enable the cache and wait for it to become ready */
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putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT);
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do
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{
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putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC_CTRLSTAT);
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regval = getreg32(MAX326_ICC_CTRLSTAT);
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}
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while ((regval & ICC_CTRLSTAT_READY) == 0);
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127
arch/arm/src/max326xx/max32690/max32690_icc.c
Normal file
127
arch/arm/src/max326xx/max32690/max32690_icc.c
Normal file
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@ -0,0 +1,127 @@
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/****************************************************************************
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* arch/arm/src/max326xx/max32690/max32690_icc.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "arm_internal.h"
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#include "hardware/max326_icc.h"
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#include "max326_periphclks.h"
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#include "max326_icc.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: max326_icc_enable
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*
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* Description:
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* Enables or disables the instruction cache.
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* The MAX32690 actually has two cache controllers.
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* Support for the RISC-V core will be added later.
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*
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****************************************************************************/
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void max326_icc_enable(bool enable)
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{
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uint32_t regval;
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if (enable)
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{
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/* Enable ICC peripheral clocking */
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max326_syscache_enableclk();
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putreg32(1, MAX326_ICC0_INVDTALL);
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/* Enable the cache and wait for it to become ready */
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putreg32(ICC_CTRLSTAT_ENABLE, MAX326_ICC0_CTRLSTAT);
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do
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{
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regval = getreg32(MAX326_ICC0_CTRLSTAT);
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}
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while ((regval & ICC_CTRLSTAT_READY) == 0);
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}
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else
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{
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/* Disable the cache */
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putreg32(0, MAX326_ICC0_CTRLSTAT);
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/* Disable clocking to the ICC peripheral */
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max326_syscache_disableclk();
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}
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}
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/****************************************************************************
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* Name: max326_icc_invalidate
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*
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* Description:
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* Invalidate the instruction cache
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*
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****************************************************************************/
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void max326_icc_invalidate(void)
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{
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/* Any write to the INVDTALL register will invalidate the entire cache. */
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putreg32(1, MAX326_ICC0_INVDTALL);
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/* Wait for the cache to become ready again */
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while ((getreg32(MAX326_ICC0_CTRLSTAT) & ICC_CTRLSTAT_READY) == 0)
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{
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}
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}
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/****************************************************************************
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* Name: up_addrenv_coherent
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*
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* Description:
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* Flush D-Cache and invalidate I-Cache in preparation for a change in
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* address environments. This should immediately precede a call to
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* up_addrenv_select();
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*
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* Input Parameters:
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* addrenv - Describes the address environment to be made coherent.
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno value on failure.
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_ADDRENV
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int up_addrenv_coherent(const arch_addrenv_t *addrenv)
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{
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max326_icc_invalidate();
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}
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#endif
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