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style: fix spelling in code comments and strings

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Lars Kruse 2025-05-03 06:16:30 +02:00 • committed by Xiang Xiao
parent b2315e98c4
commit 3ce85ca54e
1670 changed files with 3162 additions and 2991 deletions
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154
.codespell-ignore-lines
View file

@ -15,4 +15,158 @@ Linix 45ZWN24-40 2 0.5 Ohm 0.400 mH 2.34A 24V
* [#14540](https://github.com/apache/nuttx/pull/14540) CMake/preprocess: fix typo PREPROCES -> PREPROCESS
* [#14927](https://github.com/apache/nuttx/pull/14927) spelling: fix spelling typo premption -> preemption
* [#15520](https://github.com/apache/nuttx/pull/15520) drivers/note: fix typo falgs and align local name to irq_mask
* [#4526](https://github.com/apache/nuttx/pull/4526) Rearch video
* [#6447](https://github.com/apache/nuttx/pull/6447) bcm43xxx: Remove bcmf_txavail_work and resue bcmf_tx_poll_work
ans init
* CAF : Depends on CONFIG_NET_PROMISCUOUS
* been lost). If ORE is set along with RXNE then it tells you
/* GIR bits must be masked! */
#define MU_GIER_GIE(n) (1 << (n)) /* Bit n: MUA/MUB General Purpose Interrupt Enable n (GIEn) */
tloadr r1, DEBUG_GPIO @0x80058a PB oen
.word (0x80058a) @ PBx oen
* FLASH_STATUS_WEL: The Write Enable Latch (WEL) bit indicates the
* 1. Enable the SPI and I2C for GroupA and GroupD;
/* HALP - Hall Current and Expected patterns */
#define USIC_TCSR_FLEMD (1 << 2) /* Bit 2: FLE Mode */
* (due to CALL or RCALL instruction).
/* Selete the SCIBR register value */
addd #(TOTALFRAME_SIZE-INTFRAME_SIZE)
addd #INTFRAME_SIZE
unsigned short ATTCH:1;
unsigned long ACEND:1;
unsigned long ENDE:1;
* Description : Clear the specified port's ATTCH-bit; "ATTCH Interrupt
* Description : Enable ATTCH (attach) interrupt of the specified USB
* Description : Disable ATTCH (attach) interrupt of the specified USB
* Description : Disable USB Bus Interrupts OVRCR, ATTCH, DTCH, and BCHG.
/* ATTCH status Clear */
/* ATTCH Clear */
/* ATTCH interrupt disable */
/* ATTCH interrupt enable */
/* The previous command is not accepted, leaving the WEL
* as long as the following conditions are aheared to.
as long as the following conditions are aheared to.
* The licence and distribution terms for any publically available version or
The licence and distribution terms for any publically available version or
* The licence and distribution terms for any publically
The licence and distribution terms for any publically
(WEL bit) and in AAI mode (AAI bit).
#define W25QXXXJV_READ_STATUS_1 0x05 /* SRP|SEC|TB |BP2|BP1|BP0|WEL|BUSY */
#define W25QXXXJV_WRITE_STATUS_1 0x01 /* SRP|SEC|TB |BP2|BP1|BP0|WEL|BUSY */
* WEL=1.
* instruction, WEL=1.
ret = apds9960_i2c_write8(priv, APDS9960_GCONFIG4, (GMODE | GIEN));
uint32_t allo = 0;
allo++;
spiffs_gcinfo("Wipe pallo=%" PRIu32 " pdele=%" PRIu32 "\n", allo, dele);
fs->alloc_pages -= allo;
#define XK_Arabic_tehmarbuta 0x05c9 /* U+0629 ARABIC LETTER TEH MARBUTA */
#define XK_Arabic_teh 0x05ca /* U+062A ARABIC LETTER TEH */
#define XK_Greek_LAMDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */
#define XK_Greek_LAMBDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */
#define XK_Greek_lamda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */
#define XK_Greek_lambda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */
#define XK_Armenian_SE 0x100054d /* U+054D ARMENIAN CAPITAL LETTER SEH */
#define XK_Armenian_se 0x100057d /* U+057D ARMENIAN SMALL LETTER SEH */
#define XK_Armenian_VEV 0x100054e /* U+054E ARMENIAN CAPITAL LETTER VEW */
#define XK_Armenian_vev 0x100057e /* U+057E ARMENIAN SMALL LETTER VEW */
#define XK_Sinh_o2 0x1000ddc /* U+0DDC SINHALA KOMBUVA HAA AELA-PILLA*/
#define XK_Sinh_oo2 0x1000ddd /* U+0DDD SINHALA KOMBUVA HAA DIGA AELA-PILLA*/
#define XK_Sinh_au2 0x1000dde /* U+0DDE SINHALA KOMBUVA HAA GAYANUKITTA */
#define GIEN (1 << 1) /* Bit 1: Gesture Interrupt Enable */
/* See also http://vektor.theorem.ca/graphics/ycbcr/ */
* is in froms[] array which points to tos[] array
" + ofo %d"
% ("txbuf", "rxbuf", "ofo", "local_address", "remote_address")
FAR int_fast32_t *offsetp);
FAR int_fast32_t *offsetp)
ans = (FAR struct dns_answer_s *)nameptr;
* been lost). If ORE is set along with RXNE then it tells you
# define WR9_INTACKEN (0x20) /* Bit 5: Software INTACK Enable */
FAR struct dns_answer_s *ans;
* We use RUNSTALL and RESETING signals to ensure that the App core stops
/* Reply with a WONT, that means we will not work in
/* Reply with a WONT */
exten = (extcfg & ADC_CFGR_EXTEN_MASK);
exten = (extcfg & ADC_EXTREG_EXTEN_MASK);
exten = extcfg & ADC_EXTREG_EXTEN_MASK;
if (exten > 0)
setbits = (extsel | exten);
setbits = extsel | exten;
uint32_t exten = 0;
* SPDX-FileContributor: Daniel Pereira Volpato <dpo@certi.org.br>
* SPDX-FileContributor: Guillherme da Silva Amaral <gvr@certi.org.br>
* SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved.
Copyright (C) 2019 Fundação CERTI. All rights reserved.
* SPDX-FileCopyrightText: Fundação CERTI. All rights reserved.
/* TSS (IST) for 64 bit long mode will be filled in up_irq. */
/* IST data structures ******************************************************
/* NOE, NWE, NE1, NBL1 */
/* NOE, NWE, and NE1 */
/* NOE, NWE, and NE3 */
/* NOE, NWE */
* PD4: FSMC NOE PE2: FSMC A23
* SCL High Time: Thi = divider * SCLhi
* Fscl = Finput / (Thi + Tlo)
* If Thi == TloL: Fscl = Finput / (divider * SCL * 2)
* Thi = Tspi * CLKCFG.high
* Fbaud = 1 / (Thi + Tlow)
* If we assume that Thi == Tlow, then:
* Thi = Tspi * CLKCFG.high
* Fbaud = 1 / (2 * Thi)
* Te = (3/2) * p * (lambda_d * i_q - lambda_q * i_d)
* Te = (3/2) * p * (lambda_m * i_q + (L_d - L_q) * i_q * i_d)
* Te = (3/2) * p * i_q * (lambda_m + (L_d - L_q) * i_d)
* Pem = wm * Te
* Te = Tl + Td + B * wm + J * (d/dt) * wm
* Te = Tl + J * (d/dt) * wm
* (d/dt) * wm = (Te - Tl) / J
* Te - electromagnetic torque
* R0 = saveregs = pinter saved array
/* Get EXTEN and EXTSEL from input */
set(SRCS regcomp.c regexec.c regerror.c tre-mem.c)
CSRCS += regcomp.c regexec.c regerror.c tre-mem.c
#include "tre.h"
/* from tre-compile.h
/* from tre-ast.c and tre-ast.h
/* from tre-stack.c and tre-stack.h
/* from tre-parse.c and tre-parse.h
/* from tre-compile.c
/* from tre-mem.h: */
* libs/libc/regex/tre.h
* libs/libc/regex/tre-mem.c
libs/libc/tre.h
libs/libc/tre-mem.c
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define CAN_RERRAR_NCE (1 << 24) /* Bit 24: Non-Correctable Error (NCE) */
#define PINT_PMCTRL_SELPMATCH (1 << 0) /* Bit 0: Rin interrupts interrupt or pattern match function */
#define STR71X_IRQ_T0TOI (29) /* IRQ 29: T0.TOI Timer 0 Overflow interrupt */
#define CP0_CONFIG_KU_SHIFT (25) /* Bits 25-27: KUSEG and USEG cacheability */
#define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
#define FT08X_EFFECT_CHACK 0x58 /* Chack */
#define XK_Thai_fofa 0x0dbd /* U+0E1D THAI CHARACTER FO FA */
* ODER -> disabled
gpioinfo(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n",
uint32_t fpr;
fpr = getreg32(STM32_EXTI_FPR1);
if (((rpr & mask) != 0) || ((fpr & mask) != 0))
* (SPOFF Bits 0-7 = 0xA5) */
* (SPOFF Bits 8-9 = 0); (SPON Bits 8-9 = 0) */
[ESR_ELX_EC_SME] = "SME",
[ESR_ELX_EC_SME] = "SME",
IS_PADD(segment_hdr.load_addr) ? "padd" :
ret = register_mtddriver("/dev/fram", mtd_dev, 0755, NULL);
ret = nx_mount("/dev/fram", "/mnt/lfs", "littlefs", 0,
* TWRITE/TREAD
/* size[4] Tread tag[2] fid[4] offset[8] count[4]
* (see http://csrc.nist.gov/cryptval/shs/sha256-384-512.pdf) uses this
* PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM
leas 2, sp
* To initialize the nCE, configure any PIO as an output pin (refer to Tips
* and Tricks for the supported nCE connection types)
* PCM Clock = (Crystal * (ND + 1 + FRACR/2^22) / (QDPMC + 1)) / 8
/* The Figure of Merit (FoM) characterizing the ranging measurement */
* | 0 | 1 | x | EXT | RIN | IN | off |
* FIFO mode, INT1 , THS 0
* REG03[3] ITERM Termination Current Limit 128-1024mA Default: 256mA

24
.codespellrc
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@ -19,16 +19,20 @@ ignore-words-list =
ACI,
AFE,
afile,
ALS,
AMEBA,
als,
ameba,
ARCHTYPE,
BU,
DAA,
dout,
emac,
eeeprom,
extint,
filp,
finitel,
froms,
FRAM,
FRO,
hart,
hsi,
iif,
@ -37,16 +41,24 @@ ignore-words-list =
inport,
lod,
mot,
NWE,
OEN,
PRES,
mis,
nexted,
numer,
nwe,
oen,
parm,
parms,
pres,
RCALL,
REGONS,
SAIs,
SER,
sie,
ser,
servent,
synopsys,
TE,
TIMOUT,
THRE,
tolen,
UE,
WRON,

8
CMakeLists.txt
View file

@ -158,7 +158,7 @@ if(NOT EXISTS "${NUTTX_DEFCONFIG}")
message(FATAL_ERROR "No config file found at ${NUTTX_DEFCONFIG}")
endif()
# Generate inital .config ###################################################
# Generate initial .config ###################################################
# This is needed right before any other configure step so that we can source
# Kconfig variables into CMake variables
@ -267,7 +267,7 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/boards/dummy/Kconfig)
endif()
endif()
# board platfrom driver
# board platform driver
file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/drivers)
@ -314,7 +314,7 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/chip)
${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/chip)
endif()
# Unsupport custom board/chips yet, workaround
# Unsupported custom board/chips yet, workaround
if(NOT EXISTS ${NUTTX_APPS_BINDIR}/platform/board/Kconfig)
file(MAKE_DIRECTORY ${NUTTX_APPS_BINDIR}/platform/board)
@ -381,7 +381,7 @@ include(nuttx_generate_headers)
include(nuttx_generate_outputs)
include(nuttx_add_library)
# add NuttX CMake extenstion after nuttx_add_library
# add NuttX CMake extension after nuttx_add_library
include(nuttx_extensions)
include(nuttx_add_application)

8
CONTRIBUTING.md
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@ -37,7 +37,7 @@ standardized pull requests processing, as well as long term self-compatibility
and maintenance of the project.
Because every change may affect users, products, or services around the world,
all rules apply equally to all authors, reviewers, committers and maintainters.
all rules apply equally to all authors, reviewers, committers and maintainers.
This is our Check-List for processing every incoming pull request.
Also, we filter out breaking changes and handle them accordingly.
@ -282,7 +282,7 @@ We avoid breaking changes unless absolutely necessary and unavoidable
**mandatory**. Help of the community is welcome.
7. Breaking change requires at least 4 independent positive PR reviews
(see 1.16), all discussions resolved, and zero "request changes".
8. Change must be well documented (buid / runtime test logs, pr, git
8. Change must be well documented (build / runtime test logs, pr, git
commit, documentation, release notes, etc) with clear notes on how to
fix the introduced problems.
9. Breaking Change must be clearly marked with a `[BREAKING]` tag in the
@ -306,7 +306,7 @@ verification and minimizes possible negative impact on various users.
See: https://github.com/apache/nuttx/blob/master/INVIOLABLES.md
### 1.15. Reviews reuqirements.
### 1.15. Review requirements.
Before PR can be merged to the master repository it requires:
@ -409,7 +409,7 @@ as described in requirement 1.7.
* Is new feature added? Is existing feature changed? NO / YES (please describe if yes).
* Impact on user (will user need to adapt to change)? NO / YES (please describe if yes).
* Impact on build (will build process change)? NO / YES (please descibe if yes).
* Impact on build (will build process change)? NO / YES (please describe if yes).
* Impact on hardware (will arch(s) / board(s) / driver(s) change)? NO / YES (please describe if yes).
* Impact on documentation (is update required / provided)? NO / YES (please describe if yes).
* Impact on security (any sort of implications)? NO / YES (please describe if yes).

2
Documentation/ReleaseNotes/NuttX-7.19
View file

@ -317,7 +317,7 @@ for SMP.
- graphics/traveler/tcledit and libwld: Add an X11 Tcl/Tk tool that can
be used to edit Traveler world files.
- Graphics: Remove all NX server taks. Instead, call boardctl() to the
- Graphics: Remove all NX server tasks. Instead, call boardctl() to the
NX server kernel thread.
* Applications: apps/examples:

2
LICENSE
View file

@ -6275,7 +6275,7 @@ libs/libc/stdlib/lib_ldiv.c
libs/libc/stdlib/lib_lldiv.c
=============================
A direct leverage of the div() inplement by:
A direct leverage of the div() implemented by:
Copyright (C) 2015 Stavros Polymenis. All rights reserved.

6
arch/Kconfig
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@ -912,7 +912,7 @@ config PAGING
default n
depends on BUILD_KERNEL && ARCH_USE_MMU && !ARCH_ROMPGTABLE && !LEGACY_PAGING
---help---
If set =y in your configation file, this setting will enable on-demand
If set =y in your configuration file, this setting will enable on-demand
paging, which relies on a MMU to enable larger virtual memory spaces
and map it to physical memory on-demand (usually during a page-fault
exception).
@ -922,7 +922,7 @@ menuconfig LEGACY_PAGING
default n
depends on EXPERIMENTAL && ARCH_USE_MMU && !ARCH_ROMPGTABLE
---help---
If set =y in your configation file, this setting will enable lazy loading
If set =y in your configuration file, this setting will enable lazy loading
backed up by the experimental on-demand paging feature as described in
https://nuttx.apache.org/docs/latest/components/paging.html.
@ -1186,7 +1186,7 @@ config ARCH_MINIMAL_VECTORTABLE
if it occurs will result in an unexpected interrupt crash.
config ARCH_MINIMAL_VECTORTABLE_DYNAMIC
bool "Dynaminc Minimal RAM usage for vector table"
bool "Dynamic Minimal RAM usage for vector table"
default n
depends on ARCH_MINIMAL_VECTORTABLE
---help---

2
arch/arm/include/dm320/irq.h
View file

@ -75,7 +75,7 @@
#define DM320_IRQ_EXT14 35 /* IRQ35: External Interrupt #14 (GIO14) */
#define DM320_IRQ_EXT15 36 /* IRQ36: External Interrupt #15 (GIO15) */
#define DM320_IRQ_PREV0 37 /* IRQ37: Preview Engine 0 (Preview Over) */
#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */
#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Histogram Over) */
#define DM320_IRQ_WDT 39 /* IRQ39: Watchdog Timer Interrupt */
#define DM320_IRQ_I2C 40 /* IRQ40: I2C Interrupt */
#define DM320_IRQ_CLKC 41 /* IRQ41: Clock controller Interrupt (wake up) */

2
arch/arm/include/gd32f4/gd32f4xx_irq.h
View file

@ -209,7 +209,7 @@
#define GD32_IRQ_FPU (GD32_IRQ_EXINT+81) /* 81: FPU interrupt */
#else
#error "Unkonwn GD32F4xx chip."
#error "Unknown GD32F4xx chip."
#endif /* CONFIG_GD32F4_GD32F450 */
#if defined(CONFIG_GD32F4_GD32F450) || defined(CONFIG_GD32F4_GD32F470)

2
arch/arm/include/gd32f4/irq.h
View file

@ -74,7 +74,7 @@
#if defined(CONFIG_GD32F4_GD32F4XX)
# include <arch/gd32f4/gd32f4xx_irq.h>
#else
# error "Uknown GD32 chip"
# error "Unknown GD32 chip"
#endif
/****************************************************************************

12
arch/arm/include/kinetis/chip.h
View file

@ -1224,7 +1224,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
@ -1263,7 +1263,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
@ -1380,7 +1380,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
@ -1419,7 +1419,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
@ -1458,7 +1458,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
@ -1497,7 +1497,7 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 3 /* Three I2C modules */
# define KINETIS_NUART 6 /* Six UART modues */
# define KINETIS_NUART 6 /* Six UART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 1 /* One CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */

2
arch/arm/include/mx8mp/mx8mp_irq.h
View file

@ -207,7 +207,7 @@
#define MX8MP_IRQ_SOFT_GPIO_START MX8MP_IRQ_NVECTORS
/* GPIO1 has dedicated interrupts for pins 0-7, however theses pin are also
/* GPIO1 has dedicated interrupts for pins 0-7, however these pins are also
* connected to the multiplexed IRQ and both can be triggered together is
* enabled. Here we choose to no use the dedicated IRQ.
* REVISIT: add an option to choose the strategy:

8
arch/arm/include/s32k3xx/s32k3x4_irq.h
View file

@ -45,10 +45,10 @@
/* CPU to CPU and Directed Interrupts */
#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interupt 0 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interupt 1 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interupt 2 (Core 0 <-- Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interupt 3 (Core 0 <-- Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interrupt 0 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interrupt 1 (Core 0 --> Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interrupt 2 (Core 0 <-- Core 1) */
#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interrupt 3 (Core 0 <-- Core 1) */
/* Shared Peripheral Interrupts - On-Platform Vectors */

2
arch/arm/include/stm32/stm32g4xxxx_irq.h
View file

@ -167,7 +167,7 @@
#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */
#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math acclerator interrupt */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */
#define STM32_IRQ_NEXTINT (102)
#define NR_IRQS (STM32_IRQ_FIRST + 102)

2
arch/arm/src/am335x/am335x_i2c.c
View file

@ -1557,7 +1557,7 @@ static int am335x_i2c_reset(struct i2c_master_s *dev)
out:
/* Release the port for re-use by other clients */
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;

6
arch/arm/src/arm/arm_allocpage.c
View file

@ -72,15 +72,15 @@ typedef uint32_t l2ndx_t;
/* Free pages in memory are managed by indices ranging from up to
* CONFIG_PAGING_NPAGED. Initially all pages are free so the page can be
* simply allocated in order: 0, 1, 2, ... . After all CONFIG_PAGING_NPAGED
* pages have be filled, then they are blindly freed and re-used in the
* pages have be filled, then they are blindly freed and reused in the
* same order 0, 1, 2, ... because we don't know any better. No smart "least
* recently used" kind of logic is supported.
*/
static pgndx_t g_pgndx;
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used.
* In order to re-used the page, we will have un-map the page from its
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be reused.
* In order to reused the page, we will have un-map the page from its
* previous mapping. In order to that, we need to be able to map a physical
* address to to an index into the PTE where it was mapped. The following
* table supports this backward lookup - it is indexed by the page number

2
arch/arm/src/arm/arm_syscall.c
View file

@ -76,7 +76,7 @@ uint32_t *arm_syscall(uint32_t *regs)
cmd = regs[REG_R0];
/* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid
* should not be overwriten
* should not be overwritten
*/
if (cmd != SYS_restore_context)

2
arch/arm/src/armv6-m/arm_ramvec_attach.c
View file

@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector)
irqstate_t flags;
/* If the new vector is NULL, then the vector is being detached. In
* this case, disable the itnerrupt and direct any interrupts to the
* this case, disable the interrupt and direct any interrupts to the
* common exception handler.
*/

2
arch/arm/src/armv7-a/Kconfig
View file

@ -32,7 +32,7 @@ config ARMV7A_GICV2_LEGACY_IRQ0
int "pci legacy irq0 default val"
default 35
---help---
The qemu pci lagacy irq0 default is 35. -1 mean disable
The qemu pci legacy irq0 default is 35. -1 means disable
config ARMV7A_GICv2M
bool "gic support msi irq"

6
arch/arm/src/armv7-a/arm_allocpage.c
View file

@ -67,15 +67,15 @@ typedef uint32_t l1ndx_t;
/* Free pages in memory are managed by indices ranging from up to
* CONFIG_PAGING_NPAGED. Initially all pages are free so the page can be
* simply allocated in order: 0, 1, 2, ... . After all CONFIG_PAGING_NPAGED
* pages have be filled, then they are blindly freed and re-used in the
* pages have be filled, then they are blindly freed and reused in the
* same order 0, 1, 2, ... because we don't know any better. No smart "least
* recently used" kind of logic is supported.
*/
static pgndx_t g_pgndx;
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used.
* In order to re-used the page, we will have un-map the page from its
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be reused.
* In order to reused the page, we will have un-map the page from its
* previous mapping. In order to that, we need to be able to map a physical
* address to to an index into the PTE where it was mapped. The following
* table supports this backward lookup - it is indexed by the page number

2
arch/arm/src/armv7-a/arm_smpcall.c
View file

@ -56,7 +56,7 @@
*
* 1. It saves the current task state at the head of the current assigned
* task list.
* 2. It porcess g_delivertasks
* 2. It processes g_delivertasks
* 3. Returns from interrupt, restoring the state of the new task at the
* head of the ready to run list.
*

2
arch/arm/src/armv7-a/arm_syscall.c
View file

@ -184,7 +184,7 @@ uint32_t *arm_syscall(uint32_t *regs)
cmd = regs[REG_R0];
/* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid
* should not be overwriten
* should not be overwritten
*/
if (cmd != SYS_restore_context)

2
arch/arm/src/armv7-a/arm_vectors.S
View file

@ -48,7 +48,7 @@
* Name: cpuindex
*
* Description:
* Return an index idenifying the current CPU. Single CPU case. Must be
* Return an index identifying the current CPU. Single CPU case. Must be
* provided by MCU-specific logic in chip.h for the SMP case.
*
****************************************************************************/

2
arch/arm/src/armv7-a/gic.h
View file

@ -843,7 +843,7 @@ int arm_start_handler(int irq, void *context, void *arg);
*
* 1. It saves the current task state at the head of the current assigned
* task list.
* 2. It porcess g_delivertasks
* 2. It processes g_delivertasks
* 3. Returns from interrupt, restoring the state of the new task at the
* head of the ready to run list.
*

2
arch/arm/src/armv7-m/arm_exception.S
View file

@ -177,7 +177,7 @@ exception_common:
*/
#if CONFIG_ARCH_INTERRUPTSTACK < 7
/* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will re-use the
/* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will reuse the
* interrupted thread's stack. That may mean using either MSP or PSP
* stack for interrupt level processing (in kernel mode).
*/

2
arch/arm/src/armv7-m/arm_ramvec_attach.c
View file

@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector)
irqstate_t flags;
/* If the new vector is NULL, then the vector is being detached. In
* this case, disable the itnerrupt and direct any interrupts to the
* this case, disable the interrupt and direct any interrupts to the
* common exception handler.
*/

2
arch/arm/src/armv7-m/etm.h
View file

@ -533,7 +533,7 @@
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /* Bit mask for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Start/Stop Block Uses EmbeddedICE watchpoint inputs */
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /* Shift value for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /* Bit mask for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */

2
arch/arm/src/armv7-m/nvic.h
View file

@ -187,7 +187,7 @@
#define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */
#define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */
#define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */
#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control registr */
#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control register */
#define NVIC_SYSCON_OFFSET 0x0d10 /* System control register */
#define NVIC_CFGCON_OFFSET 0x0d14 /* Configuration control register */
#define NVIC_SYSH_PRIORITY_OFFSET(n) (0x0d14 + 4*((n) >> 2))

2
arch/arm/src/armv7-r/arm_mpu.c
View file

@ -486,7 +486,7 @@ unsigned int mpu_configure_region(uintptr_t base, size_t size,
* Configure a region for privileged, strongly ordered memory
*
* Input Parameters:
* table - MPU Initiaze table.
* table - MPU Initialize table.
* count - Initialize the number of entries in the region table.
*
* Returned Value:

2
arch/arm/src/armv7-r/arm_smpcall.c
View file

@ -56,7 +56,7 @@
*
* 1. It saves the current task state at the head of the current assigned
* task list.
* 2. It porcess g_delivertasks
* 2. It processes g_delivertasks
* 3. Returns from interrupt, restoring the state of the new task at the
* head of the ready to run list.
*

2
arch/arm/src/armv7-r/arm_syscall.c
View file

@ -181,7 +181,7 @@ uint32_t *arm_syscall(uint32_t *regs)
cmd = regs[REG_R0];
/* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid
* should not be overwriten
* should not be overwritten
*/
if (cmd != SYS_restore_context)

2
arch/arm/src/armv7-r/gic.h
View file

@ -813,7 +813,7 @@ int arm_start_handler(int irq, void *context, void *arg);
*
* 1. It saves the current task state at the head of the current assigned
* task list.
* 2. It porcess g_delivertasks
* 2. It processes g_delivertasks
* 3. Returns from interrupt, restoring the state of the new task at the
* head of the ready to run list.
*

4
arch/arm/src/armv7-r/mpu.h
View file

@ -337,7 +337,7 @@ unsigned int mpu_configure_region(uintptr_t base, size_t size,
* Configure a region for privileged, strongly ordered memory
*
* Input Parameters:
* table - MPU Initiaze table.
* table - MPU Initialize table.
* count - Initialize the number of entries in the region table.
*
* Returned Value:
@ -690,7 +690,7 @@ static inline void mpu_control(bool enable)
* Name: mpu_peripheral
*
* Description:
* Configure a region as privileged periperal address space
* Configure a region as privileged peripheral address space
*
****************************************************************************/

2
arch/arm/src/armv7-r/scu.h
View file

@ -53,7 +53,7 @@
#define SCU_DEBUGRAM_OFFSET 0x0070 /* SCU Debug Tag RAM Operation Register */
#define SCU_DEBUGRAMDATA_OFFSET 0x0074 /* SCU Debug Tag RAM Data Value Register */
#define SCU_DEBUGRAMECC_OFFSET 0x0078 /* SCU Debug Tag RAM ECC Chunk Register */
#define SCU_ECCERR_OFFSET 0x007c /* ECC Fatal Error Registe */
#define SCU_ECCERR_OFFSET 0x007c /* ECC Fatal Error Register */
#define SCU_FPPFILTERSTART_OFFSET(n) (0x0080 + (n)*8) /* FPP Filtering Start Address Register for core n */
#define SCU_FPPFILTEREND_OFFSET(n) (0x0084 + (n)*8) /* FPP Filtering End Address Register for core n */

2
arch/arm/src/armv8-m/arm_exception.S
View file

@ -188,7 +188,7 @@ exception_common:
mrs r0, ipsr
#if CONFIG_ARCH_INTERRUPTSTACK < 7
/* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will re-use the
/* If CONFIG_ARCH_INTERRUPTSTACK is not defined, we will reuse the
* interrupted thread's stack. That may mean using either MSP or PSP
* stack for interrupt level processing (in kernel mode).
*/

8
arch/arm/src/armv8-m/arm_gen_nonsecfault.c
View file

@ -81,13 +81,13 @@ bool weak_function arm_should_gen_nonsecurefault(void)
*
* Description:
* For TEE & REE, securefault & busfault are not banked, so the faults can
* only forword to TEE/REE.
* only forward to TEE/REE.
* But how to crash dump the other core which not handled faults ?
*
* Here we provide a way to resolve this problem:
* 1. Set the securefault & busfault to TEE
* 2. busfault happend from TEE, then directly dump TEE
* 3. busfault happend from REE, then generate nonsecurefault
* 2. busfault happened from TEE, then directly dump TEE
* 3. busfault happened from REE, then generate nonsecurefault
* 4. Back to REE, and dump
*
* Return values:
@ -121,7 +121,7 @@ int arm_gen_nonsecurefault(int irq, uint32_t *regs)
return 0;
}
/* Redict busfault to REE */
/* Redirect busfault to REE */
up_secure_irq(NVIC_IRQ_BUSFAULT, false);
}

2
arch/arm/src/armv8-m/arm_ramvec_attach.c
View file

@ -71,7 +71,7 @@ int arm_ramvec_attach(int irq, up_vector_t vector)
irqstate_t flags;
/* If the new vector is NULL, then the vector is being detached. In
* this case, disable the itnerrupt and direct any interrupts to the
* this case, disable the interrupt and direct any interrupts to the
* common exception handler.
*/

4
arch/arm/src/armv8-m/etm.h
View file

@ -277,7 +277,7 @@
#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /* Bit mask for ETM_TRACESS */
#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /* Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /* Coprocessor and Memeory Access */
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /* Coprocessor and Memory Access */
#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /* Shift value for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /* Bit mask for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCR */
@ -533,7 +533,7 @@
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /* Bit mask for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /* Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /* Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /* Trace Start/Stop Block Uses EmbeddedICE watchpoint inputs */
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /* Shift value for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /* Bit mask for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /* Mode DEFAULT for ETM_ETMCCER */

2
arch/arm/src/armv8-m/nvic.h
View file

@ -207,7 +207,7 @@
#define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */
#define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */
#define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */
#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control registr */
#define NVIC_AIRCR_OFFSET 0x0d0c /* Application interrupt/reset control register */
#define NVIC_SYSCON_OFFSET 0x0d10 /* System control register */
#define NVIC_CFGCON_OFFSET 0x0d14 /* Configuration control register */
#define NVIC_SYSH_PRIORITY_OFFSET(n) (0x0d14 + 4*((n) >> 2))

2
arch/arm/src/armv8-r/arm_syscall.c
View file

@ -181,7 +181,7 @@ uint32_t *arm_syscall(uint32_t *regs)
cmd = regs[REG_R0];
/* if cmd == SYS_restore_context (*running_task)->xcp.regs is valid
* should not be overwriten
* should not be overwritten
*/
if (cmd != SYS_restore_context)

48
arch/arm/src/at32/Kconfig
View file

@ -4431,10 +4431,10 @@ config AT32_TIM1_CHANNEL
channel {1,..,4}
config AT32_TIM1_CLOCK
int "TIM1 work frequence for capture"
int "TIM1 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM1_CAP
@ -4460,10 +4460,10 @@ config AT32_TIM2_CHANNEL
channel {1,..,4}
config AT32_TIM2_CLOCK
int "TIM2 work frequence for capture"
int "TIM2 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM2_CAP
@ -4489,10 +4489,10 @@ config AT32_TIM3_CHANNEL
channel {1,..,4}
config AT32_TIM3_CLOCK
int "TIM3 work frequence for capture"
int "TIM3 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM3_CAP
@ -4518,10 +4518,10 @@ config AT32_TIM4_CHANNEL
channel {1,..,4}
config AT32_TIM4_CLOCK
int "TIM4 work frequence for capture"
int "TIM4 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM4_CAP
@ -4547,10 +4547,10 @@ config AT32_TIM5_CHANNEL
channel {1,..,4}
config AT32_TIM5_CLOCK
int "TIM5 work frequence for capture"
int "TIM5 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM5_CAP
@ -4576,10 +4576,10 @@ config AT32_TIM8_CHANNEL
channel {1,..,4}
config AT32_TIM8_CLOCK
int "TIM8 work frequence for capture"
int "TIM8 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM8_CAP
@ -4605,10 +4605,10 @@ config AT32_TIM9_CHANNEL
channel {1,..,4}
config AT32_TIM9_CLOCK
int "TIM9 work frequence for capture"
int "TIM9 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM9_CAP
@ -4634,10 +4634,10 @@ config AT32_TIM10_CHANNEL
channel {1,..,4}
config AT32_TIM10_CLOCK
int "TIM10 work frequence for capture"
int "TIM10 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM10_CAP
@ -4663,10 +4663,10 @@ config AT32_TIM11_CHANNEL
channel {1,..,4}
config AT32_TIM11_CLOCK
int "TIM11 work frequence for capture"
int "TIM11 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM11_CAP
@ -4692,10 +4692,10 @@ config AT32_TIM12_CHANNEL
channel {1,..,4}
config AT32_TIM12_CLOCK
int "TIM12 work frequence for capture"
int "TIM12 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM12_CAP
@ -4721,10 +4721,10 @@ config AT32_TIM13_CHANNEL
channel {1,..,4}
config AT32_TIM13_CLOCK
int "TIM13 work frequence for capture"
int "TIM13 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM13_CAP
@ -4750,10 +4750,10 @@ config AT32_TIM14_CHANNEL
channel {1,..,4}
config AT32_TIM14_CLOCK
int "TIM14 work frequence for capture"
int "TIM14 work frequency for capture"
default 1000000
---help---
This clock frequence limiting the count rate at the expense of resolution.
This clock frequency limiting the count rate at the expense of resolution.
endif # AT32_TIM14_CAP

8
arch/arm/src/at32/at32_eth.c
View file

@ -1510,7 +1510,7 @@ static int at32_recvframe(struct at32_ethmac_s *priv)
* 3) All of the TX descriptors are in flight.
*
* This last case is obscure. It is due to that fact that each packet
* that we receive can generate an unstoppable transmisson. So we have
* that we receive can generate an unstoppable transmission. So we have
* to stop receiving when we can not longer transmit. In this case, the
* transmit logic should also have disabled further RX interrupts.
*/
@ -1769,7 +1769,7 @@ static void at32_receive(struct at32_ethmac_s *priv)
}
/* We are finished with the RX buffer. NOTE: If the buffer is
* re-used for transmission, the dev->d_buf field will have been
* reused for transmission, the dev->d_buf field will have been
* nullified.
*/
@ -2003,11 +2003,11 @@ static void at32_interrupt_work(void *arg)
at32_putreg(ETH_DMAINT_NIS, AT32_ETH_DMASR);
}
/* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */
/* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */
#ifdef CONFIG_DEBUG_NET
/* Check if there are pending "anormal" interrupts */
/* Check if there are pending "abnormal" interrupts */
if ((dmasr & ETH_DMAINT_AIS) != 0)
{

2
arch/arm/src/at32/at32_i2c.c
View file

@ -2496,7 +2496,7 @@ static int at32_i2c_reset(struct i2c_master_s *dev)
out:
/* Release the port for re-use by other clients */
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;

6
arch/arm/src/at32/at32_otgfsdev.c
View file

@ -2230,8 +2230,8 @@ static inline void at32_ep0out_testmode(struct at32_usbdev_s *priv,
* Name: at32_ep0out_stdrequest
*
* Description:
* Handle a stanard request on EP0. Pick off the things of interest to the
* USB device controller driver; pass what is left to the class driver.
* Handle a standard request on EP0. Pick off the things of interest to
* the USB device controller driver; pass what is left to the class driver.
*
****************************************************************************/
@ -5646,7 +5646,7 @@ void arm_usbinitialize(void)
arm_usbuninitialize();
/* Initialie the driver data structure */
/* Initialize the driver data structure */
at32_swinitialize(priv);

2
arch/arm/src/at32/at32_otgfshost.c
View file

@ -2774,7 +2774,7 @@ static inline void at32_gint_hcoutisr(struct at32_usbhost_s *priv,
else if ((pending & OTGFS_HCINT_STALL) != 0)
{
/* Clear the pending the STALL response receiv (STALL) interrupt */
/* Clear the pending the STALL response receive (STALL) interrupt */
at32_putreg(AT32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL);

8
arch/arm/src/at32/at32_pwm.c
View file

@ -2800,7 +2800,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev,
uint32_t ccer = 0;
uint32_t regval = 0;
/* Get curren register state */
/* Get current register state */
ccer = pwm_getreg(priv, AT32_GTIM_CCER_OFFSET);
@ -2823,7 +2823,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev,
if (state == true)
{
/* Enable outpus - set bits */
/* Enable outputs - set bits */
ccer |= regval;
}
@ -2886,7 +2886,7 @@ errout:
* Name: pwm_trgo_configure
*
* Description:
* Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2)
* Configure an output synchronisation event for PWM timer (TRGO/TRGO2)
*
****************************************************************************/
@ -2989,7 +2989,7 @@ static uint16_t pwm_outputs_from_channels(struct at32_pwmtimer_s *priv)
if (channel != 0)
{
/* Enable output if confiugred */
/* Enable output if configured */
if (priv->channels[i].out1.in_use == 1)
{

2
arch/arm/src/at32/at32_sdio.c
View file

@ -2189,7 +2189,7 @@ static int at32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested response (due to
* failure means only a failure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.

2
arch/arm/src/at32/at32_serial.c
View file

@ -246,7 +246,7 @@ struct up_dev_s
#ifdef SERIAL_HAVE_TXDMA
const unsigned int txdma_channel; /* DMA channel assigned */
DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */
DMA_HANDLE txdma; /* currently-open transmit DMA stream */
#endif
#ifdef SERIAL_HAVE_RXDMA

2
arch/arm/src/at32/hardware/at32f43xxx_rcc.h
View file

@ -215,7 +215,7 @@
# define CRM_CFG_CLKOUT2DIV1_1_4 (6 << CRM_CFG_CLKOUT2DIV1_SHIFT) /* CLKOUT2/4 */
# define CRM_CFG_CLKOUT2DIV1_1_5 (7 << CRM_CFG_CLKOUT2DIV1_SHIFT) /* CLKOUT2/5 */
#define CRM_CFG_CLKOUT2_SEL1_SHIFT (30) /* clock output2 selecction 1 */
#define CRM_CFG_CLKOUT2_SEL1_SHIFT (30) /* clock output2 selection 1 */
#define CRM_CFG_CLKOUT2_SEL1_MASK (3 << CRM_CFG_CLKOUT2_SEL1_SHIFT)
# define CRM_CFG_CLKOUT2_SEL1_SCLK (0 << CRM_CFG_CLKOUT2_SEL1_SHIFT) /* Output from SCLK */
# define CRM_CFG_CLKOUT2_SEL1_2 (1 << CRM_CFG_CLKOUT2_SEL1_SHIFT) /* Output determine from CRM_MISC1 */

2
arch/arm/src/c5471/c5471_irq.c
View file

@ -76,7 +76,7 @@ static up_vector_t g_vectorinittab[] =
* Name: up_ackirq
*
* Description:
* Acknowlede the IRQ.Bit 0 of the Interrupt Control
* Acknowledge the IRQ.Bit 0 of the Interrupt Control
* Register == New IRQ agreement (NEW_IRQ_AGR). Reset IRQ
* output. Clear source IRQ register. Enables a new IRQ
* generation. Reset by internal logic.

2
arch/arm/src/c5471/chip.h
View file

@ -62,7 +62,7 @@
#define ENET0_FLWCONTROL 0xffff0110 /* Flow control register */
#define ENET0_VTYPE 0xffff0114 /* VTYPE tag register */
#define ENET0_SEISR 0xffff0118 /* System error int status register */
#define ENET0_TXBUFRDY 0xffff011c /* TX descripter buffer ready */
#define ENET0_TXBUFRDY 0xffff011c /* TX descriptor buffer ready */
#define ENET0_TDBA 0xffff0120 /* TX descriptor base address */
#define ENET0_RDBA 0xffff0124 /* RX descriptor base address */
#define ENET0_PARHI 0xffff0128 /* Dest phys address match (HI) */

2
arch/arm/src/common/arm_backtrace_sp.c
View file

@ -35,7 +35,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Macro and definitions for simple decoding of instuctions.
/* Macro and definitions for simple decoding of instructions.
* To check an instruction, it is ANDed with the IMASK_ and
* the result is compared with the IOP_. The macro INSTR_IS
* does this and returns !0 to indicate a match.

2
arch/arm/src/common/arm_backtrace_unwind.c
View file

@ -233,7 +233,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_s *ctrl)
* Name: unwind_pop_register
*
* Description:
* Before poping a register check whether it is feasible or not
* Before popping a register check whether it is feasible or not
*
****************************************************************************/

2
arch/arm/src/cxd32xx/cxd32_serial.c
View file

@ -328,7 +328,7 @@ static void up_set_format(struct uart_dev_s *dev)
up_serialout(priv, CXD32_UART_LCR_H, lcr);
/* CXD32 does not have CTS/RTS pin, so these are disbled */
/* CXD32 does not have CTS/RTS pin, so these are disabled */
cr &= ~(UART_CR_RTSEN | UART_CR_CTSEN);
up_serialout(priv, CXD32_UART_CR, cr | cr_en);

4
arch/arm/src/cxd32xx/cxd32_timerisr.c
View file

@ -54,7 +54,7 @@
#define TICK_RELOAD ((CXD32_TIMER_BASEFREQ / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify taht the reload value
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
@ -140,7 +140,7 @@ static void cxd32_timer1_initialize(void)
{
uint32_t ctrl;
/* Configure the coutner */
/* Configure the counter */
putreg32(TIMER4_CH1_INITVALUE, TIMER4_CH1 + CXD32_TIMER_LOAD);

2
arch/arm/src/cxd32xx/cxd32_uart.c
View file

@ -219,7 +219,7 @@ void cxd32_uart_reset(int ch)
void cxd32_uart_setup(int ch)
{
/* XXX: enabling uart contrller */
/* XXX: enabling uart controller */
}
/****************************************************************************

2
arch/arm/src/cxd32xx/hardware/cxd32_timer.h
View file

@ -41,7 +41,7 @@
#define CXD32_TIMER_INTCLR (0x000C) /* Clear Interrupt register [WO] */
#define CXD32_TIMER_RIS (0x0010) /* Raw Interrupt Status register [RO] */
#define CXD32_TIMER_MIS (0x0014) /* Interrupt Status register [RO] */
#define CXD32_TIMER_BGLOAD (0x0018) /* Backround Load register [RO] */
#define CXD32_TIMER_BGLOAD (0x0018) /* Background Load register [RO] */
#define CXD32_TIMER_ITCR (0x0F00) /* Integration Test Control register */
#define CXD32_TIMER_ITOP (0x0F04) /* Integration Test Output register [WO] */
#define CXD32_TIMER_PERIPHID0 (0x0FE0) /* Peripheral ID0 register [RO] */

2
arch/arm/src/cxd56xx/Kconfig
View file

@ -1093,7 +1093,7 @@ config CXD56_SCU_PREDIV
default 64
range 1 256
---help---
This configuration ralated to maximum sampling rate based
This configuration related to maximum sampling rate based
on 32.768KHz.
e.g. 32768 / 64 = 512 (samples)

2
arch/arm/src/cxd56xx/cxd56_clock.c
View file

@ -296,7 +296,7 @@ static void do_power_control2(uint32_t reg1, uint32_t mask1, uint32_t stat1,
static inline void release_pwd_reset(uint32_t domain)
{
/* Reset acts only belows
/* Reset affects only:
* [ 0] SCU
* [ 6] SYSIOP_SUB
* [ 8] APP

2
arch/arm/src/cxd56xx/cxd56_cpu1signal.h
View file

@ -23,7 +23,7 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPU1SIGNAL_H
/* CPU1 Notifyable functions */
/* CPU1 Notifiable functions */
#define CXD56_CPU1_DATA_TYPE_GNSS 0
#define CXD56_CPU1_DATA_TYPE_GEOFENCE 1

2
arch/arm/src/cxd56xx/cxd56_nxaudio.h
View file

@ -278,7 +278,7 @@ struct cxd56_dev_s
#ifdef CONFIG_AUDIO_CXD56_SRC
struct dq_queue_s down_pendq; /* Pending SRC buffers to be DMA'd */
struct dq_queue_s down_runq; /* SRC buffers being processed */
struct dq_queue_s down_doneq; /* Done SRC buffers to be re-used */
struct dq_queue_s down_doneq; /* Done SRC buffers to be reused */
#endif
uint32_t samplerate; /* Sample rate */

2
arch/arm/src/cxd56xx/cxd56_pwm.c
View file

@ -254,7 +254,7 @@ static int convert_freq2period(uint32_t freq, ub16_t duty, uint32_t *param,
return -1;
}
/* calcurate prescale */
/* calculate prescale */
if ((freq << 8) < (pwmfreq >> 8))
{

2
arch/arm/src/cxd56xx/cxd56_rtc.c
View file

@ -582,7 +582,7 @@ int cxd56_rtc_setalarm(struct alm_setalarm_s *alminfo)
count -= g_rtc_save->offset;
/* clear previsous setting */
/* clear previous setting */
mask = RTCREG_ALM0_ERR_FLAG_MASK | RTCREG_ALM0_FLAG_MASK;
mask <<= id;

2
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -2189,7 +2189,7 @@ static int cxd56_sdio_waitresponse(struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested response (due to
* failure means only a failure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.

2
arch/arm/src/cxd56xx/cxd56_sdhci.h
View file

@ -221,7 +221,7 @@ extern "C"
#define SDHCI_SYSCTL_ICLKEN (1 << 0) /* Bit 0: Internal Clock Enable */
#define SDHCI_SYSCTL_ICLKSTA (1 << 1) /* Bit 1: Internal Clock Stable */
#define SDHCI_SYSCTL_SDCLKEN (1 << 2) /* Bit 2: SD Clock Enable */
#define SDHCI_SYSCTL_GENSEL (1 << 5) /* Bit 5: Clock Generetor Select */
#define SDHCI_SYSCTL_GENSEL (1 << 5) /* Bit 5: Clock Generator Select */
#define SDHCI_SYSCTL_SDCLKFSUP_SHIFT (6) /* Bits 6-7: Divisor */
#define SDHCI_SYSCTL_SDCLKFSUP_MASK (3 << SDHCI_SYSCTL_SDCLKFSUP_SHIFT)
#define SDHCI_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */

6
arch/arm/src/cxd56xx/cxd56_usbdev.c
View file

@ -2914,7 +2914,7 @@ static void cxd56_epinitialize(struct cxd56_usbdev_s *priv)
priv->usbdev.ep0 = &priv->eplist[0].ep;
/* Initilialize USB hardware */
/* Initialize USB hardware */
for (i = 1; i < CXD56_NENDPOINTS; i++)
{
@ -2996,7 +2996,7 @@ static int cxd56_vbusinterrupt(int irq, void *context, void *arg)
}
/* Notify attach signal.
* if class driver not binded, can't get supply curret value.
* if class driver not bound, can't get supply current value.
*/
if (!priv->driver)
@ -3307,7 +3307,7 @@ static void cxd56_usbreset(struct cxd56_usbdev_s *priv)
mask &= ~(1 << i << (priv->eplist[i].in ? 0 : 16));
putreg32(mask, CXD56_USB_DEV_EP_INTR_MASK);
/* DMA descripter setting */
/* DMA descriptor setting */
priv->eplist[i].buffer = NULL;
priv->eplist[i].desc->status = DESC_BS_HOST_BUSY;

2
arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h
View file

@ -35,7 +35,7 @@
/* Set the standard pinconf macro Definitions
* - If it's used as input pin, then set 1. Otherwise set 0 (default).
* - If it's drived in 4mA, then set 1. Otherwise set 0 (default 2mA).
* - If it's driven with 4mA, then set 1. Otherwise set 0 (default 2mA).
* - If it's used as weak pull-up/down,
* then set PINCONF_PULLUP/PINCONF_PULLDOWN.
* Otherwise set 0 (default).

2
arch/arm/src/dm320/dm320_framebuffer.c
View file

@ -771,7 +771,7 @@ static void dm320_disable(void)
{
/* Disable all planes */
ginfo("Inactivate OSD:\n");
ginfo("Deactivate OSD:\n");
putreg16(0, DM320_OSD_OSDWIN0MD); /* Win0 mode = 0 (1:active) */
putreg16(0, DM320_OSD_OSDWIN1MD); /* Win1 mode = 0 (1:active) */

4
arch/arm/src/dm320/dm320_usbdev.c
View file

@ -1709,7 +1709,7 @@ static int dm320_ctlrinterrupt(int irq, void *context, void *arg)
* Name: dm320_attachinterrupt
*
* Description:
* Attach GIO interrtup handler
* Attach GIO interrupt handler
*
****************************************************************************/
@ -2485,7 +2485,7 @@ void arm_usbinitialize(void)
GIO_OUTPUT(CONFIG_DM320_GIO_USBDPPULLUP);
GIO_SET_OUTPUT(CONFIG_DM320_GIO_USBDPPULLUP);
/* Initilialize USB attach GIO */
/* Initialize USB attach GIO */
GIO_INTERRUPT(CONFIG_DM320_GIO_USBATTACH);
GIO_BOTHEDGES(CONFIG_DM320_GIO_USBATTACH);

2
arch/arm/src/efm32/efm32_i2c.c
View file

@ -1595,7 +1595,7 @@ int efm32_i2c_reset(struct i2c_master_s *dev)
out:
/* Release the port for re-use by other clients */
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;

4
arch/arm/src/efm32/efm32_usbdev.c
View file

@ -2121,7 +2121,7 @@ static inline void efm32_ep0out_testmode(struct efm32_usbdev_s *priv,
* Name: efm32_ep0out_stdrequest
*
* Description:
* Handle a stanard request on EP0. Pick off the things of interest to
* Handle a standard request on EP0. Pick off the things of interest to
* the USB device controller driver; pass what is left to the class driver.
*
****************************************************************************/
@ -5591,7 +5591,7 @@ void arm_usbinitialize(void)
arm_usbuninitialize();
/* Initialie the driver data structure */
/* Initialize the driver data structure */
efm32_swinitialize(priv);

2
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -2793,7 +2793,7 @@ static inline void efm32_gint_hcoutisr(struct efm32_usbhost_s *priv,
else if ((pending & USB_HC_INT_STALL) != 0)
{
/* Clear the pending the STALL response receiv (STALL) interrupt */
/* Clear the pending the STALL response receive (STALL) interrupt */
efm32_putreg(EFM32_USB_HC_INT(chidx), USB_HC_INT_STALL);

4
arch/arm/src/gd32f4/gd32f4xx_dma.c
View file

@ -566,7 +566,7 @@ void weak_function arm_dma_initialize(void)
* gd32_dma_channel_free().
*
* Input Parameters:
* periph_req - Identifies the DMA channle is request by which peripheral
* periph_req - Identifies the DMA channel is request by which peripheral
*
* Returned Value:
* If periph_req is valid, this function ALWAYS returns a non-NULL
@ -704,7 +704,7 @@ void gd32_dma_singlemode_setup(struct gd32_dma_channel_s *dmachan,
regaddr = GD32_DMA_CHCNT(dmachan->dmabase, dmachan->chan_num);
putreg32(init_struct->number, regaddr);
/* Configure peripheral and memory transfer width, channel priotity,
/* Configure peripheral and memory transfer width, channel priority,
* transfer mode
*/

2
arch/arm/src/gd32f4/gd32f4xx_dma.h
View file

@ -135,7 +135,7 @@ extern "C"
* gd32_dma_channel_free().
*
* Input Parameters:
* periph_req - Identifies the DMA channle is request by which peripheral
* periph_req - Identifies the DMA channel is request by which peripheral
*
* Returned Value:
* If periph_req is valid, this function ALWAYS returns a non-NULL

10
arch/arm/src/gd32f4/gd32f4xx_enet.c
View file

@ -839,7 +839,7 @@ static void gd32_enet_clock_enable(void)
regaddr = GD32_RCU_AHB1EN;
/* Check clock if alreay enable. */
/* Check clock if already enable. */
if (rcu_en != (rcu_en & getreg32(regaddr)))
{
@ -1492,7 +1492,7 @@ static int gd32_receive_frame(struct gd32_enet_mac_s *priv)
* 3) All of the TX descriptors are in flight.
*
* This last case is obscure. It is due to that fact that each packet
* that we receive can generate an unstoppable transmisson. So we have
* that we receive can generate an unstoppable transmission. So we have
* to stop receiving when we can not longer transmit. In this case, the
* transmit logic should also have disabled further RX interrupts.
*/
@ -1730,7 +1730,7 @@ static void gd32_receive(struct gd32_enet_mac_s *priv)
}
/* We are finished with the RX buffer. NOTE: If the buffer is
* re-used for transmission, the dev->d_buf field will have been
* reused for transmission, the dev->d_buf field will have been
* nullified.
*/
@ -1965,11 +1965,11 @@ static void gd32_interrupt_work(void *arg)
gd32_reg_write(ENET_DMA_INTEN_NIE, GD32_ENET_DMA_STAT);
}
/* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */
/* Handle error interrupt only if CONFIG_DEBUG_NET is enabled */
#ifdef CONFIG_DEBUG_NET
/* Check if there are pending "anormal" interrupts */
/* Check if there are pending "abnormal" interrupts */
if ((dma_reg & ENET_DMA_STAT_AI) != 0)
{

2
arch/arm/src/gd32f4/gd32f4xx_gpio.c
View file

@ -318,7 +318,7 @@ int gd32_gpio_config(uint32_t cfgset)
port_base = g_gpio_base[port];
/* Eable the GPIO port clock */
/* Enable the GPIO port clock */
gd32_gpio_clock_enable(port_base);

2
arch/arm/src/gd32f4/gd32f4xx_i2c.c
View file

@ -2555,7 +2555,7 @@ static int gd32_i2c_reset(struct i2c_master_s *dev)
out:
/* Release the port for re-use by other clients */
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;

2
arch/arm/src/gd32f4/gd32f4xx_sdio.c
View file

@ -2155,7 +2155,7 @@ static int gd32_wait_response(struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested response (due to
* failure means only a failure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.

8
arch/arm/src/gd32f4/gd32f4xx_serial.c
View file

@ -176,7 +176,7 @@ struct up_dev_s
#ifdef SERIAL_HAVE_TXDMA
const uint32_t txdma_channel; /* DMA channel assigned */
DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */
DMA_HANDLE txdma; /* currently-open transmit DMA stream */
#endif
/* RX DMA state */
@ -1982,7 +1982,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
# endif
#endif
/* Only availible in USART0,1,2,5 */
/* Only available in USART0,1,2,5 */
#ifdef CONFIG_GD32F4_USART_INVERT
case TIOCSINVERT:
@ -2379,7 +2379,7 @@ static void up_dma_tx_callback(DMA_HANDLE handle, uint16_t status, void *arg)
dma_init_struct.priority = USART_DMA_PRIO;
dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_DISABLE;
/* Configure DMA for USART transmmit */
/* Configure DMA for USART transmit */
gd32_dma_setup(priv->txdma, &dma_init_struct, 1);
@ -2470,7 +2470,7 @@ static void up_dma_send(struct uart_dev_s *dev)
dma_init_struct.priority = USART_DMA_PRIO;
dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_DISABLE;
/* Configure DMA for USART transmmit */
/* Configure DMA for USART transmit */
gd32_dma_setup(priv->txdma, &dma_init_struct, 1);

2
arch/arm/src/gd32f4/gd32f4xx_spi.c
View file

@ -1080,7 +1080,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t actual;
uint32_t plk_div;
/* Check if the requested frequence is the same as the frequency
/* Check if the requested frequency is the same as the frequency
* selection.
*/

2
arch/arm/src/gd32f4/gd32f4xx_syscfg.c
View file

@ -217,7 +217,7 @@ void gd32_syscfg_clock_enable(void)
regaddr = GD32_RCU_APB2EN;
/* Check clock if alreay enable. */
/* Check clock if already enable. */
if (rcu_en != (rcu_en & getreg32(regaddr)))
{

2
arch/arm/src/gd32f4/gd32f4xx_usart.h
View file

@ -494,7 +494,7 @@
*
* 24-bit Encoding: 2222 2222 1111 1111 1100 0000 0000
* 7654 3210 9876 5432 1098 7654 3210
* ENCODING SHIF
* ENCODING SHIFT
*
* CTL SHIFT: Bit24-27, CTL2 int: Bit8-23, CTL3 int: Bit6-7,
* CTL1 int: Bit5, CTL0 int: Bit0-4,

2
arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h
View file

@ -189,7 +189,7 @@
/* DMA_CHxCTL,x=0..7 */
#define DMA_CHXCTL_CHEN (1 << 0) /* Bit 0: channel x enable */
#define DMA_CHXCTL_SDEIE (1 << 1) /* Bit 1: enable bit for channel x single data mode exception interrupt */
#define DMA_CHXCTL_TAEIE (1 << 2) /* Bit 2: enable bit for channel x tranfer access error interrupt */
#define DMA_CHXCTL_TAEIE (1 << 2) /* Bit 2: enable bit for channel x transfer access error interrupt */
#define DMA_CHXCTL_HTFIE (1 << 3) /* Bit 3: enable bit for channel x half transfer finish interrupt */
#define DMA_CHXCTL_FTFIE (1 << 4) /* Bit 4: enable bit for channel x full transfer finish interrupt */
#define DMA_CHXCTL_TFCS (1 << 5) /* Bit 5: transfer flow controller select */

8
arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h
View file

@ -50,7 +50,7 @@
#define GD32_ENET_MAC_FCTL_OFFSET 0x0018 /* MAC flow control register offset */
#define GD32_ENET_MAC_VLT_OFFSET 0x001C /* MAC VLAN tag register offset */
#define GD32_ENET_MAC_RWFF_OFFSET 0x0028 /* MAC remote wakeup frame filter register offset */
#define GD32_ENET_MAC_WUM_OFFSET 0x002C /* MAC wakeup managenment register offset */
#define GD32_ENET_MAC_WUM_OFFSET 0x002C /* MAC wakeup management register offset */
#define GD32_ENET_MAC_DBG_OFFSET 0x0034 /* MAC debug register offset */
#define GD32_ENET_MAC_INTF_OFFSET 0x0038 /* MAC interrupt flag register offset */
@ -75,7 +75,7 @@
#define GD32_ENET_MSC_TINTMSK_OFFSET 0x0110 /* MSC transmit interrupt mask register offset */
#define GD32_ENET_MSC_SCCNT_OFFSET 0x014C /* MSC transmitted good frames after a single collision counter register offset */
#define GD32_ENET_MSC_MSCCNT_OFFSET 0x0150 /* MSC transmitted good frames after more than a signle collision counter register offset */
#define GD32_ENET_MSC_MSCCNT_OFFSET 0x0150 /* MSC transmitted good frames after more than a single collision counter register offset */
#define GD32_ENET_MSC_TGFCNT_OFFSET 0x0168 /* MSC transmitted good frames counter register offset */
@ -438,7 +438,7 @@
#define ENET_MAC_FCTH_RFA_SHIFT (0) /* Bits 0-2 threshold of active flow control */
#define ENET_MAC_FCTH_RFA_MASK (7 << ENET_MAC_FCTH_RFA_SHIFT)
#define ENET_MAC_FCTH_RFD_SHIFT (4) /* Bits 4-6 threshold of deactive flow control */
#define ENET_MAC_FCTH_RFD_SHIFT (4) /* Bits 4-6 threshold of deactivate flow control */
#define ENET_MAC_FCTH_RFD_MASK (7 << ENET_MAC_FCTH_RFD_SHIFT)
/* MSC Registers */
@ -647,7 +647,7 @@
#define ENET_RX_STATE_WAITING (3 << ENET_DMA_STAT_RP_SHIFT) /* 011: waiting for receive packet */
#define ENET_RX_STATE_SUSPENDED (4 << ENET_DMA_STAT_RP_SHIFT) /* 100: Rx descriptor unavailable */
#define ENET_RX_STATE_CLOSING (5 << ENET_DMA_STAT_RP_SHIFT) /* 101: closing receive descriptor */
#define ENET_RX_STATE_QUEUING (6 << ENET_DMA_STAT_RP_SHIFT) /* 111: transferring the receive packet data from recevie buffer to host memory */
#define ENET_RX_STATE_QUEUING (6 << ENET_DMA_STAT_RP_SHIFT) /* 111: transferring the receive packet data from receive buffer to host memory */
#define ENET_DMA_STAT_TP_SHIFT (20) /* Bits 20-22: transmit process state */
#define ENET_DMA_STAT_TP_MASK (7 << ENET_DMA_STAT_TP_SHIFT)

24
arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h
View file

@ -40,18 +40,18 @@
/* Register Offsets *********************************************************/
#define GD32_GPIO_CTL_OFFSET 0x0000 /* GPIO port control register offfset */
#define GD32_GPIO_OMODE_OFFSET 0x0004 /* GPIO port output mode register offfset */
#define GD32_GGPIO_OSPD_OFFSET 0x0008 /* GPIO port output speed register offfset */
#define GD32_GPIO_PUD_OFFSET 0x000c /* GPIO port pull-up/pull-down register offfset */
#define GD32_GPIO_ISTAT_OFFSET 0x0010 /* GPIO port input status register offfset */
#define GD32_GPIO_OCTL_OFFSET 0x0014 /* GPIO port output control register offfset */
#define GD32_GPIO_BOP_OFFSET 0x0018 /* GPIO port bit operation register offfset */
#define GD32_GPIO_LOCK_OFFSET 0x001c /* GPIO port configuration lock register offfset */
#define GD32_GPIO_AFSEL0_OFFSET 0x0020 /* GPIO alternate function selected register 0 offfset */
#define GD32_GPIO_AFSEL1_OFFSET 0x0024 /* GPIO alternate function selected register 1 offfset */
#define GD32_GPIO_BC_OFFSET 0x0028 /* GPIO bit clear register offfset */
#define GD32_GPIO_TG_OFFSET 0x002c /* GPIO port bit toggle register offfset */
#define GD32_GPIO_CTL_OFFSET 0x0000 /* GPIO port control register offset */
#define GD32_GPIO_OMODE_OFFSET 0x0004 /* GPIO port output mode register offset */
#define GD32_GGPIO_OSPD_OFFSET 0x0008 /* GPIO port output speed register offset */
#define GD32_GPIO_PUD_OFFSET 0x000c /* GPIO port pull-up/pull-down register offset */
#define GD32_GPIO_ISTAT_OFFSET 0x0010 /* GPIO port input status register offset */
#define GD32_GPIO_OCTL_OFFSET 0x0014 /* GPIO port output control register offset */
#define GD32_GPIO_BOP_OFFSET 0x0018 /* GPIO port bit operation register offset */
#define GD32_GPIO_LOCK_OFFSET 0x001c /* GPIO port configuration lock register offset */
#define GD32_GPIO_AFSEL0_OFFSET 0x0020 /* GPIO alternate function selected register 0 offset */
#define GD32_GPIO_AFSEL1_OFFSET 0x0024 /* GPIO alternate function selected register 1 offset */
#define GD32_GPIO_BC_OFFSET 0x0028 /* GPIO bit clear register offset */
#define GD32_GPIO_TG_OFFSET 0x002c /* GPIO port bit toggle register offset */
/* Register Addresses *******************************************************/

2
arch/arm/src/goldfish/chip.h
View file

@ -66,7 +66,7 @@
* Name: cpuindex
*
* Description:
* Return an index idenifying the current CPU.
* Return an index identifying the current CPU.
*
****************************************************************************/

4
arch/arm/src/imx1/imx_uart.h
View file

@ -136,8 +136,8 @@
#define UART2_UCR3_INVT (1 << 1) /* Bit 1: Inverted Infrared Transmission */
#define UART2_UCR3_REF30 (1 << 2) /* Bit 2: Reference frequency 30 mhz */
#define UART2_UCR3_REF25 (1 << 3) /* Bit 3: Reference frequency 25 mhz */
#define UART2_UCR3_AWAKEN (1 << 4) /* Bit 4: Asychronous WAKE Interrupt Enable */
#define UART2_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asychronous IR WAKE Interrupt Enable */
#define UART2_UCR3_AWAKEN (1 << 4) /* Bit 4: Asynchronous WAKE Interrupt Enable */
#define UART2_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asynchronous IR WAKE Interrupt Enable */
#define UART2_UCR3_RXDSEN (1 << 6) /* Bit 6: Receive Status Interrupt Enable */
#define UART2_UCR3_RI (1 << 7) /* Bit 7: Ring Indicator */
#define UART2_UCR3_Reserved2 (1 << 8) /* Bit 8: Reserved */

2
arch/arm/src/imx6/chip.h
View file

@ -63,7 +63,7 @@
* Name: cpuindex
*
* Description:
* Return an index idenifying the current CPU.
* Return an index identifying the current CPU.
*
****************************************************************************/

4
arch/arm/src/imx6/hardware/imx_enet.h
View file

@ -309,7 +309,7 @@
#define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */
/* Receive Interrupt Coalescing Register */
@ -319,7 +319,7 @@
#define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Enable/disable Interrupt Coalescing */
#endif /* if 0 */

2
arch/arm/src/imx6/imx_enet.c
View file

@ -2510,7 +2510,7 @@ int imx_netinitialize(int intf)
memset(priv, 0, sizeof(struct imx_driver_s));
priv->base = IMX_ENET_VBASE; /* Assigne base address */
priv->base = IMX_ENET_VBASE; /* Assign base address */
priv->dev.d_ifup = imx_ifup; /* I/F up (new IP address) callback */
priv->dev.d_ifdown = imx_ifdown; /* I/F down callback */

4
arch/arm/src/imx6/imx_iomuxc.c
View file

@ -423,12 +423,12 @@ int imx_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
value = (ioset & IOMUX_DRIVE_MASK) >> IOMUX_DRIVE_SHIFT;
regval |= PADCTL_DSE(value);
/* Select spped */
/* Select speed */
value = (ioset & IOMUX_SPEED_MASK) >> IOMUX_SPEED_SHIFT;
regval |= PADCTL_SPEED(value);
/* Select CMOS output or Open Drain outpout */
/* Select CMOS output or Open Drain output */
if ((ioset & IOMUX_OPENDRAIN) != 0)
{

4
arch/arm/src/imx6/imx_lowputc.c
View file

@ -579,8 +579,8 @@ void imx_lowputc(int ch)
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) &
UART_USR2_TXFE) == 0);
/* If the character to output is a newline, then pre-pend a carriage
* return
/* If the character to output is a newline, then prepend a carriage
* return.
*/
/* Send the character by writing it into the UART_TXD register. */

2
arch/arm/src/imx9/Kconfig
View file

@ -755,7 +755,7 @@ config IMX9_LPI2C_DMA_MAXMSG
default 8
depends on IMX9_LPI2C_DMA
---help---
This option set the mumber of mesg that can be in a transfer.
This option set the number of mesg that can be in a transfer.
It is used to allocate space for the 16 bit LPI2C commands
that will be DMA-ed to the LPI2C device.

2
arch/arm/src/imx9/hardware/imx9_lpit.h
View file

@ -38,7 +38,7 @@
#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */
#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */
#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */
#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */
#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Module Interrupt Enable */
#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */
#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */
#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */

2
arch/arm/src/imx9/imx9_clockconfig.c
View file

@ -83,7 +83,7 @@ void imx9_clockconfig(void)
IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG, 0);
#endif
/* Cortex-M33 with SM does PLL initalization */
/* Cortex-M33 with SM does PLL initialization */
}
#ifdef CONFIG_IMX9_CLK_OVER_SCMI

2
arch/arm/src/imx9/imx9_edma.h
View file

@ -83,7 +83,7 @@
* i mxrt_dmach_stop(handle);
*
* 7. The callback will be received when the DMA completes (or an error
* occurs). After that, you may free the DMA channel, or re-use it on
* occurs). After that, you may free the DMA channel, or reuse it on
* subsequent DMAs.
*
* imx9_dmach_free(handle);

8
arch/arm/src/imx9/imx9_flexcan.c
View file

@ -747,9 +747,9 @@ static int imx9_transmit(struct imx9_driver_s *priv)
mb->cs = cs; /* Go. */
/* Errata ER005829 step 8: Write twice into the first TX MB
* Errata mentions writng 0x8 value, but this one couses
* Errata mentions writing 0x8 value, but this one causes
* the ESR2_LPTM register to choose the reserved MB for
* transmiting the package, hence we write 0x3
* transmitting the package, hence we write 0x3.
*/
struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT);
@ -1777,9 +1777,9 @@ static int imx9_initialize(struct imx9_driver_s *priv)
}
/* Errata ER005829 step 7: Reserve first TX MB
* Errata mentions writng 0x8 value, but this one couses
* Errata mentions writing 0x8 value, but this one causes
* the ESR2_LPTM register to choose the reserved MB for
* transmiting the package, hence we write 0x3
* transmitting the package, hence we write 0x3.
*/
struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT);

2
arch/arm/src/imx9/imx9_lowputc.c
View file

@ -555,7 +555,7 @@ void arm_lowputc(char ch)
}
/* If the character to output is a newline,
* then pre-pend a carriage return
* then prepend a carriage return.
*/
if (ch == '\n')

4
arch/arm/src/imx9/imx9_lpi2c.c
View file

@ -1974,7 +1974,7 @@ static int imx9_lpi2c_dma_transfer(struct imx9_lpi2c_priv_s *priv)
LPI2C_MSR_ALF |
LPI2C_MSR_FEF);
/* Enable the Iterrupts */
/* Enable the Interrupts */
imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET,
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
@ -2291,7 +2291,7 @@ static int imx9_lpi2c_reset(struct i2c_master_s *dev)
out:
/* Release the port for re-use by other clients */
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;

2
arch/arm/src/imx9/imx9_lpspi.c
View file

@ -2114,7 +2114,7 @@ struct spi_dev_s *imx9_lpspibus_initialize(int bus)
* Name: imx9_lpspibus_uninitialize
*
* Description:
* Unitialize the selected SPI bus
* Uninitialize the selected SPI bus
*
* Input Parameters:
* dev - Device-specific state data

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