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arch/armv7-r: revise headers to support QEMU armv7-r

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This revise armv7-r/ header files needed to support QEMU cortex-r5
virtual process for armv7-r family.

Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This commit is contained in:
Yanfeng Liu 2025-01-17 15:08:58 +08:00 • committed by Alan C. Assis
parent 2779989add
commit 3f85df583c
3 changed files with 10 additions and 0 deletions
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2
arch/arm/include/armv7-r/cp15.h
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@ -161,6 +161,8 @@
#define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */
#define CP15_CNTP_CVAL(lo,hi) _CP15_64(2, lo, hi, c14) /* Physical Timer CompareValue register */
#define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */
#define CP15_SET(reg, value) \

4
arch/arm/src/armv7-r/mpcore.h
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@ -47,14 +47,18 @@
/* Peripheral Base Offsets **************************************************/
#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */
#ifndef MPCORE_ICC_OFFSET
#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt controller interface */
#endif
#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */
/* 0x0300-0x05ff Reserved */
#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */
/* 0x0700-0x07ff Reserved */
#ifndef MPCORE_ICD_OFFSET
#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */
#endif
/* Peripheral Base Addresses ************************************************/

4
arch/arm/src/armv7-r/sctlr.h
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@ -42,6 +42,10 @@
* Pre-processor Definitions
****************************************************************************/
/* Vector Base Address Register (VBAR) */
#define VBAR_MASK (0xffffffe0)
/* CP15 c0 Registers ********************************************************/
/* Main ID Register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=0