risc-v/espressif/uart: Update common source code functions
Updates the common source code for the UART peripheral used by Espressif's RISC-Vs SoCs. This enables newer SoCs to be supported in the future while maintaining backwards compatibility. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit is contained in:
Tiago Medicci Serrano
Xiang Xiao
parent
78b7cc729b
commit
c8b7950bd4
6 changed files with 169 additions and 101 deletions
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@ -47,8 +47,11 @@
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#include "esp_irq.h"
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#include "esp_lowputc.h"
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#include "esp_usbserial.h"
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#include "esp_private/critical_section.h"
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#include "esp_private/uart_share_hw_ctrl.h"
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#include "hal/uart_hal.h"
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#include "soc/uart_periph.h"
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#include "periph_ctrl.h"
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#include "soc/gpio_sig_map.h"
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#ifdef CONFIG_ESPRESSIF_LP_UART
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@ -71,6 +74,18 @@
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# define ESP_LP_UART0_ID UART_NUM_MAX
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#endif /* CONFIG_ESPRESSIF_LP_UART */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define UART_CONTEXT_INIT_DEF(uart_num) \
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{ \
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.port_id = uart_num, \
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.hal.dev = UART_LL_GET_HW(uart_num), \
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INIT_CRIT_SECTION_LOCK_IN_STRUCT(spinlock) \
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.hw_enabled = false, \
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}
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -90,22 +105,17 @@ static uart_hal_context_t g_uart0_hal =
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struct esp_uart_s g_uart0_config =
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{
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.source = UART0_INTR_SOURCE,
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.cpuint = -ENOMEM,
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.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
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.id = 0,
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.irq = ESP_IRQ_UART0,
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.baud = CONFIG_UART0_BAUD,
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.stop_b2 = CONFIG_UART0_2STOP,
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.bits = CONFIG_UART0_BITS,
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.parity = CONFIG_UART0_PARITY,
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.txpin = CONFIG_ESPRESSIF_UART0_TXPIN,
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.txsig = U0TXD_OUT_IDX,
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.rxpin = CONFIG_ESPRESSIF_UART0_RXPIN,
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.rxsig = U0RXD_IN_IDX,
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rtspin = CONFIG_ESPRESSIF_UART0_RTSPIN,
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.rtssig = U0RTS_OUT_IDX,
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#ifdef CONFIG_UART0_IFLOWCONTROL
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.iflow = true, /* input flow control (RTS) enabled */
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#else
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@ -114,7 +124,6 @@ struct esp_uart_s g_uart0_config =
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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.ctspin = CONFIG_ESPRESSIF_UART0_CTSPIN,
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.ctssig = U0CTS_IN_IDX,
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#ifdef CONFIG_UART0_OFLOWCONTROL
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.oflow = true, /* output flow control (CTS) enabled */
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#else
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@ -145,22 +154,17 @@ static uart_hal_context_t g_uart1_hal =
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struct esp_uart_s g_uart1_config =
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{
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.source = UART1_INTR_SOURCE,
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.cpuint = -ENOMEM,
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.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
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.id = 1,
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.irq = ESP_IRQ_UART1,
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.baud = CONFIG_UART1_BAUD,
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.stop_b2 = CONFIG_UART1_2STOP,
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.bits = CONFIG_UART1_BITS,
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.parity = CONFIG_UART1_PARITY,
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.txpin = CONFIG_ESPRESSIF_UART1_TXPIN,
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.txsig = U1TXD_OUT_IDX,
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.rxpin = CONFIG_ESPRESSIF_UART1_RXPIN,
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.rxsig = U1RXD_IN_IDX,
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rtspin = CONFIG_ESPRESSIF_UART1_RTSPIN,
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.rtssig = U1RTS_OUT_IDX,
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#ifdef CONFIG_UART1_IFLOWCONTROL
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.iflow = true, /* input flow control (RTS) enabled */
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#else
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@ -169,7 +173,6 @@ struct esp_uart_s g_uart1_config =
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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.ctspin = CONFIG_ESPRESSIF_UART1_CTSPIN,
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.ctssig = U1CTS_IN_IDX,
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#ifdef CONFIG_UART1_OFLOWCONTROL
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.oflow = true, /* output flow control (CTS) enabled */
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#else
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@ -200,22 +203,17 @@ static uart_hal_context_t g_lp_uart0_hal =
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struct esp_uart_s g_lp_uart0_config =
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{
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.source = LP_UART_INTR_SOURCE,
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.cpuint = -ENOMEM,
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.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
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.id = ESP_LP_UART0_ID,
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.irq = ESP_IRQ_LP_UART,
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.baud = CONFIG_LPUART0_BAUD,
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.stop_b2 = CONFIG_LPUART0_2STOP,
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.bits = CONFIG_LPUART0_BITS,
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.parity = CONFIG_LPUART0_PARITY,
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.txpin = LP_UART_DEFAULT_TX_GPIO_NUM,
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.txsig = LP_U0TXD_MUX_FUNC,
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.rxpin = LP_UART_DEFAULT_RX_GPIO_NUM,
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.rxsig = LP_U0RXD_MUX_FUNC,
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rtspin = LP_UART_DEFAULT_RTS_GPIO_NUM,
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.rtssig = LP_U0RTS_MUX_FUNC,
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#ifdef CONFIG_LPUART0_IFLOWCONTROL
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.iflow = true, /* input flow control (RTS) enabled */
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#else
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@ -224,7 +222,6 @@ struct esp_uart_s g_lp_uart0_config =
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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.ctspin = LP_UART_DEFAULT_CTS_GPIO_NUM,
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.ctssig = LP_U0CTS_MUX_FUNC,
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#ifdef CONFIG_LPUART0_OFLOWCONTROL
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.oflow = true, /* output flow control (CTS) enabled */
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#else
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@ -240,6 +237,28 @@ struct esp_uart_s g_lp_uart0_config =
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#endif /* HAVE_UART_DEVICE */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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uart_context_t g_uart_context[UART_NUM_MAX] =
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{
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UART_CONTEXT_INIT_DEF(UART_NUM_0),
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UART_CONTEXT_INIT_DEF(UART_NUM_1),
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#if SOC_UART_HP_NUM > 2
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UART_CONTEXT_INIT_DEF(UART_NUM_2),
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#endif
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#if SOC_UART_HP_NUM > 3
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UART_CONTEXT_INIT_DEF(UART_NUM_3),
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#endif
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#if SOC_UART_HP_NUM > 4
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UART_CONTEXT_INIT_DEF(UART_NUM_4),
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#endif
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#if (SOC_UART_LP_NUM >= 1)
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UART_CONTEXT_INIT_DEF(LP_UART_NUM_0),
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -295,6 +314,51 @@ static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
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* Public Functions
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****************************************************************************/
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bool esp_lowputc_uart_module_enable(const struct esp_uart_s *priv)
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{
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int uart_num = priv->id;
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bool newly_enabled = false;
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mutex_t lock;
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nxmutex_init(&lock);
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g_uart_context[uart_num].mutex = (_lock_t)&lock;
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_lock_acquire(&(g_uart_context[uart_num].mutex));
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if (g_uart_context[uart_num].hw_enabled != true)
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{
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if (uart_num < SOC_UART_HP_NUM)
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{
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HP_UART_BUS_CLK_ATOMIC()
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{
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uart_ll_enable_bus_clock(uart_num, true);
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}
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if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM)
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{
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HP_UART_BUS_CLK_ATOMIC()
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{
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uart_ll_reset_register(uart_num);
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}
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HP_UART_SRC_CLK_ATOMIC()
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{
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uart_ll_sclk_enable(g_uart_context[uart_num].hal.dev);
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}
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}
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}
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g_uart_context[uart_num].hw_enabled = true;
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newly_enabled = true;
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}
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_lock_release(&(g_uart_context[uart_num].mutex));
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nxmutex_destroy(&lock);
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g_uart_context[uart_num].mutex = NULL;
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return newly_enabled;
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}
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/****************************************************************************
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* Name: esp_lowputc_send_byte
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*
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@ -313,25 +377,6 @@ void esp_lowputc_send_byte(const struct esp_uart_s *priv, char byte)
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uart_hal_write_txfifo(priv->hal, (const uint8_t *)&byte, 1, &write_size);
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}
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/****************************************************************************
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* Name: esp_lowputc_enable_sysclk
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*
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* Description:
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* Enable clock for the UART using the System register.
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*
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* Parameters:
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* priv - Pointer to the private driver struct.
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*
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****************************************************************************/
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void esp_lowputc_enable_sysclk(const struct esp_uart_s *priv)
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{
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if (priv->id < ESP_LP_UART0_ID)
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{
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periph_module_enable(PERIPH_UART0_MODULE + priv->id);
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}
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}
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/****************************************************************************
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* Name: esp_lowputc_disable_all_uart_int
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*
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@ -410,24 +455,32 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
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if (priv->id < ESP_LP_UART0_ID)
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{
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esp_configgpio(priv->rxpin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
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esp_gpio_matrix_in(priv->rxpin,
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UART_PERIPH_SIGNAL(priv->id, SOC_UART_RX_PIN_IDX),
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0);
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esp_configgpio(priv->txpin, OUTPUT);
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esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
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esp_gpio_matrix_out(priv->txpin,
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UART_PERIPH_SIGNAL(priv->id, SOC_UART_TX_PIN_IDX),
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0, 0);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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uint32_t sig = UART_PERIPH_SIGNAL(priv->id, SOC_UART_RTS_PIN_IDX);
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esp_configgpio(priv->rtspin, OUTPUT);
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esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
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esp_gpio_matrix_out(priv->rtspin, sig, 0, 0);
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}
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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if (priv->oflow)
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{
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uint32_t sig = UART_PERIPH_SIGNAL(priv->id, SOC_UART_CTS_PIN_IDX);
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esp_configgpio(priv->ctspin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
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esp_gpio_matrix_in(priv->ctspin, sig, 0);
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}
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#endif
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@ -546,12 +599,12 @@ void esp_lowsetup(void)
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#ifndef CONFIG_SUPPRESS_UART_CONFIG
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#ifdef CONFIG_ESPRESSIF_UART0
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esp_lowputc_enable_sysclk(&g_uart0_config);
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esp_lowputc_uart_module_enable(&g_uart0_config);
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esp_lowputc_config_pins(&g_uart0_config);
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#endif
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#ifdef CONFIG_ESPRESSIF_UART1
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esp_lowputc_enable_sysclk(&g_uart1_config);
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esp_lowputc_uart_module_enable(&g_uart1_config);
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esp_lowputc_config_pins(&g_uart1_config);
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#endif
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@ -35,6 +35,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <sys/types.h>
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#include <sys/lock.h>
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#include <unistd.h>
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#include <nuttx/arch.h>
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@ -44,6 +45,7 @@
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#include "chip.h"
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#include "esp_irq.h"
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#include "hal/uart_hal.h"
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#include "esp_private/critical_section.h"
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/****************************************************************************
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* Public Types
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@ -53,27 +55,21 @@
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struct esp_uart_s
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{
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int source; /* UART interrupt source */
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int cpuint; /* CPU interrupt assigned to this UART */
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irq_priority_t int_pri; /* UART Interrupt Priority */
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int id; /* UART ID */
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int irq; /* IRQ associated with this UART */
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uint32_t baud; /* Configured baud rate */
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bool stop_b2; /* Flag for using 2 stop bits */
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uint8_t bits; /* Data length (5 to 8 bits) */
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uint8_t parity; /* 0=no parity, 1=odd, 2=even */
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uint8_t txpin; /* TX pin */
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uint8_t txsig; /* TX signal */
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uint8_t rxpin; /* RX pin */
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uint8_t rxsig; /* RX signal */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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uint8_t rtspin; /* RTS pin number */
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uint8_t rtssig; /* RTS signal */
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bool iflow; /* Input flow control (RTS) enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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uint8_t ctspin; /* CTS pin number */
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uint8_t ctssig; /* CTS signal */
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bool oflow; /* Output flow control (CTS) enabled */
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#endif
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#ifdef HAVE_RS485
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@ -85,6 +81,15 @@ struct esp_uart_s
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spinlock_t lock; /* Spinlock */
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};
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typedef struct
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{
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_lock_t mutex; /* Protect uart_module_enable, uart_module_disable, retention, etc. */
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uart_port_t port_id;
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uart_hal_context_t hal; /* UART hal context */
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DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(spinlock)
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bool hw_enabled;
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} uart_context_t;
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extern struct esp_uart_s g_uart0_config;
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extern struct esp_uart_s g_uart1_config;
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extern struct esp_uart_s g_lp_uart0_config;
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@ -108,19 +113,6 @@ extern struct esp_uart_s g_lp_uart0_config;
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void esp_lowputc_send_byte(const struct esp_uart_s *priv,
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char byte);
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/****************************************************************************
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* Name: esp_lowputc_enable_sysclk
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*
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* Description:
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* Enable clock for the UART using the System register.
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*
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* Parameters:
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* priv - Pointer to the private driver struct.
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*
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****************************************************************************/
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void esp_lowputc_enable_sysclk(const struct esp_uart_s *priv);
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/****************************************************************************
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* Name: esp_lowputc_disable_all_uart_int
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*
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@ -193,4 +185,6 @@ void esp_lowputc_restore_pins(const struct esp_uart_s *priv);
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void esp_lowsetup(void);
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bool esp_lowputc_uart_module_enable(const struct esp_uart_s *priv);
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#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LOWPUTC_H */
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@ -55,7 +55,10 @@
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#endif
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#include "esp_clk_tree.h"
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#include "esp_private/uart_share_hw_ctrl.h"
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#include "esp_private/esp_clk_tree_common.h"
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#include "hal/uart_hal.h"
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#include "soc/uart_periph.h"
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#include "soc/clk_tree_defs.h"
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#include "periph_ctrl.h"
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@ -306,6 +309,12 @@ static uart_dev_t g_lp_uart0_dev =
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#endif /* CONFIG_ESPRESSIF_UART */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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extern uart_context_t g_uart_context[UART_NUM_MAX];
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -453,15 +462,21 @@ static void set_stop_length(const struct esp_uart_s *priv)
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static int esp_setup(uart_dev_t *dev)
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{
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struct esp_uart_s *priv = dev->priv;
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soc_module_clk_t src_clk;
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uint32_t sclk_freq;
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bool success = false;
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/* Enable the UART Clock */
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esp_lowputc_enable_sysclk(priv);
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esp_lowputc_uart_module_enable(priv);
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esp_clk_tree_src_get_freq_hz((soc_module_clk_t)priv->clk_src,
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ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
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&sclk_freq);
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uart_hal_get_sclk(priv->hal, &src_clk);
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esp_clk_tree_src_get_freq_hz(src_clk,
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ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
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&sclk_freq);
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esp_os_enter_critical(&(g_uart_context[priv->id].spinlock));
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/* Initialize UART module */
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#ifdef CONFIG_ESPRESSIF_LP_UART
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@ -479,25 +494,18 @@ static int esp_setup(uart_dev_t *dev)
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#endif
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uart_hal_init(priv->hal, priv->id);
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uart_hal_set_mode(priv->hal, UART_MODE_UART);
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if (priv->id < ESP_LP_UART0_ID)
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{
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uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
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uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
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}
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#ifdef CONFIG_ESPRESSIF_LP_UART
|
||||
else
|
||||
{
|
||||
/* Override protocol parameters from the configuration */
|
||||
|
||||
if (!lp_uart_ll_set_baudrate(priv->hal->dev, priv->baud, sclk_freq))
|
||||
if (priv->id < SOC_UART_HP_NUM)
|
||||
{
|
||||
esp_clk_tree_enable_src(UART_SCLK_XTAL, true);
|
||||
HP_UART_SRC_CLK_ATOMIC()
|
||||
{
|
||||
/* Unachievable baud rate */
|
||||
|
||||
return ESP_FAIL;
|
||||
uart_hal_set_sclk(priv->hal, UART_SCLK_XTAL);
|
||||
success = uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
uart_hal_set_parity(priv->hal, priv->parity);
|
||||
set_data_length(priv);
|
||||
|
|
@ -559,6 +567,13 @@ static int esp_setup(uart_dev_t *dev)
|
|||
else
|
||||
#endif
|
||||
|
||||
esp_os_exit_critical(&(g_uart_context[priv->id].spinlock));
|
||||
|
||||
if (success == false)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* Clear FIFOs */
|
||||
|
||||
uart_hal_rxfifo_rst(priv->hal);
|
||||
|
|
@ -619,24 +634,27 @@ static int esp_attach(uart_dev_t *dev)
|
|||
{
|
||||
struct esp_uart_s *priv = dev->priv;
|
||||
int ret;
|
||||
int source;
|
||||
|
||||
DEBUGASSERT(priv->cpuint == -ENOMEM);
|
||||
|
||||
/* Set up to receive peripheral interrupts */
|
||||
|
||||
priv->cpuint = esp_setup_irq(priv->source, priv->int_pri,
|
||||
source = uart_periph_signal[priv->id].irq;
|
||||
|
||||
priv->cpuint = esp_setup_irq(source, priv->int_pri,
|
||||
ESP_IRQ_TRIGGER_LEVEL);
|
||||
|
||||
/* Attach and enable the IRQ */
|
||||
|
||||
ret = irq_attach(priv->irq, uart_handler, dev);
|
||||
ret = irq_attach(ESP_SOURCE2IRQ(source), uart_handler, dev);
|
||||
if (ret == OK)
|
||||
{
|
||||
up_enable_irq(priv->irq);
|
||||
up_enable_irq(ESP_SOURCE2IRQ(source));
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(priv->irq);
|
||||
up_disable_irq(ESP_SOURCE2IRQ(source));
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -661,17 +679,20 @@ static int esp_attach(uart_dev_t *dev)
|
|||
static void esp_detach(uart_dev_t *dev)
|
||||
{
|
||||
struct esp_uart_s *priv = dev->priv;
|
||||
int source;
|
||||
|
||||
DEBUGASSERT(priv->cpuint != -ENOMEM);
|
||||
|
||||
source = uart_periph_signal[priv->id].irq;
|
||||
|
||||
/* Disable and detach the CPU interrupt */
|
||||
|
||||
up_disable_irq(priv->irq);
|
||||
irq_detach(priv->irq);
|
||||
up_disable_irq(ESP_SOURCE2IRQ(source));
|
||||
irq_detach(ESP_SOURCE2IRQ(source));
|
||||
|
||||
/* Disassociate the peripheral interrupt from the CPU interrupt */
|
||||
|
||||
esp_teardown_irq(priv->source, priv->cpuint);
|
||||
esp_teardown_irq(source, priv->cpuint);
|
||||
priv->cpuint = -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -106,8 +106,8 @@ static char g_txbuffer[ESP_USBCDC_BUFFERSIZE];
|
|||
|
||||
static struct esp_priv_s g_usbserial_priv =
|
||||
{
|
||||
.source = USB_SERIAL_JTAG_INTR_SOURCE,
|
||||
.irq = ESP_IRQ_USB_SERIAL_JTAG,
|
||||
.source = ETS_USB_SERIAL_JTAG_INTR_SOURCE,
|
||||
.irq = ESP_SOURCE2IRQ(ETS_USB_SERIAL_JTAG_INTR_SOURCE),
|
||||
.cpuint = -ENOMEM,
|
||||
};
|
||||
|
||||
|
|
@ -167,23 +167,23 @@ uart_dev_t g_uart_usbserial =
|
|||
static int esp_interrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
|
||||
uint32_t tx_mask = USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST;
|
||||
uint32_t rx_mask = USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST;
|
||||
uint32_t int_status = usb_serial_jtag_ll_get_intsts_mask();
|
||||
|
||||
/* Send buffer has room and can accept new data. */
|
||||
|
||||
if ((int_status & tx_mask) != 0)
|
||||
if ((int_status & USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY) != 0)
|
||||
{
|
||||
usb_serial_jtag_ll_clr_intsts_mask(tx_mask);
|
||||
usb_serial_jtag_ll_clr_intsts_mask(
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
|
||||
uart_xmitchars(dev);
|
||||
}
|
||||
|
||||
/* Data from the host are available to read. */
|
||||
|
||||
if ((int_status & rx_mask) != 0)
|
||||
if ((int_status & USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT) != 0)
|
||||
{
|
||||
usb_serial_jtag_ll_clr_intsts_mask(rx_mask);
|
||||
usb_serial_jtag_ll_clr_intsts_mask(
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
|
||||
uart_recvchars(dev);
|
||||
}
|
||||
|
||||
|
|
@ -230,12 +230,12 @@ static void esp_txint(struct uart_dev_s *dev, bool enable)
|
|||
if (enable)
|
||||
{
|
||||
usb_serial_jtag_ll_ena_intr_mask(
|
||||
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA);
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb_serial_jtag_ll_disable_intr_mask(
|
||||
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA);
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -252,12 +252,12 @@ static void esp_rxint(struct uart_dev_s *dev, bool enable)
|
|||
if (enable)
|
||||
{
|
||||
usb_serial_jtag_ll_ena_intr_mask(
|
||||
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA);
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
|
||||
}
|
||||
else
|
||||
{
|
||||
usb_serial_jtag_ll_disable_intr_mask(
|
||||
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA);
|
||||
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -197,6 +197,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
|
|||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
|
||||
|
||||
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
|
||||
|
|
@ -217,7 +218,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
|||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
|
||||
|
|
|
|||
|
|
@ -199,6 +199,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
|
|||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)uart_periph.c
|
||||
|
||||
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
|
||||
|
|
@ -219,7 +220,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
|||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue