TMS570: More clock configuration logic
This commit is contained in:
Gregory Nutt
parent
2bd1be6c96
commit
d7595446bf
2 changed files with 238 additions and 14 deletions
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@ -204,12 +204,13 @@
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#define SYS_CSDIS_CLKSR3OFF (1 << 3) /* Bit 3: Clock source 3 */
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#define SYS_CSDIS_CLKSR4OFF (1 << 4) /* Bit 4: Clock source 4 */
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#define SYS_CSDIS_CLKSR5OFF (1 << 5) /* Bit 5: Clock source 5 */
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#define SYS_CSDIS_CLKSROFFALL (0x3b)
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#define SYS_CLKSRC_OSC SYS_CSDIS_CLKSR0OFF /* Oscillator */
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#define SYS_CLKSRC_PLL SYS_CSDIS_CLKSR1OFF /* PLL */
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#define SYS_CLKSRC_EXTCLKIN SYS_CSDIS_CLKSR3OFF /* EXTCLKIN */
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#define SYS_CLKSRC_LFLPO SYS_CSDIS_CLKSR4OFF /* Low Frequency LPO (Low Power Oscillator) clock */
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#define SYS_CLKSRC_HFLPO SYS_CSDIS_CLKSR5OFF /* High Frequency LPO (Low Power Oscillator) clock */
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#define SYS_CSDIS_CLKSRC_OSC SYS_CSDIS_CLKSR0OFF /* Oscillator */
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#define SYS_CSDIS_CLKSRC_PLL SYS_CSDIS_CLKSR1OFF /* PLL */
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#define SYS_CSDIS_CLKSRC_EXTCLKIN SYS_CSDIS_CLKSR3OFF /* EXTCLKIN */
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#define SYS_CSDIS_CLKSRC_LFLPO SYS_CSDIS_CLKSR4OFF /* Low Frequency LPO (Low Power Oscillator) clock */
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#define SYS_CSDIS_CLKSRC_HFLPO SYS_CSDIS_CLKSR5OFF /* High Frequency LPO (Low Power Oscillator) clock */
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/* Clock Domain Disable Register, Clock Domain Disable Set Register, and Clock Domain
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* Disable Clear Register.
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@ -224,15 +225,144 @@
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#define SYS_CDDIS_VCLKEQEPOFF (1 << 9) /* Bit 9: VCLK_EQEP_OFF domain off */
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/* GCLK, HCLK, VCLK, and VCLK2 Source Register */
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#define SYS_GHVSRC_
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#define SYS_CLKSRC_OSC 0 /* Alias for oscillator clock Source */
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#define SYS_CLKSRC_PLL1 1 /* Alias for Pll1 clock Source */
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#define SYS_CLKSRC_EXTERNAL1 3 /* Alias for external clock Source */
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#define SYS_CLKSRC_LPOLOW 4 /* Alias for low power oscillator low clock Source */
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#define SYS_CLKSRC_LPOHIGH 5 /* Alias for low power oscillator high clock Source */
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#define SYS_CLKSRC_PLL2 6 /* Alias for Pll2 clock Source */
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#define SYS_CLKSRC_EXTERNAL2 7 /* Alias for external 2 clock Source */
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#define SYS_CLKSRC_VCLK 9 /* Alias for synchronous VCLK1 clock Source */
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#define SYS_GHVSRC_GHVSRC_SHIFT (0) /* Bits 0-3: GCLK, HCLK, VCLK, VCLK2 current source */
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#define SYS_GHVSRC_GHVSRC_MASK (15 << SYS_GHVSRC_GHVSRC_SHIFT)
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# define SYS_GHVSRC_GHVSRC_SRC(n) ((uint32_t)(n) << SYS_GHVSRC_GHVSRC_SHIFT)
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# define SYS_GHVSRC_GHVSRC_SRC0 (0 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source0 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC1 (1 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source1 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC2 (2 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source2 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC3 (3 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source3 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC4 (4 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source4 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC5 (5 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source5 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC6 (6 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source6 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC7 (7 << SYS_GHVSRC_GHVSRC_SHIFT) /* Clock source7 for GCLK, HCLK, VCLK, VCLK2 */
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# define SYS_GHVSRC_GHVSRC_SRC(n) ((uint32_t)(n) << SYS_GHVSRC_GHVSRC_SHIFT)
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# define SYS_GHVSRC_GHVSRC_OSC SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_OSC)
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# define SYS_GHVSRC_GHVSRC_PLL1 SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_PLL1)
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# define SYS_GHVSRC_GHVSRC_EXTERNAL1 SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_EXTERNAL1)
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# define SYS_GHVSRC_GHVSRC_LPOLOW SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_LPOLOW)
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# define SYS_GHVSRC_GHVSRC_LPOHIGH SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_LPOHIGH)
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# define SYS_GHVSRC_GHVSRC_PLL2 SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_PLL2)
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# define SYS_GHVSRC_GHVSRC_EXTERNAL2 SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_EXTERNAL2)
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# define SYS_GHVSRC_GHVSRC_VCLK SYS_GHVSRC_GHVSRC_SRC(SYS_CLKSRC_VCLK)
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#define SYS_GHVSRC_HVLPM_SHIFT (16) /* Bits 16-19: HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off */
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#define SYS_GHVSRC_HVLPM_MASK (15 << SYS_GHVSRC_HVLPM_SHIFT)
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# define SYS_GHVSRC_HVLPM_SRC0 (0 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source0 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC1 (1 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source1 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC2 (2 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source2 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC3 (3 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source3 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC4 (4 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source4 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC5 (5 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source5 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC6 (6 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source6 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM_SRC7 (7 << SYS_GHVSRC_HVLPM_SHIFT) /* Clock source7 for HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_HVLPM(n) ((uint32_t)(n) << SYS_GHVSRC_HVLPM_SHIFT)
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# define SYS_GHVSRC_HVLPM_OSC SYS_GHVSRC_HVLPM(SYS_CLKSRC_OSC)
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# define SYS_GHVSRC_HVLPM_PLL1 SYS_GHVSRC_HVLPM(SYS_CLKSRC_PLL1)
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# define SYS_GHVSRC_HVLPM_EXTERNAL1 SYS_GHVSRC_HVLPM(SYS_CLKSRC_EXTERNAL1)
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# define SYS_GHVSRC_HVLPM_LPOLOW SYS_GHVSRC_HVLPM(SYS_CLKSRC_LPOLOW)
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# define SYS_GHVSRC_HVLPM_LPOHIGH SYS_GHVSRC_HVLPM(SYS_CLKSRC_LPOHIGH)
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# define SYS_GHVSRC_HVLPM_PLL2 SYS_GHVSRC_HVLPM(SYS_CLKSRC_PLL2)
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# define SYS_GHVSRC_HVLPM_EXTERNAL2 SYS_GHVSRC_HVLPM(SYS_CLKSRC_EXTERNAL2)
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# define SYS_GHVSRC_HVLPM_VCLK SYS_GHVSRC_HVLPM(SYS_CLKSRC_VCLK)
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#define SYS_GHVSRC_GHVWAKE_SHIFT (24) /* Bits 24-17: GCLK, HCLK, VCLK, VCLK2 source on wakeup */
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#define SYS_GHVSRC_GHVWAKE_MASK (15 << SYS_GHVSRC_GHVWAKE_SHIFT)
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# define SYS_GHVSRC_GHVWAKE_SRC0 (0 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source0 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC1 (1 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source1 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC2 (2 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source2 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC3 (3 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source3 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC4 (4 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source4 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC5 (5 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source5 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC6 (6 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source6 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE_SRC7 (7 << SYS_GHVSRC_GHVWAKE_SHIFT) /* Clock source7 for GCLK, HCLK, VCLK, VCLK2 on wakeup */
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# define SYS_GHVSRC_GHVWAKE(n) ((uint32_t)(n) << SYS_GHVSRC_GHVWAKE_SHIFT)
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# define SYS_GHVSRC_GHVWAKE_OSC SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_OSC)
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# define SYS_GHVSRC_GHVWAKE_PLL1 SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_PLL1)
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# define SYS_GHVSRC_GHVWAKE_EXTERNAL1 SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_EXTERNAL1)
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# define SYS_GHVSRC_GHVWAKE_LPOLOW SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_LPOLOW)
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# define SYS_GHVSRC_GHVWAKE_LPOHIGH SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_LPOHIGH)
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# define SYS_GHVSRC_GHVWAKE_PLL2 SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_PLL2)
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# define SYS_GHVSRC_GHVWAKE_EXTERNAL2 SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_EXTERNAL2)
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# define SYS_GHVSRC_GHVWAKE_VCLK SYS_GHVSRC_GHVWAKE(SYS_CLKSRC_VCLK)
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/* Peripheral Asynchronous Clock Source Register */
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#define SYS_VCLKASRC_
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#define SYS_VCLKASRC_VCLKA1S_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock1 source */
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#define SYS_VCLKASRC_VCLKA1S_MASK (15 << SYS_VCLKASRC_VCLKA1S_SHIFT)
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# define SYS_VCLKASRC_VCLKA1S_SRC0 (0 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source0 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC1 (1 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source1 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC2 (2 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source2 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC3 (3 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source3 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC4 (4 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source4 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC5 (5 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source5 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC6 (6 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source6 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S_SRC7 (7 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source7 for RTICLK1 */
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# define SYS_VCLKASRC_VCLKA1S(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA1S_SHIFT)
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# define SYS_VCLKASRC_VCLKA1S_OSC SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_OSC)
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# define SYS_VCLKASRC_VCLKA1S_PLL1 SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_PLL1)
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# define SYS_VCLKASRC_VCLKA1S_EXTERNAL1 SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_EXTERNAL1)
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# define SYS_VCLKASRC_VCLKA1S_LPOLOW SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_LPOLOW)
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# define SYS_VCLKASRC_VCLKA1S_LPOHIGH SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_LPOHIGH)
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# define SYS_VCLKASRC_VCLKA1S_PLL2 SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_PLL2)
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# define SYS_VCLKASRC_VCLKA1S_EXTERNAL2 SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_EXTERNAL2)
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# define SYS_VCLKASRC_VCLKA1S_VCLK SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_VCLK)
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/* RTI Clock Source Register */
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#define SYS_RCLKSRC_
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#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */
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#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT)
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# define SYS_RCLKSRC_RTI1SRC_SRC0 (0 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source0 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC1 (1 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source1 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC2 (2 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source2 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC3 (3 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source3 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC4 (4 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source4 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC5 (5 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source5 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC6 (6 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source6 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC_SRC7 (7 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source7 for RTICLK1 */
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# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT)
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# define SYS_RCLKSRC_RTI1SRC_OSC SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_OSC)
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# define SYS_RCLKSRC_RTI1SRC_PLL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL1)
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# define SYS_RCLKSRC_RTI1SRC_EXTERNAL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL1)
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# define SYS_RCLKSRC_RTI1SRC_LPOLOW SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOLOW)
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# define SYS_RCLKSRC_RTI1SRC_LPOHIGH SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOHIGH)
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# define SYS_RCLKSRC_RTI1SRC_PLL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL2)
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# define SYS_RCLKSRC_RTI1SRC_EXTERNAL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL2)
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# define SYS_RCLKSRC_RTI1SRC_VCLK SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK)
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#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) /* Bits 8-9: RTI clock 1 divider */
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#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT)
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# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 1 */
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# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 2 */
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# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 4 */
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# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 8 */
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/* Clock Source Valid Status Register */
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#define SYS_CSVSTAT_
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/* Memory Self-Test Global Control Register */
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#define SYS_MSTGCR_
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#define SYS_MSTGCR_CLKSR0V (1 << 0) /* Bit 0: Clock source xx valid */
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#define SYS_MSTGCR_CLKSR1V (1 << 1) /* Bit 1: Clock source xx valid */
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#define SYS_MSTGCR_CLKSR3V (1 << 3) /* Bit 3: Clock source xx valid */
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#define SYS_MSTGCR_CLKSR4V (1 << 4) /* Bit 4: Clock source xx valid */
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#define SYS_MSTGCR_CLKSR5V (1 << 5) /* Bit 5: Clock source xx valid */
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#define SYS_MSTGCR_CLKSRVALL (0x3b)
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/* Memory Hardware Initialization Global Control Register */
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@ -408,6 +538,7 @@
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#define SYS_BMMCR1_
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/* CPU Reset Control Register */
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#define SYS_CPURSTCR_
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/* Clock Control Register */
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#define SYS_CLKCNTL_PENA (1 << 8) /* Bit 8: Peripheral enable bit */
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@ -145,7 +145,7 @@ static void tms570_pll_setup(void)
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* external clock remains disabled.
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*/
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regval = SYS_CLKSRC_EXTCLKIN;
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regval = SYS_CSDIS_CLKSRC_EXTCLKIN;
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putreg32(regval, TMS570_SYS_CSDIS);
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}
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@ -225,7 +225,9 @@ static void tms570_lpo_trim(void)
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lotrim = (getreg32(TMS570_TITCM_LPOTRIM) & TMS570_TITCM_LPOTRIM_MASK) <<
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TMS570_TITCM_LPOTRIM_SHIFT;
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/* Use if the LPO trim value TI OTP if programmed. Otherwise, use the default value */
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/* Use if the LPO trim value TI OTP if programmed. Otherwise, use a
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* default value.
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*/
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if (lotrim != 0xffff)
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{
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@ -241,6 +243,96 @@ static void tms570_lpo_trim(void)
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putreg32(regval, TMS570_SYS_LPOMONCTL);
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}
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/****************************************************************************
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* Name: tms570_clocksrc_configure
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*
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* Description:
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* Finalize PLL configuration, enable and configure clocks sources.
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*
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****************************************************************************/
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static void tms570_clocksrc_configure(void)
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{
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uint32_t regval;
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uint32_t csvstat;
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uint32_t csdis;
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/* Disable / Enable clock domains. Writing a '1' to the CDDIS register turns
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* the clock off.
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*
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* GCLK Bit 0 On
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* HCLK/VCLK_sys Bit 1 On
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* VCLK_periph Bit 2 On
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* VCLK2 Bit 3 On
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* VCLKA1 Bit 4 On
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* RTICLK1 Bit 6 On
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* TCLK_EQEP Bit 9 On
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*/
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putreg32(0, TMS570_SYS_CDDIS);
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/* Work Around for Errata SYS#46: Errata Description: Clock Source
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* Switching Not Qualified with Clock Source Enable And Clock Source Valid
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* Workaround: Always check the CSDIS register to make sure the clock source
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* is turned on and check the CSVSTAT register to make sure the clock source
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* is valid. Then write to GHVSRC to switch the clock.
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*/
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do
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{
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/* Get the set of valid clocks */
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csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_MSTGCR_CLKSRVALL;
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/* Get the (inverted) state of each clock. Inverted so that '1' means
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* ON not OFF.
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*/
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csdis = (getreg32(TMS570_SYS_CSDIS) ^ SYS_CSDIS_CLKSROFFALL) &
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SYS_CSDIS_CLKSROFFALL;
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}
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while ((csvstat & csdis) != csdis);
|
||||
|
||||
|
||||
/* Now the PLLs are locked and the PLL outputs can be sped up. The R-
|
||||
* divider was programmed to be 0xF. Now this divider is changed to
|
||||
* programmed value
|
||||
*/
|
||||
|
||||
regval = getreg32(TMS570_SYS_PLLCTL1);
|
||||
regval &= ~SYS_PLLCTL1_PLLDIV_MASK;
|
||||
regval |= SYS_PLLCTL1_PLLDIV(BOARD_PLL_R - 1);
|
||||
putreg32(regval, TMS570_SYS_PLLCTL1);
|
||||
|
||||
/* Map device clock domains to desired sources and configure top-level
|
||||
* dividers. All clock domains were working off the default clock sources
|
||||
* until this point.
|
||||
*
|
||||
* Setup GCLK, HCLK and VCLK clock source for normal operation, power down
|
||||
* mode and after wakeup
|
||||
*/
|
||||
|
||||
regval = SYS_GHVSRC_GHVSRC_PLL1 | SYS_GHVSRC_HVLPM_PLL1 |
|
||||
SYS_GHVSRC_GHVWAKE_PLL1;
|
||||
putreg32(regval, TMS570_SYS_GHVSRC);
|
||||
|
||||
/* Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
|
||||
|
||||
regval = getreg32(TMS570_SYS_CLKCNTL);
|
||||
regval &= ~(SYS_CLKCNTL_VCLKR2_MASK | SYS_CLKCNTL_VCLKR_MASK);
|
||||
regval |= SYS_CLKCNTL_VCLKR2_DIV1 | SYS_CLKCNTL_VCLKR_DIV1;
|
||||
putreg32(regval, TMS570_SYS_CLKCNTL);
|
||||
|
||||
/* Setup RTICLK1 and RTICLK2 clocks */
|
||||
|
||||
regval = SYS_RCLKSRC_RTI1SRC_VCLK | SYS_RCLKSRC_RTI1DIV_DIV2;
|
||||
putreg32(regval, TMS570_SYS_RCLKSRC);
|
||||
|
||||
/* Setup asynchronous peripheral clock sources for AVCLK1 */
|
||||
|
||||
putreg32(SYS_VCLKASRC_VCLKA1S_VCLK, TMS570_SYS_VCLKASRC);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -294,9 +386,10 @@ void tms570_clockconfig(void)
|
|||
|
||||
tms570_lpo_trim();
|
||||
|
||||
/* Wait for PLLs to start up and map clock domains to desired clock
|
||||
* sources.
|
||||
*/
|
||||
/* Finalize PLL configuration, enable and configure clocks sources. */
|
||||
|
||||
tms570_clocksrc_configure();
|
||||
|
||||
#warning Missing Logic
|
||||
|
||||
/* Set ECLK pins functional mode */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue