The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts. For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Previous code was failing to disable error interrupts which
due to standard CAN retransmissions might trigger continusouly
(for example, with a disconnected CAN interface) flooding the
system and preventing other operations to continue.
Fixes: https://github.com/apache/nuttx/issues/16668
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
Commit 83a119160 fixed SMP by removing call to uart_xmitchars from inside spinlock.
This only works for SMP, since uart_xmitchars has a lock only in SMP. In a single
core configuration the function can be called in parallel from the interrupt
handler and from the imx9_txint.
Fix this by filling the uart buffers already before enabling the
interrupt, this way it is not possible to get the function called in parallel
for the same device.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit adds the lowerhalf driver support for the I2C Slave.
While not currently ideal, it is compatible with the upperhalf i2c slave driver.
A workqueue can be used to delegate the isr work to the upperhalf driver.
But keep in mind wq introduces a lot of delay and in certain scenarios,
it is better to write your own better upperhalf driver.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
This product does not have MTE. MTE is only available for Arch or higher extensions of armv8-5+memory tags
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. Add hw_tags.c, which will call arm64_mte to implement tagging of memory blocks by operating registers
2. It has been able to run normally on the default NX memory allocator, excluding mempool and tlsf
3. On more complex configurations, memory tests such as memstress can run normally without system crashes
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Support hardware debugging of ARM architecture, and support smp mode.We can use "up_debugpoint_add" or "up_debugpoint_remove" to add breakpoints, and the hardware will jump into the interrupt after detecting it.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The ARM64 instruction ADD has a 12-bit limit (0 - 4095) for immediate values, but here we try to use a symbolic address (.Linitparms) as an immediate value, which does not comply with the ARM64 instruction set rules.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Added subclasses of STM32G0 (such as STM32G07X) to Kconfig for use in dmamux driver. Added definitions to stm32g0_dmamux.h. Added configuration of number of dma and dmamux channels.
Added missing dma mappings for stm32g0.
Remove reserved defines.
Formatting fixes.
Added DMA2 IRQ mappings for STM32G0B and STM32G0C. Changed STM32_DMAMUX_BASE to STM32_DMAMUX1_BASE to align with stm32_dma_v1mux.c and C0 defines.
Provide correct mapping for ADC1_DMA_CHAN. Add STM32F0L0G0_HAVE_ADC1_DMA to STM32G0.
Add support for continuous mode to the ADC. Also added support to set smp1 and smp2 in board.h, as well as smpsel.
Removed unnecessary selects of STM32F0L0G0_STM32G0. Changed board level files to properly define A0-A3 on nucleo-g0b1re.
Add new Kconfig changes.
Made combined configs for STM32G0. Ex. STM32G0BX for STM32G0B0 and STM32G0B1.
Fixed defines and references in Kconfig and stm32_dma_v1mux.c
Defined adc_sampletime_write and adc_sampletime_set. Changed adc_sample_time_s structure to be much simpler. Old way made no sense. You can only have 2 sample times, so defining one for each channel makes no sense. The new adc_sample_time_s contains smp1, smp2, and smpsel. Also define ADC_HAVE_SMPR_SMP2 for STM32C0.
Added adc_sampletime_write and adc_sampletime_set. Altered adc_sample_time_s structure to be more appropriate for g0 and c0. Only two sample times can be defined. Added rcc support for DMA2.
Added defconfig for nucleo-g0b1re:adc_dma config.
Restore correct Kconfig from my original branch
Removed redundant ifdefs. If we select for G0 and C0, we know they have SMP2. Fixed formatting.
Formatting feedback. Aligned columns in irq and dma headers.
When the vaddr parameter passed to map_region() is not aligned to the page directory,
it causes incorrect address mapping for later regions.
For example, in the sv32 case, `PGPOOL` started at `0x80a00000` with a size of `1024*4096B`,
leading to page table errors for the range `0x80c00000~0x80e00000`.
This patch fixes the issue by ensuring map_region() correctly handles unaligned vaddr cases.
Signed-off-by: wushenhui <wushenhui@xiaomi.com>
This commit fixes an issue when `CONFIG_DEBUG_SYSCALL_INFO=y`: the
`cmd` variable doesn't exist (instead, `regs[REG_A0]` represents
the syscall command directly. Also, it fixes the parameter for
`up_dump_register`, as `tcb` is a pointer here. By applying these
fixes, debugging syscall info is now possible again.
Previously, if an event was generated in hardware after taking spin
lock it was not correctly accounted for in current reading cycle.
Now, we check for events and compensate count accordingly.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Port fix from risc-v code. Providing original description:
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.
Fixed by enabling the associated interrupt events.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Original-fix-by: michal matias <mich4l.matias@gmail.com>
