For AVR, atomic functions generated by LOAD macro turn into load surrounded
by up_irq_save and up_irq_restore. The generated code was incorrect as can
be seen from disassembly of __atomic_load_4:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
out 0x3f, r18 ; restore the flag
movw r30, r24 ; copy parameter (address) to pointer register
ld r22, Z ; indirect load to return value registers
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
ret ; return
The interrupts are disabled to be immediately re-enabled, the load only takes
place after that.
Both up_irq_save and up_irq_restore are defined in inline assembly. Other
architectures (x86/486, Risc-V) mark this assembly with clobbers: memory.
Doing the same thing for AVR alleviates the problem:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
movw r30, r24 ; copy address
ld r22, Z ; load
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
out 0x3f, r18 ; restore interrupts enabled flag
ret ; return
Besides compiling the code and checking the assembly, this was tested
with a custom stress application on AVR128DA28.
Assembly of up_irq_enable is marked in the same way with regards to clobbers.
This patch also removes two functions that are not called from anywhere
(up_irq_disabled, putsreg)
Signed-off-by: Kerogit <kr.git@kerogit.eu>
The up_saveusercontext function leverages USER_SAVE macro,
which is ordinarily used as a first half of the context switch.
This macro is therefore unsuitable to be used standalone,
it pops return address from the stack and does not return.
This patch adds missing instructions to do what would otherwise
be done by the second half of the context switch.
Tested by compiling and verifying the disassembly - the function
no longer falls through to the next function in the program memory,
push/pop instructions are balanced and stack contents preserved
Signed-off-by: Kerogit <kr.git@kerogit.eu>
After a mailing list suggestion, the indirection that enabled
ARCH_TOOLCHAIN_GCC only when user requested it is removed.
The indirection was a safety measure for chips and boards with linker
scripts that (possibly) do not handle keeping for example .vectors
section even if the linker considers it unreferenced.
Instead, all existing configurations now disable
CONFIG_DEBUG_OPT_UNUSED_SECTIONS to prevent the linker from removing
any code. (Preserving previous behaviour.) This can be removed again
at some point after making sure that corresponding linker script
only removes code that is truly unused.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
This patch adds definitions for listed chips. No other changes are needed
as the chips are similar to the previously supported AVR128DA28 and all
that is needed is some definitions for extra peripherals.
AVR DA/DB family chips have single interrupt vector for all changes
on an I/O port. This poses problem when multiple drivers want to claim
the same interrupt (might happen for example with button and discrete
joystick drivers using pins on the same port.)
The I/O multiplexer solves it by providing interface similar
to irq_attach. However, it allows registration of multiple handlers
for the same interrupt vector with additional information recording
which pins should be serviced by each handler.
Only handler for pins that triggered the interrupt is then called.
Initial support adds chip specific files like Kconfig, flags for the compiler,
and basic functionality like system timer. Some files are stubs derived
from corresponding ATmega files but without the functionality they are
supposed to add (to be done in later patches)
Part of the work is altered copies of corresponding files for ATMega MCUs.
Initially supported is AVR128DA28.
This patch marks host GCC toolchain option with ARCH_TOOLCHAIN_GCC,
enabling various other settings depending on it. One of the enabled
settings is DEBUG_OPT_UNUSED_SECTIONS.
This patch also adjusts compiler and linker flags based on the value
of DEBUG_OPT_UNUSED_SECTIONS so unused sections are removed
The code used subi instruction to decrement the Y pointer but this
instruction only affects a byte, not a word. Fixed it by using
pre-decrement in the LD instruction instead.
Renaming "modlib" to "libelf" is more in line with the implementation content,
which makes it easier for individual developers to understand the capabilities of this module.
CONFIG_LIBC_MODLIB -> CONFIG_LIBC_ELF
Signed-off-by: chao an <anchao.archer@bytedance.com>
test:
1.use mps3-an547 build helloxx as module and run it
2.use qemu-armv7a:knsh test kernel build helloxx and run it
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Inline & inline_function both used make confuze, let's modify all inline
in irq.h to inline_function, also clear the always_inline_funcion
declaration.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Most tools used for compliance and SBOM generation use SPDX identifiers
This change brings us a step closer to an easy SBOM generation.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
reason:
When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."
When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.
As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some app with same code runs on different cores in AMP mode,
need the physical core on which the function is called.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
reason:
In the kernel, we are planning to remove all occurrences of up_cpu_pause as one of the steps to
simplify the implementation of critical sections. The goal is to enable spin_lock_irqsave to encapsulate critical sections,
thereby facilitating the replacement of critical sections(big lock) with smaller spin_lock_irqsave(small lock)
Signed-off-by: hujun5 <hujun5@xiaomi.com>
