the ${MENUCONFIG} file in the output directory is enough,
as invoking nuttx_generate_kconfig() will generate this
file in the output directory.
Since we are collecting these files recursively,
the nuttx_generate_kconfig() function of the parent directory
will be called after all the subdirectories' nuttx_generate_kconfig()
functions have been invoked.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
time/lib_localtime.c: In function 'tz_lock':
time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function)
396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP()))
| ^~~~~~~~~~~~~~~~~~~~
Signed-off-by: ligd <liguiding1@xiaomi.com>
Improve the pci ivshmem device compatibility, do not return error when
irq mode init failed, fallback to the polling mode as mush as possible.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
Since pthread_cond_broadcast is already protected by a mutex,
even if sem_post causes a context switch, it will not affect the count of wait_count.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Don't compile dump_assert_info logic if CONFIG_DEBUG_ALERT=n
With _alert() disabled this logic does nothing, but the compiler
is not smart enough to optimize this code.
on minimal stm32f3 configuration it saves 220B of flash.
The PLL clock configuration was simplified on the assumption the clocks are correctly set in the board.h file. Instead of seperate conditions
for register components, assume the relevant PLL registers are fully defined in board.h. This should result in easier to understand defines in board.h
and simpler code flow in the standard clock configuration function.
Changes were mad in the board file alongside changing the arch files. Changes to board/stm32h5:
- PLL1 has been configured to use integer instead of fractional mode to reach the 250 MHz target. PLL2 and PLL3 configurations were
removed since they are currently unused in the H5 configuration.
- PLL1 output was verified by testing for changes in serial baud rate.
reason:
new implementation does not requires the use of enter_critical_section,
so the source code needs to be moved to user space
This reverts commit d189a86a35.
syslog_putc() have a lot of duplicate logic with syslog_write().
remove syslog_putc() and reuse syslog_write() to simplify syslog printing.
Signed-off-by: chao an <anchao@lixiang.com>
reason:
When entering an exception or interrupt, there are two sets of registers:
one is the "running regs", which we need to save,
and the other is the "ready to running regs", which we may soon use.
For consistency in logic, we can always store the "running regs" in the regs field of g_running_tasks,
otherwise it may lead to errors in the storage location of the "running regs."
When we need to access the "running regs," we should uniformly retrieve them from the regs field of g_running_tasks.
As the next step, we will rename the set_current_regs/up_current_regs functions
for each architecture to more appropriate names, solely for the purpose of identifying interrupts.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
We decouple semcount from business logic by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
We could call backtrace from mm module and access to kasan protected mm_node.backtrace field. Disable kasan check for backtrace_format.
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
About libcxx with CONFIG_LIBC_ARCH_ATOMIC, it still
does not work. It is also needed to call nx_atomic_ ver
instead of __atomic ver in
libcxx/include/__atomic/cxx_atomic_lmpl.h.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
This performs the DDR training for imx93-evk. In addition to the source code,
it downloads binaries which are included in the final image. The bootloader
must be ARCH_CORTEX_A53 instead of A55 due to atomic instructions that don't
work with the OCRAM / EL3 combination.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit adds a max_pins field into the private struct.
AFEC0 has 11, AFEC1 has 12. The 12th pin of AFEC0 is an internal
pin connected to a temperature sensor, which we don't use.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
1. arch/arm/src/cmake/gcc.cmake: The same judgment has been made in line 164
2. boards/sim/sim/sim/scripts/Make.defs: arch/sim/src/Makefile also has in line 147
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Currently, there are four code coverage statistics implementations:
1. GCC native implementation
2. CLANG native implementation
3. GCC coverage nuttx mini version
4. CLANG coverage nuttx mini version
Coverage Support:
GCC native implementation CLANG native implementation GCC coverage nuttx mini version CLANG coverage nuttx mini version
Compiler version requirements ALL ALL GCC 13.2 and below CLANG 17.0 and below
Program coverage statistics support Main program √ √ √ √
Program coverage statistics support Interrupt program X √ √ √
Configuration options CONFIG_COVERAGE_TOOLCHAIN CONFIG_COVERAGE_COMPILER_RT CONFIG_COVERAGE_MINI CONFIG_COVERAGE_MINI
Platform Support ARM √ √ √ √
ARM64 √ √
(Coming soon, not yet merged)
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
