For AVR, atomic functions generated by LOAD macro turn into load surrounded
by up_irq_save and up_irq_restore. The generated code was incorrect as can
be seen from disassembly of __atomic_load_4:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
out 0x3f, r18 ; restore the flag
movw r30, r24 ; copy parameter (address) to pointer register
ld r22, Z ; indirect load to return value registers
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
ret ; return
The interrupts are disabled to be immediately re-enabled, the load only takes
place after that.
Both up_irq_save and up_irq_restore are defined in inline assembly. Other
architectures (x86/486, Risc-V) mark this assembly with clobbers: memory.
Doing the same thing for AVR alleviates the problem:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
movw r30, r24 ; copy address
ld r22, Z ; load
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
out 0x3f, r18 ; restore interrupts enabled flag
ret ; return
Besides compiling the code and checking the assembly, this was tested
with a custom stress application on AVR128DA28.
Assembly of up_irq_enable is marked in the same way with regards to clobbers.
This patch also removes two functions that are not called from anywhere
(up_irq_disabled, putsreg)
Signed-off-by: Kerogit <kr.git@kerogit.eu>
Changed copyright to apache copyright. Altered stm32_uid function to take uint32_t pointer instead of a twelve byte uint8_t array. Refined code in stm32_uid.c.
Fixed style and indentation.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
In singlewire mode the ops were only for non-dma usecases. But if rxdma is enabled we can use that.
For TXDMA it's not possible because we've to change pin direction immediately after transmission is done.
There is no more linking error for MPFS after the flagging is corrected in
drivers/timers/arch_alarm.c
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
For the RTL8211F PHY, configuration of RX/TXDLY was missing.
At least on my i.MX93 EVK, this is necessary for transmission
to work (RXDLY defaults to true on the PHY).
This commit brings support for RGMII internal delay configuration
(on or off for both directions) and enables it on the i.MX93 EVK
board. The introduced Kconfig is set to default to 'n', to avoid
breaking the functionality of other, out-of-tree boards based on
i.MX93, running the RTL8211F PHY, or to avoid introducing
unnecessary code on boards running other PHYs.
Configuration of internal delay on other PHYs is not
implemented, and results in a warning (but no error).
Signed-off-by: George Poulios <gpoulios@census-labs.com>
MUX_ENET1_TXC was missing from both the EVK board
definition and the IO muxing configuration function
of the ENET1 driver. As a result, transmission does
not work (unless the muxing is set by default in some
board? -not the case with EVK). This commit adds the
configuration and adds the definition to i.MX93 EVK.
WARN: other, out-of-tree i.MX93 boards need to define
MUX_ENET1_TXC accordingly, otherwise build will break.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Add up_perf_ functions for MPFS, which don't rely on alarm/oneshot interface.
Also add optimized up_udelay and up_ndelay functions, which use the MTIMER
directly to measure time; making them accurate and more multithreading friendly.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Bitfield CPHA has to be set to run SPI in mode 0. This is a default mode,
therefore it should be set during the peripheral initialization.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds a LPI2C driver for the mcx-nxxx chip, and the necessary board
definitions for the frdm-mcxn236 evaluation kit.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
FlexRAM peripheral was incorrectly clocked and turned during
M7 sleep. This patch fixes clock setting and ensure that clock
stays on during M7 for backdoor access from for example eDMA
Boards that run the i.MX9 bootloader at EL1 must not touch EL3-only
configuration. Add Kconfig guards so that:
* DDR training (IMX9_DDR_TRAINING)
* FIQ decode support (ARM64_DECODEFIQ)
are selected only when ARCH_ARM64_EXCEPTION_LEVEL == 3.
Code in arm64_chip_boot() is also guarded with ARCH_ARM64_EXCEPTION_LEVEL == 3
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
After `CONFIG_STACK_USAGE` enabled, no "*.su" file was generated, tools/showstack.sh output nothing.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
On rt10xx chips the MPU didn't got reset, which is needed for use
with bootloaders. Furthermore the TCM sizes where fixed now we use
kconfig symbol to set the size respectively. Also we mark ITCM as
RO/RO so we can't change data we executed from.
The up_saveusercontext function leverages USER_SAVE macro,
which is ordinarily used as a first half of the context switch.
This macro is therefore unsuitable to be used standalone,
it pops return address from the stack and does not return.
This patch adds missing instructions to do what would otherwise
be done by the second half of the context switch.
Tested by compiling and verifying the disassembly - the function
no longer falls through to the next function in the program memory,
push/pop instructions are balanced and stack contents preserved
Signed-off-by: Kerogit <kr.git@kerogit.eu>
This enables the use of the cryptographic accelerator within
the ESP32. The support algorithms are: SHA1, SHA256, SHA384
and SHA512.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
Fix case for CAN character driver in simulator when CANFD is disabled
and ch_edl field is not present in CAN header.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Interrupts should be disabled during the access to the user signature
area in internal flash memory, otherwise the system might be halted.
This applies also for read operation as this is performed with a
special flash commands on a special part of memory.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fix some misspelled field names.
These field names seem to be used only in private contexts.
Thus, the probability of external code accessing these fields is very
low.
In the rare case of external usage, compile time errors will easily
direct users to the new field name.
Properly select physical bank for block erase based on block number.
Previously, it would configure flash erase bank select based on the logical bank. If banks were swapped, and user application
tried to erase the first block of logical bank 2 (expecting to erase starting at 0x08100000), it would actually erase starting
at 0x0800000. This is fixed in this commit.
Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
After a mailing list suggestion, the indirection that enabled
ARCH_TOOLCHAIN_GCC only when user requested it is removed.
The indirection was a safety measure for chips and boards with linker
scripts that (possibly) do not handle keeping for example .vectors
section even if the linker considers it unreferenced.
Instead, all existing configurations now disable
CONFIG_DEBUG_OPT_UNUSED_SECTIONS to prevent the linker from removing
any code. (Preserving previous behaviour.) This can be removed again
at some point after making sure that corresponding linker script
only removes code that is truly unused.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
- Add ELE command to initialize the ELE RNG context.
- Add ELE command to poll the readiness of the RNG
- Add ELE command to obtain random numbers.
- Replace AHAB_ prefixes with ELE_
- Cleanup header includes
- Added some explanatory comments on .../hardware/imx9_ele.h
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.
Fixed by enabling the associated interrupt events.
Signed-off-by: michal matias <mich4l.matias@gmail.com>
