Commit graph

23539 commits

Author SHA1 Message Date
Ville Juven
6707715916 arch/risc-v: PANIC() on system call crash
If a process causes a fatal error when it's running a system call, the
whole system should crash as the crash originated from the kernel.

Do this by running the PANIC() branch, if task is in syscall.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-10 22:36:02 +08:00
zhangshoukui
69597ec486 arch/sim: Add i2s setup and shutdown interface
This interface is required if you want to open an i2c node directly on the sim
12b4340b00

Signed-off-by: zhangshoukui <zhangshoukui@xiaomi.com>
2025-04-10 18:10:54 +08:00
anjiahao
c9a150781c arch/arm64: remove unrecognized command-line option
aarch64-none-elf-gcc: error: unrecognized command-line option '-mlong-calls'

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2025-04-09 23:07:29 +08:00
anjiahao
3411e5c6db arm:elf module need long call aviod jump addr over length
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2025-04-09 23:07:29 +08:00
anjiahao
422c43949a binfmt:use crt0 inside of starthook
test:
1.use mps3-an547 build helloxx as module and run it
2.use qemu-armv7a:knsh test kernel build helloxx and run it

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2025-04-09 23:07:29 +08:00
anjiahao
297a1cb1fe armv7a:need initialize constructor and destructor on crt0
The C++ constructor and destructor need to be executed in crt0

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2025-04-09 23:07:29 +08:00
Tiago Medicci Serrano
05e63e31c4 arch/xtensa/espressif: Fix ESP32-S2 SPI flash frequency selection
This commit fixes the SPI flash frequency selection for ESP32-S2,
enabling the Kconfig macros to be selected when ESP32-S2 SoC is
enabled. Please note that this was recently changed to make it
compatible with already existing SPI flash Kconfig macros for ESP32
and ESP32-S3 and it introduced this regression for ESP32-S2.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-09 14:00:08 +08:00
Eren Terzioglu
8a835dd545 arch/xtensa: Remove legacy I2S implementation for esp32[-|-s2|s3]
Remove legacy I2S implementation without breaking defconfigs for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
97ff8906e4 arch/esp[s2|s3]: Update common layer version
Update common layer version of Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
873a6319bb arch/esp32[s2|s3]: Add common I2S arch layer support
Add common I2S arch layer support for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
Eren Terzioglu
fd4914b953 arch/xtensa/esp32[s3]: Add more dma functions
Add dma function to use peripheral more efficiently

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-04-08 22:53:58 +08:00
chenxiaoyi
b3567fe964 xtensa/esp32s2: enable sysclk and deassert reset signal for uart1
The uart1 is found be in reset state, and the sysclk is not enabled
for it.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2025-04-08 22:44:59 +08:00
Tiago Medicci Serrano
622355b5c3 arch/xtensa/esp32s3: Fix bug regarding SPI flash operation mode
SPI flash operation modes - Dual Output (dout), Dual I/O (dio),
Quad Output (qout), Quad I/O (qio) and Octal (opi) were not being
properly selected. This commit fixes this behavior and the device
is now able to boot and initialize the proper SPI flash mode.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-08 14:44:38 +08:00
raiden00pl
5d66f2c973 arch/stm32f0l0g0: add support for IWDG and WWDG
add IWDG and WWDG support for stm32f0l0g0.

ported from arch/stm32.

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-07 23:28:47 +08:00
liujp
32c5667d5d Optimize double buffering implementation
optimize the implemented dual buffer support to avoid compilation errors on other development boards.

Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-07 16:28:30 +08:00
liujp
e421e2c9e5 arch/arm/stm32h7: add support for STM32H750B
modify the compilation configuration of stm32h7, add compilation options for stm32h750.

Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-07 16:28:30 +08:00
Kye Morton
a8b862396e arch/arm: Add CMakeLists for the stm32l4 architecture.
boards/arm: Add CMakeLists for the nucleo-l476rg.

Adds CMakeLists files for the STM32L4 architectures
and one of the development boards. Files are adapted
from the similar STM32F7 boards, but built to reflect
the existing Make.defs.

Signed-off-by: Kye Morton <pryre.dev@outlook.com>
2025-04-07 12:10:40 +08:00
raiden00pl
57d1dee7e1 arch/arm: add stm32c0 support
add stm32c0 support

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-05 11:23:40 -03:00
Tiago Medicci Serrano
80559890ff espressif: Simplify the selection of the SPI flash frequency
This commit simplifies the selection of the SPI flash frequency for
Espressif SoCs by using a standardized Kconfig-defined macro.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-05 11:26:32 +08:00
Tiago Medicci Serrano
1e8250d918 boards/xtensa/esp32s3: Move some .bss sections to the external RAM
This commit moves some internal libraries' .bss sections to the
external PSRAM chip, freeing internal memory for other usages. Note
that it is necessary to update `esp32s3-devkit:python` defconfig
otherwise it would fail to build.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-05 11:24:58 +08:00
raiden00pl
23ef48e673 arch/stm32f0l0g0/stm32_adc.c: fix ADC calibration
Fix and enable ADC calibration. The ADC voltage regulator must be
enabled and regulator start-up time must be respected.

tested on nucleo-c071rb and b-l072z-lrwan1

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-05 11:23:47 +08:00
Jinliang Li
d5db7d1cee libc/arm: optimize crc32/crc32c for arm
Optimize crc32 standard(poly:0x04C11DB7) and crc32
castagnoli(poly:0x1EDC6F41) with arm crc32 extension instructions.

For example, crc32 standard caculates(lookup crc32 table) 1812 bytes data,
reduced the time from 118 us to 14 us through optimization.

Performance improved ~700%

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-04 09:51:50 -03:00
Laczen JMS
34bb3c88a2 arch/xtensa/src/esp32: remove espnow
remove espnow pktradio from arch/xtensa/src/esp32

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-04-04 06:49:50 +08:00
Laczen JMS
58463d9484 arch/xtensa/src/common/espressif: Introduce espnow
Move espnow:
 arch/xtensa/src/esp32 -> arch/xtensa/src/common/espressif

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-04-04 06:49:50 +08:00
Ville Juven
cc64c026d9 mpfs/mpfs_entrypoints.c: Change atomic_load > atomic_read
Otherwise we get an undefined symbol error when LIBC_ARCH_ATOMIC is
defined.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-03 18:34:11 +08:00
Jinliang Li
95ba78e1bd arch/armv8-r: Enable fpu before arm_el_init
In the arm_el_init function, the FPU might be used, for example, the
assembly optimization of memcpy in arm_tcm_load uses FPU and NEON
instructions and registers.
Therefore, it's important to initialize the
FPU as early as possible to prevent system hangs that could occur if the
FPU is used without being initialized.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-02 21:07:54 +08:00
buxiasen
41cbbb0c12 arch/arm/imx6: fix missed comma
Will Compile error if enable IMX6_UART2..5

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2025-04-02 21:05:52 +08:00
raiden00pl
5d2e0f8c80 arch/esp32s3/esp32s3_wdt_lowerhalf.c: fix printf warning
fix printf warning:

chip/esp32s3_wdt_lowerhalf.c:497:17: error: format '%u' expects argument of
type 'unsigned int', but argument 4 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
649e979f58 arch/esp32s2/esp32s2_wdt_lowerhalf.c: fix printf warning
fix printf warning:

chip/esp32s2_wdt_lowerhalf.c:493:17: error: format '%u' expects argument of
type 'unsigned int', but argument 4 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
1a6cb4c784 arch/esp32s3/esp32s3_ble_adapter.c: fix printf warning
fix printf warning:

chip/esp32s3_ble_adapter.c:1065:13: error: format '%u' expects argument of
type 'unsigned int', but argument 3 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
raiden00pl
ea28e08be4 arch/esp32/esp32_ble_adapter.c: fix printf warning
fix printf warning:

  chip/esp32_ble_adapter.c:1137:13: error: format '%u' expects argument of
  type 'unsigned int', but argument 3 has type 'long unsigned int'

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-04-02 08:29:00 -03:00
ouyangxiangzhen
87c217ad93 arch/x86_64: Fix strict-prototype warning.
This commit fixed a strict-prototype warning.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2025-04-02 12:01:46 +08:00
ouyangxiangzhen
0c9a239b9e arch/x86_64: Initialize framebuffer early-print.
This commit initialized framebuffer early-print if `CONFIG_MULTBOOT2_FB_TERM` is defined. This enabled `early_kprintf` to output debug information using framebuffer.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2025-04-02 12:01:46 +08:00
ouyangxiangzhen
d7cea12af3 arch/x86_64: Fix fb_putc for early-print.
This commit fixed `fb_putc` for early-print.
- Modified fb_putc to return an int instead of void.
- Handled error cases where the character is not found by replacing it with a '.'.
- Ensured cursor position is updated correctly after each character is processed.
- Fixed above 4G framebuffer memory mapping.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2025-04-02 12:01:46 +08:00
Tiago Medicci Serrano
b388b84af6 arch/risc-v/esp32h2: Set the default SPI flash frequency to 64MHz
The default frequency for the SPI flash chip on ESP32-H2 is 64MHz.
Although it was being set to 48MHz, this isn't a valid value. The
device, however, must be flashed using 48MHz when 64MHz is set.
2025-04-02 09:53:27 +08:00
liujp
c4b81bb922 feat(nuttx): implement stm32h7 ltdc double buffer on layer 1
Signed-off-by: liujp <liujp@xiaomi.com>
2025-04-01 17:00:02 -03:00
Ville Juven
04df2ccead arch/mpfs/mpfs_usb.c: Replace big kernel lock with spin lock
Remove call to enter_critical_section (big kernel lock) and replace it
with a smaller lock to protect the USB clock and its reference counter.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-01 20:49:43 +08:00
Ville Juven
4c7fedebd1 arch/mpfs/mpfs_ethernet.c: Replace big kernel lock with spin lock
Remove call to enter_critical_section (big kernel lock) and replace it
with a smaller lock.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-01 20:49:43 +08:00
Ville Juven
f165407ac8 arch/mpfs/mpfs_mmc.c: Replace big kernel lock with spin lock
Remove call to enter_critical_section (big kernel lock) and replace it
with a smaller lock.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-01 20:49:43 +08:00
Ville Juven
01b5a70666 arch/mpfs/mpfs_dsn.c: Replace big kernel lock with spin lock
Remove call to enter_critical_section (big kernel lock) and replace it
with a smaller lock.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-01 20:49:43 +08:00
Eero Nurkkala
95163f504c risc-v/mpfs: usb: fix fierce cpu polling if remote closes
If the remote end just closes an endpoint and no longer handles it,
the system is prone to intensive cpu polling via mpfs_write_tx_fifo()
especially if the device side doesn't know a thing about what the
remote did.

Fix this by marking the EP as dead, which will skip all writes causing
unnecessary polling. The EP is back in business if the remote end
sends some data (rx) or the connection is re-established.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Ville Juven <ville.juven@unikie.com>
2025-04-01 20:49:43 +08:00
Laczen JMS
b8964f5c46 arch/xtensa/src/common/espressif: Add wlan config option
Add an option to configure wlan support

Signed-off-by: Laczen JMS <laczenjms@gmail.com>
2025-03-31 11:35:39 -03:00
wangjianyu3
cc23e06ea2 arch/esp32s3: The MISO, MOSI and C/S are optional
The MISO or MOSI pin is optional.
The C/S pin is unnecessary when `ESP32S3_SPI_UDCS` is enabled.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2025-03-29 10:33:45 +08:00
Michal Lenc
bd628883ab arch/arm/src/samv7: enable GPIO clock even if interrupt not enabled
GPIO peripheral clocks have to be enabled even if interrupt support
on the peripheral is not enabled, otherwise GPIO input will not work.
This is probably caused by input filters that need clock signal.

This commit moves the clock enable call from interrupt specific function
to common initialization function that is called from _start entry
point function.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2025-03-29 10:33:25 +08:00
nuttxs
bfcc283694 arch/esp32_himemcdev: Multiple instances of struct file for the same file
share the f_inode, ensuring that the mapping status is associated with
the file entity rather than a single descriptor.
Avoid redundant mapping operations caused by multiple descriptors
operating on the same file.

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-03-27 02:27:35 +08:00
Yanfeng Liu
672f806a7e arch/armv7-r: relax ARM_THUMB
This drops forcing ARM_THUMB for ARMV7R so that downstream chips
can use it optionally.

Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
2025-03-27 02:25:05 +08:00
Yanfeng Liu
c7d3f92867 arch/arm: guard .thumb_func use
This guards use of .thumb_func with ARM_THUBM kconfig so that
CONFIG_ARM_THUMB can be off for cases like qemu-armv7r:pnsh

Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
2025-03-27 02:25:05 +08:00
lpxiao
9e07b4a924 arch/arm/stm32: fix stm32f1xx alarm support
Summary:
stm32: support querying a previously set RTC alarm In the STM32F1xx series

Impact:
When using the stm32f1xx series MCU, the alarm function can be used, but when we enabled the CONFIG_RTC_ALARM configuration, an error was reported due to the inability to find the specific implementation of rdalarm.

Testing:
In our own projects, we have done alarm verification using the STM32F103RE..
2025-03-27 02:22:51 +08:00
Tim Kan(SSS)
1c6b603eec feat(arch/xensa): add CONFIG_SPIRAM_MEMTEST from ESP-IDF
The CONFIG item is beneficial for startup performance tuning, so
it would be better to have it in Nuttx as well.

Co-authored-by: FunatsuTaishi <51806905+FunatsuTaishi@users.noreply.github.com>
Co-authored-by: Roy Feng <roy.feng@sony.com>
Signed-off-by: Tim Kan(SSS) <tim.kan@sony.com>
2025-03-27 02:21:16 +08:00
nuttxs
720c6cce6f arch/esp32_partition: read data from SPI Flash at designated
address (with decryption)

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-03-27 02:21:04 +08:00