Commit graph

22800 commits

Author SHA1 Message Date
anjiahao
b81b16ba97 arm7/8-m:support all nuttx iamge build with pic
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.

Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
anjiahao
112b6fd9a5 modlib:support modlib can load PIC elf
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-16 18:40:06 +08:00
fanjiangang
b6a4e91ef0 armv8-r/cp15: fix the problem of op1 operand confusion in ICC_SGI1R
Reference:

https://developer.arm.com/documentation/100026/0103/Generic-Interrupt-Controller/GIC-programmers-model/CPU-Interface-Registers

              CRn   Op1    CRm    Op2
    ICC_SGI0R  -     2     c12     -
    ICC_SGI1R  -     0     c12     -

Signed-off-by: fanjiangang <fanjiangang@lixiang.com>
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-16 17:17:30 +08:00
yinshengkai
d01bbaecc1 sim/heap: malloc returns a valid pointer when allocating 0 bytes.
The default heap management in nuttx returns a valid memory address when malloc(0).
In sim_heap, malloc(0) returns NULL, aligning the behavior of sim_heap with mm_heap

The man manual describes malloc as follows:
https://man7.org/linux/man-pages/man3/malloc.3.html

The malloc() function allocates size bytes and returns a pointer
to the allocated memory.  The memory is not initialized.  If size
is 0, then malloc() returns a unique pointer value that can later
be successfully passed to free().  (See "Nonportable behavior"
for portability issues.)

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-16 17:03:40 +08:00
Jukka Laitinen
6a5b395459 arch/arm64/src/imx9: Add initial version of canbus driver
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-16 15:43:19 +08:00
Jukka Laitinen
bcfdb58686 arch/arm64/src/common/arm64_initialize.c: Add initializing of socket can interface
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-10-16 15:43:19 +08:00
wurui3
de2920605d sim_offload: add MONO channel encode method and set samplerate before encode.
According to different pcm data format, set real sample rate and encode separately.

Signed-off-by: wurui3 <wurui3@xiaomi.com>
2024-10-16 15:40:35 +08:00
wangmingrong1
bf70cd2bce bug/fix: Makefile expression error caused
expr: syntax error: unexpected argument "12"
expr: syntax error: unexpected argument "12"

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-16 15:35:04 +08:00
Peter Bee
8f77e3cfc4 select ARM_HAVE_MVE and ARCH_HAVE_FPU for mps platform
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2024-10-16 13:55:30 +08:00
ouyangxiangzhen
a45f903650 imx8qm-mek: Resolve boot issue for non-EL3 environments.
This commit addresses the issue of unauthorized writes to cntfrq_el0 during boot when not in EL3 mode.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-10-16 13:54:44 +08:00
liwenxiang1
8a1743d0a6 arch/x86_64: Resolving NUC Boot Failure Issue
The segment of the Xen PVH boot protocol was not specified during linking and was placed before .loader.text, causing the boot to fail

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-16 13:53:11 +08:00
wangming9
d9558a3583 arm/armv7-r: Correctly use CONFIG_ARMV7R_ASSOCIATIVITY_16WAY
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-16 12:27:10 +08:00
qiaohaijiao1
54e128367d sim/alsa: clear AUDIO_APB_FINAL flag before DEQUEUE
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:23:17 +08:00
qiaohaijiao1
eba292f4b9 sim/alsa: add ptr check in _stop
Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:21:19 +08:00
qiaohaijiao1
09afb4d7d0 sim/alsa: fix runtime warning.
sim/posix/sim_offload.c:369:18: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'
    #0 0x3a146c2  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a146c2)
    #1 0x3a0ecb0  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a0ecb0)
    #2 0x3a1193a  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a1193a)
    #3 0x3a13141  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x3a13141)
    #4 0x39fc3ef  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x39fc3ef)
    #5 0x38ca7f2  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x38ca7f2)
    #6 0x39fc6cf  (/home/qiaohj/disk1/work/vela/nuttx/nuttx+0x39fc6cf)

Signed-off-by: qiaohaijiao1 <qiaohaijiao1@xiaomi.com>
2024-10-16 12:17:35 +08:00
Gao Jiawei
d5c44de14c add missing source file
Signed-off-by: Gao Jiawei <gaojiawei@xiaomi.com>
2024-10-16 08:04:13 +08:00
Kyle Wilson
df47241a2b STM32G4 Flash Driver
Added a flash driver for the STM32G4 series. The primary change here is
the addition of stm32g4xxx_flash.c. This file uses the STM32L4 flash
driver as a template. The primary difference is the accounting for dual
banks with different page sizes.

Fixed error while building b-g474e-dpow1/buckboost. It was possible (technically) to have page be used uninitialzied. Changing the if statement to default to using a flash_page_size == 2048 fixes this issue.
2024-10-15 18:11:38 -03:00
cuiziwei
9d9857acd2 Change the judgment of GCCVER version to greater equal.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 23:32:13 +08:00
Tim Hardisty
bb7dce11a2 SAMA5 fix compiler warning in sam_adc.c 2024-10-15 11:37:54 -03:00
zhangyuan29
57650d841e armv8-m: set fpscr when do exception_direct
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2024-10-15 22:16:09 +08:00
anjiahao
ef9640c696 armv7-a:adjust gdb register order
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-10-15 21:46:41 +08:00
wangming9
5b14fb75bc arm/fpu: FPU is supported when the TEE is enabled
Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
   Non-secure access to coprocessor 11,10 enable

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:11:15 +08:00
wangming9
f465443f37 cpuinfo: Decouple the fetch cpuinfo from up_perf_getfreq
Summary:
Add the default CPU frequency configuration.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:11:15 +08:00
wangming9
6ee747a1e6 arm/goldfish: add memory map for DDR region
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-15 21:01:47 +08:00
hujun5
49b9aa0f33 arm/riscv: remove redundant judgment
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:32:40 +08:00
hujun5
aa0346610b arm64: we need to initialize the percpu register storing the current task more earlier.
A call stack looks like the following:
sched_idletask
syslog_write
nx_vsyslog
syslog
getreg64
gic_validate_redist_version
arm64_gic_init
arm64_gic_secondary_init
arm64_boot_secondary_c_routine

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:25:55 +08:00
hujun5
948ac9b4cc arm64: add up_this_task and up_change_task macro impl
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 15:25:55 +08:00
xuxin19
696e1a3f70 cmake(fix warning):toolchain do not have parent scope
toolchain file variable is global scope
dont need set parent scope

clear warning:
CMake Warning (dev) at /github/workspace/sources/nuttx/arch/arm/src/cmake/gcc.cmake:69 (set):
  Cannot set "GCCVER": current scope has no parent.
Call Stack (most recent call first):
  /github/workspace/sources/nuttx/arch/arm/src/cmake/Toolchain.cmake:56 (include)
  /github/workspace/sources/nuttx/build/CMakeFiles/3.26.0/CMakeSystem.cmake:6 (include)
  /github/workspace/sources/nuttx/build/CMakeFiles/CMakeScratch/TryCompile-ZJVOZO/CMakeLists.txt:5 (project)
This warning is for project developers.  Use -Wno-dev to suppress it.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-15 12:38:14 +08:00
cuiziwei
036a0674db nuttx/libc:Add _dl_find_object and dl_iterate_phdr function.
Add _dl_find_object() function, because when cxx_exception configuration is enabled, a link error occurs and that function cannot be found.

ld: /usr/lib/gcc/x86_64-linux-gnu/13/libgcc_eh.a(unwind-dw2-fde-dip.o): in function `_Unwind_Find_FDE':
(.text+0x250c): undefined reference to `_dl_find_object'

Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 12:35:54 +08:00
wanggang26
aef584a804 shm:fix build error
nuttx/arch/arm/src/armv7-a/arm_addrenv_shm.c:77:(.text.up_shmat+0x2e):
undefined reference to `shminfo'

Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 11:40:34 +08:00
wanggang26
7e5fb8450f coredump: add architecture-specific registers dump, including NVIC and MPU
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 11:40:05 +08:00
cuiziwei
6f62ef0b6f nuttx/sim:Remove asan check in up_irq_save().
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-15 03:36:55 +08:00
hujun5
d77cb8af70 sched: fix nxsched_process_delivered did not call hook
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 01:50:06 +08:00
hujun5
10659a8bc2 irq: irq_attach_wqueue replace irq_attach_thread
reason:
using a shared same priority queue can reduce memory consumption.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-15 01:12:14 +08:00
wanggang26
3fad764804 arch/armv7:fix a typo
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2024-10-15 01:06:59 +08:00
Xu Xingliang
632feb2b51 arch/arm64: remove struct regs_context
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-14 23:05:56 +08:00
cuiziwei
a08df48774 arch/x86_64:Add CXX configuration for enabling x86_64 support for C++ applications.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-14 19:03:30 +08:00
xuxingliang
f031dc39a6 arch/arm64: fix build warnings
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=]
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:29: note: format string is defined here
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |                        ~~~~~^
      |                             |
      |                             long long unsigned int
      |                        %08lX
common/arm64_mpu.c:355:13: error: format '%llX' expects argument of type 'long long unsigned int', but argument 5 has type 'long unsigned int' [-Werror=format=]
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
common/arm64_mpu.c:355:38: note: format string is defined here
  355 |       _info("MPU-%d, 0x%08llX-0x%08llX SH=%llX AP=%llX XN=%llX\n", i,

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-14 17:59:56 +08:00
chao an
7288a8d000 arch/arm64: add support to config SPI interrupt affinity routing to CPU0 by default
Signed-off-by: chao an <anchao@lixiang.com>
2024-10-14 17:58:13 +08:00
chao an
83c483c1b4 arch/armv8-a: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-10-14 17:58:13 +08:00
liwenxiang1
3e2e2132ca arch/x86_64:Adjust the position of the nm command to execute it after NuttX is generated
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2024-10-14 17:55:59 +08:00
p-szafonimateusz
c18f722185 arch/intel64: optimise context switch
We save interrupted TCB state on tcb->xcp.regs not interrupt stack now
which allows us to remove x86_64_savestate() from up_switch_context()
and other places.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-10-14 17:54:06 +08:00
xuxingliang
d655569a7c cmake: add newly added sources to cmake
These newly added files are missing from cmake.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-10-14 17:19:45 +08:00
nuttxs
9308675686 xtensa/esp32s3: add wapi support for getting country code
commands on ESP32-S3
2024-10-14 13:42:37 +08:00
cuiziwei
7246533aeb Unify the definition of GCCVER and remove duplicate code.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-10-13 11:41:22 +08:00
Marco Casaroli
c17ab3beb5 feat(esp32s3): add openeth ethernet driver for qemu
We add the config for esp32s3, then move the esp32 specifics to
esp32/chip.h, then add the esp32s3 specifics to esp32s3/chip.h.
2024-10-13 11:19:51 +08:00
Marco Casaroli
d5b32f0335 feat(esp32_openeth): move to common/espressif
Since this will be used for esp32s3 also, we can have this in
common/espressif.
2024-10-13 11:19:51 +08:00
xuxin19
57bfd02cef build ci:add msvc windows native ci workflow
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-10-13 10:25:19 +08:00
chenzhijia
505adfa277 nuttx:move "#define STRINGIFY(x)" to nuttx/macro.h
Franklin requirement, "#define STRINGIFY(x)" conflicts with https://github.com/mborgerding/kissfft define

Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2024-10-13 03:16:25 +08:00
Bowen Wang
143466baed drivers/pci: fix pci framework warning in 32bit chip
In file included from pci/pci.c:30:
pci/pci.c: In function 'pci_setup_device':
pci/pci.c:449:66: warning: right shift count >= width of type [-Wshift-count-overflow]
  449 |           pci_write_config_dword(dev, base_address_1, res->start >> 32);
      |                                                                  ^~
pci/pci.c: In function 'pci_presetup_bridge':
pci/pci.c:541:51: warning: right shift count >= width of type [-Wshift-count-overflow]
  541 |                              ctrl->mem_pref.start >> 32);
      |                                                   ^~
pci/pci.c: In function 'pci_postsetup_bridge':
pci/pci.c:604:57: warning: right shift count >= width of type [-Wshift-count-overflow]
  604 |                              (ctrl->mem_pref.start - 1) >> 32);
      |                                                         ^~
CC:  pthread/pthread_release.c pci/pci_ecam.c:71:12: warning: initialization of 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  uint32_t *)' {aka 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  long unsigned int *)'} from incompatible pointer type 'int (*)(struct pci_bus_s *, uint32_t,  int,  int,  uint32_t *)' {aka 'int (*)(struct pci_bus_s *, long unsigned int,  int,  int,  long unsigned int *)'} [-Wincompatible-pointer-types]
   71 |   .read  = pci_ecam_read_config,
      |            ^~~~~~~~~~~~~~~~~~~~
pci/pci_ecam.c:71:12: note: (near initialization for 'g_pci_ecam_ops.read')
pci/pci_ecam.c:72:12: warning: initialization of 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  uint32_t)' {aka 'int (*)(struct pci_bus_s *, unsigned int,  int,  int,  long unsigned int)'} from incompatible pointer type 'int (*)(struct pci_bus_s *, uint32_t,  int,  int,  uint32_t)' {aka 'int (*)(struct pci_bus_s *, long unsigned int,  int,  int,  long unsigned int)'} [-Wincompatible-pointer-types]
   72 |   .write = pci_ecam_write_config,

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-10-13 02:28:32 +08:00