Commit graph

83 commits

Author SHA1 Message Date
Lup Yuen Lee
edbf2e21e7 CI: Move rv-virt:python from risc-v-06 to risc-v-07 2024-12-12 23:38:35 +08:00
chao an
2961ecab9f sim/tflm: add tflite-micro demo into ci build
$ cmake -B build -DBOARD_CONFIG=sim/tflm -GNinja
$ cmake --build build
$ ./build/nuttx

NuttShell (NSH) NuttX-10.4.0
nsh> tflm -h

Utility to use tflite micro on nuttx.
[ -C       ] Compile tflite model into c++ codes.
[ -E       ] Do once evaluation (for profiling).
[ -i <str> ] Readable model file path.
[ -o <str> ] Writable c++ file path.
[ -p <str> ] Prefix of compiled code.
[ -a <int> ] Arena size (mempool).
[ -h       ] Print this message.

nsh> tflm -E -i /data/MobileNet-v3-Small.tflite -o /data/MbileNet-v3-Small.out
0 (id=0): size=602112, offset=0, first_used=0 last_used=1
1 (id=1): size=602112, offset=602112, first_used=1 last_used=2
2 (id=2): size=602112, offset=0, first_used=2 last_used=3
3 (id=3): size=607504, offset=802816, first_used=3 last_used=4
...
* (id=114): size=4096, offset=0, first_used=114 last_used=115
* (id=115): size=4000, offset=4096, first_used=115 last_used=115
 0: 00000000000000000000000000...................................................... (588k)
 1: 0000000000000000000000000011111111111111111111111111............................ (1176k)
 2: 2222222222222222222222222211111111111111111111111111............................ (1176k)
 3: 22222222222222222222222222........333333333333333333333333333................... (1182k)
...
"Event","Tag","Ticks"
0,SUB,0
1,MUL,0
2,PAD,0
3,CONV_2D,1
4,HARD_SWISH,0
5,PAD,0
...
110,MEAN,0
111,FULLY_CONNECTED,0
112,FULLY_CONNECTED,0
113,MUL,0
114,FULLY_CONNECTED,0
"Unique Tag","Total ticks across all events with that tag."
SUB, 0
MUL, 0
PAD, 0
CONV_2D, 3
...
"total number of ticks", 3
nxai done!

Signed-off-by: chao an <anchao@lixiang.com>
2024-11-29 18:34:10 +08:00
raiden00pl
7e42ca2538 boards/stm32: split nucleo-f4x1re into separate boards
Split nucleo-f4x1re into nucleo-f401re and nucleo-f411re.
These are separate boards and should be in separate directories as it's
done for all other nucleo boards in NuttX
2024-11-19 13:28:42 +01:00
xuxin19
d2a7e454bb build(qemu):add a qemu compilation configuration with application
enable various types of common applications and libraries, and enable CMake CI checks.
To avoid regression issues in the build system

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-11-14 22:50:49 +08:00
wangmingrong1
1d1ef52d1a arm/mps: Add a gcov functional testing configuration for mps-clang
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-11-13 05:33:00 +08:00
Lup Yuen Lee
f566c1a940 sim: Build quickjs with CMake 2024-11-12 12:10:42 +08:00
wangmingrong1
240dc3d5e1 mps/clang: Add a defconfig for mps to support clang compilation
1. Enable compiler_rt library builtin function

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2024-10-28 22:19:58 +08:00
Lup Yuen Lee
c4d754f135 CI: Split the targets in sim-01 and add sim-03
This PR splits the CI Build Job sim-01 and adds sim-03:

Before the Split: Simulator Jobs take up to 1.5 hours to complete
- sim-01 (1 hour 31 mins): adb, citest, lvgl, matter
- sim-02 (28 mins): posix_test, sqlite

After the Split: Simulator Jobs will complete within 1 hour
- sim-01 (58 mins): adb, citest
- sim-02 (35 mins): lvgl, matter
- sim-03 (28 mins): posix_test, sqlite

This will help us comply with the ASF Policy for GitHub Actions, as explained here: https://github.com/apache/nuttx/issues/14376
2024-10-22 08:55:20 +08:00
raiden00pl
6657f2abb7 boards/arm/stm32f7: separate nucleo-144 board into individual boards
nucleo-144 combines 3 different ST boards. This approach is inconsistent with
the support for the rest of the nucleo boards, where each board is in separate folders.
Also nucleo-144 is no longer reserved for STM32F7 chips but other families also use this format.

After this commit nucleo-144 is divided into 3 boards:

- nucleo-f746zg
- nucleo-f767zi
- nucleo-f722ze
2024-10-21 09:23:44 +08:00
Lup Yuen Lee
9c1e0d3d64 CI: Split the Build Jobs for Arm64 and x86_64
This PR creates the new CI Build Jobs `arm64-01` and `x86_64-01`. The new jobs will split and offload the Arm64 and x86_64 Build Targets from `other`. This will reduce our usage of GitHub Runners, to comply with the ASF Policy for GitHub Actions. (Recently we see more PRs for Arm64 and x86_64)

Before the Split: Simple PRs (One Arch and/or One Board) for Arm64 and x86_64 require almost 1 hour for CI Build
- `other` (57 mins): AVR, SPARC, x86, PinePhone, QEMU Arm64, QEMU x86_64

After the Split: Simple PRs for Arm64 and x86_64 will complete under 30 mins
- `other` (24 mins): AVR, SPARC, x86
- `arm64-01` (29 mins): PinePhone, QEMU Arm64
- `x86_64-01` (9 mins): QEMU x86_64

To skip more unnecessary builds: Our Build Rules `arch.yml` shall ignore the label "Area: Documentation", so that a Simple PR + Docs is still a Simple PR. Previously we experienced longer CI Build Times, just because we added docs to our Simple PR. (Now our PR shall be built exactly like a Simple PR)

The updated CI code is explained here: https://github.com/apache/nuttx/issues/13775
2024-10-20 09:49:13 +08:00
Marco Casaroli
83455a3fa1 ci: skip config
since this config requires bootloader, we skip it
2024-10-13 11:19:51 +08:00
yinshengkai
cac90afe79 Revert "sim/note: add note related configuration"
This reverts commit 154cb4a860.
2024-10-11 21:30:19 +08:00
yinshengkai
154cb4a860 sim/note: add note related configuration
Ensure that CI can cover all note code

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-10-11 11:55:17 +08:00
Lup Yuen Lee
80d03cb296 CI: Split the RISC-V Build Jobs into smaller jobs
To speed up the CI Workflow, this PR splits the CI Build Jobs for RISC-V into smaller jobs. Each job will now complete within 1 hour.

Before the PR: There are 2 jobs for RISC-V, each requiring more than 1.5 hours
- `risc-v-01` (1 hour 42 mins): BL602, Ox64, ESP32-C3 / C6 / H2
- `risc-v-02` (1 hour 41 mins): K230, Icicle, QEMU, RV32M1-Vega

After the PR: The build is spread across 6 jobs for RISC-V, each job completes within 1 hour
- `risc-v-01` (19 mins): BL602, Ox64
- `risc-v-02` (44 mins): ESP32-C3
- `risc-v-03` (45 mins): ESP32-C6, ESP32-H2
- `risc-v-04` (31 mins): K230, Icicle
- `risc-v-05` (41 mins): QEMU CITest
- `risc-v-06` (38 mins): Rest of QEMU, RV32M1-Vega

Following the same convention as the Arm32 Build Jobs, the above jobs are sorted by Target Name. Performance of the RISC-V Build Jobs is discussed in https://github.com/apache/nuttx/issues/13775
2024-10-10 08:44:02 +08:00
Lup Yuen Lee
c74206a982 CI: Split the Build Job arm-05 into multiple smaller jobs
CI Build Job `arm-05` (runtime 2 hours) has become the Performance Bottleneck for CI Workflow. That's because `arm-05` builds too many targets for nRF, RP2040, SAM 3, SAM A and SAM D. This PR splits `arm-05` into multiple smaller jobs, to reduce the CI Build Duration.

Before the PR: `arm-05` is overloaded, build requires 2 hours
- `arm-05` (2 hours): nRF, RP2040, SAM 3, SAM A, SAM D
- `arm-06` (56 mins): STM32 [a-m]*

After the PR: `arm-05` is offloaded (to `arm-06` and `arm-07`), completes within 1 hour
- `arm-05` (47 mins): nRF
- `arm-06` (1 hour): Reserve for RP2040 exclusively
- `arm-07` (1 hour 15 mins): SAM 3, SAM A, SAM D, STM32 [a-m]*

Build Jobs are sorted by Target Name. So we cascade the changes and rename the Build Jobs: `arm-07` becomes `arm-08`, `arm-08` becomes `arm-09` etc. Then `arm-13` becomes a new job `arm-14`. (Which we added to `build.yml`)

Performance of `arm-05` is discussed in https://github.com/apache/nuttx/issues/13775 and https://github.com/apache/nuttx/issues/12773
2024-10-09 13:45:26 +08:00
YAMAMOTO Takashi
8e5f6de7e5 CI: drop stm3240g-eval:knxwm for now
cf. https://github.com/apache/nuttx/issues/13246
2024-08-30 21:03:08 +08:00
simbit18
1661a66843 [cmake]: added initial support for MSYS2
Currently concerns only arm.

tools/ci/testlist/msys2.dat:
At the moment I only added the board nucleo-l152re:nsh

.github/workflows/build.yml:
Enabled cmake for msys2
2024-08-27 21:36:12 +08:00
simbit18
3637040d73 tools/ci/testlist: Added jobs to speed up CI checks.
Divided jobs risc-v and xtensa to finish workflow under 2 hours.
2024-07-30 01:43:29 +08:00
simbit18
2f8560e838 tools/ci: enable avr32dev1 build
removed in the tools/ci/testlist/other.dat file the entries
 -avr32dev1:nsh
 -avr32dev1:ostest

avr32_bringup.c
Fix  Error: ./avr32_bringup.c:54:4: error: #warning "Not Implemented"

comment out directive '#warning'
/* #warning "Not Implemented" */

avr_doirq.c

fix avr32/avr_doirq.c:117: error: assignment discards qualifiers from pointer target type
  regs = g_current_regs; -> regs = (uint32_t *)g_current_regs;
2024-07-12 00:39:21 +08:00
simbit18
3b2faa31e8 tools/ci/testlist: msys2.dat add qemu-v8a:nsh_smp
add build board qemu-v8a:nsh_smp 64-bit Arm Cortex-A53 with Multiple Cores
2024-05-28 16:29:06 -03:00
simbit18
391badcb24 tools/ci/testlist/macos.dat: fix path esp32c3-legacy
find: boards/risc-v/esp32c3/esp32c3-devkit/configs/cxx: No such file or directory
find: boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi: No such file or directory
2024-03-22 13:20:02 +08:00
Marco Casaroli
9af8299af5 arch/esp32 add config for qemu-openeth 2024-03-12 08:31:06 -03:00
Petro Karashchenko
9feac3b644 Revert "citest/sim01: disable sim:libcxxtest on macOS"
This reverts commit 1ecd78f5cc.
2024-02-16 10:42:23 -08:00
Yanfeng Liu
1ecd78f5cc citest/sim01: disable sim:libcxxtest on macOS
There have been errors like below on macOS for sim:libcxxtest

```
Error: /Applications/Xcode.../include/mach/vm_page_size.h:59:44:
error: expected ';' after top level declarator
```
This patch tries to disable that check on macOS.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-15 06:15:24 -08:00
simbit18
eaf1d07809 tools/ci: add initial support for MSYS2
removed uname from msys2 job
2024-01-09 05:50:09 -08:00
xuxin19
7207e5d1e9 tools/ci:enable arm64 CMake ci build
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-12-27 07:27:17 -08:00
xuxin19
1c9fab65d8 Revert "testlist: Disable sim:matter ci temporarily"
restart sim:matter ci

This reverts commit 17458c7dba.
2023-12-18 20:38:10 -08:00
Xiang Xiao
b68aa89e56 tools/ci: Upgrade riscv toolchain to v13.2.0
from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/tag/v13.2.0-2

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-17 18:25:24 +01:00
Xiang Xiao
17458c7dba testlist: Disable sim:matter ci temporarily
utils cmake build file can work with libcxx 17.0.6

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-17 03:39:26 -08:00
zhanghongyu
bc2dfe49f4 ci_sim: add matter build to the test list sim-01.dat and support cmake compilation
in order to maintain the completeness of the matter related functional code, the build of matter is added to testlist.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-12-06 07:56:17 -08:00
Xiang Xiao
a28ad5299a tools/ci: Upgrade macOS arm64 toolchain to 12.3.rel1
and enable arm64 ci build on macOS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-11-26 14:10:00 +02:00
Masayuki Ishikawa
194af23d1b Revert "tools/ci: Skip build sabre-6quad:libcxx temporarily"
This reverts commit 65e2a68e48.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-11-15 03:52:26 -08:00
xuxin19
906699e0a5 ci:enable RISC-V qemu cmake build ci
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-10-26 21:01:46 +08:00
Xiang Xiao
65e2a68e48 tools/ci: Skip build sabre-6quad:libcxx temporarily
since linker can't find basic_string::~basic_string() oddly:
arm-none-eabi-ld: /home/xiaoxiang/backup/os/nuttx/nuttx/staging/libxx.a(libcxx/src/locale.o): in function `__tcf_0':
/home/xiaoxiang/backup/os/nuttx/nuttx/libs/libxx/libcxx/src/locale.cpp:4941: undefined reference to `std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::~basic_string()'

another fix is removing the follow code from _LIBCPP_STRING_V1_EXTERN_TEMPLATE_LIST and _LIBCPP_STRING_UNSTABLE_EXTERN_TEMPLATE_LIST:
_Func(_LIBCPP_FUNC_VIS basic_string<_CharType>::~basic_string()) \

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-24 08:40:10 +03:00
raiden00pl
03b058dddc boards/stm32h7: add nucleo-h745zi 2023-08-26 03:35:32 +08:00
raiden00pl
3fd8dab991 ci: enable cmake for nucleo-f446re/systemview 2023-08-22 23:37:08 +08:00
raiden00pl
ec97cc8a31 ci: build arduino-nano-33ble and arduino-nano-33ble-rev2 with cmake 2023-08-14 20:42:59 +08:00
raiden00pl
4cba6630fb cmake: enable more stm32 builds in ci 2023-08-07 05:44:52 -07:00
raiden00pl
e48d730273 cmake: enable more cmake builds 2023-07-25 06:18:22 -07:00
chao an
06af0d47aa tools/ci: add rpproxy/rpserver into cmake build
Signed-off-by: chao an <anchao@xiaomi.com>
2023-07-25 15:00:10 +02:00
raiden00pl
26dda05cdf tools/ci: migrate some ci build configurations to CMake 2023-07-22 00:59:44 +08:00
chao an
dc6f1406d1 tools/ci: migrate some ci build configurations to CMake
Signed-off-by: chao an <anchao@xiaomi.com>
2023-07-15 23:32:36 +08:00
zhangyuan21
514e77b75e semaphore: Optimize priority inheritance with only one holder
This PR is a modification that optimizes priority inheritance
for only one holder. After the above modifications are completed,
the mutex lock->unlock process that supports priority inheritance
can be optimized by 200 cycles.

Before modify: 2000 cycle
After modify: 1742 cycle

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-06-17 08:26:46 +03:00
Fotis Panagiotopoulos
1530e04f20 ostest: Enabled KASAN, UBSAN & assertions. 2023-04-19 02:44:48 +08:00
Lucas Saavedra Vaz
1b87c86619 boards: Update and fix configs for ESP boards 2023-03-25 12:23:35 +02:00
zhangyuan21
83bbb54558 tools/ci: Don't build simusb on macOS
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-03 14:31:30 -03:00
chao an
b01b93cb54 sim/wamr: add example of WAMR(WebAssembly Micro Runtime)
Added compilation rules to support the construction of WebAssembly(WASM/WAMR):

1. Compile Toolchain
 1> Download WASI sdk and export the WASI_SDK_PATH path:

$ wget https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
$ tar xf wasi-sdk-19.0-linux.tar.gz
Put wasi-sdk-19.0 to your host WASI_SDK_PATH environment variable, like:
$ export WASI_SDK_PATH=`pwd`/wasi-sdk-19.0

 2> Download Wamr "wamrc" AOT compiler and export to the PATH:
$ mkdir wamrc
$ wget https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/wamrc-1.1.2-x86_64-ubuntu-20.04.tar.gz
$ tar xf wamrc-1.1.2-x86_64-ubuntu-20.04.tar.gz
$ export PATH=$PATH:$PWD

2. Configuring and running

 1> Configuring sim/wamr and compile:

nuttx$ ./tools/configure.sh  sim/wamr
nuttx$ make
...
Wamrc Generate AoT: /home/archer/code/nuttx/n5/apps/wasm/hello.aot
Wamrc Generate AoT: /home/archer/code/nuttx/n5/apps/wasm/coremark.aot
LD:  nuttx

 2> Copy the generated wasm file(Interpreter/AoT)

nuttx$ cp ../apps/wasm/hello.aot .
nuttx$ cp ../apps/wasm/hello.wasm .
nuttx$ cp ../apps/wasm/coremark.wasm .

 3> Run iwasm

nuttx$ ./nuttx
NuttShell (NSH) NuttX-10.4.0
nsh> iwasm /data/hello.wasm
Hello, World!!
nsh> iwasm /data/hello.aot
Hello, World!!
nsh> iwasm /data/coremark.wasm
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 12000
Total time (secs): 12.000000
Iterations/Sec   : 5.000000
Iterations       : 60
Compiler version : Clang 15.0.7
Compiler flags   : Using NuttX compilation options
Memory location  : Defined by the NuttX configuration
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0xa14c
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 5.000000 / Clang 15.0.7 Using NuttX compilation options / Defined by the NuttX configuration

Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-02 09:56:35 +01:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Xiang Xiao
916fa4d759 boards/sim: Enable CONFIG_SIM_M32 in nimble
please reference this pr:
https://github.com/apache/mynewt-nimble/pull/1125

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-09 14:36:05 +08:00
Xiang Xiao
d3525ec637 tools/ci: Enable stm32u5, stm32wb and stm32wl5
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-24 08:40:50 +09:00