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walnux/arch/xtensa
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chenxiaoyi 886718ade1 xtensa: support more than 32 cpu interrupts 
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts.  For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2025-07-04 11:26:07 -03:00
..
include xtensa: support more than 32 cpu interrupts 2025-07-04 11:26:07 -03:00
src xtensa: support more than 32 cpu interrupts 2025-07-04 11:26:07 -03:00
CMakeLists.txt cmake:implement CMake build of xtensa arch 2024-11-02 18:08:38 +08:00
Kconfig style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00