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walnux/arch/xtensa/include
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chenxiaoyi 886718ade1 xtensa: support more than 32 cpu interrupts 
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts.  For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2025-07-04 11:26:07 -03:00
..
esp32 arch/esp32_partition: read data from SPI Flash at designated 2025-03-27 02:21:04 +08:00
esp32s2 arch/xtensa: migrate to SPDX identifier 2024-12-18 17:51:57 +08:00
esp32s3 xtensa: inline up_cpu_index 2025-01-23 10:24:43 +08:00
lx6 arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
lx7 arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
xtensa arch/xtensa: Support __thread and thread_local keywords 2024-12-21 20:49:07 +08:00
.gitignore
arch.h style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00
elf.h xtensa: support coredump by register set alignment 2024-12-13 18:21:37 +08:00
inttypes.h arch/xtensa: use compiler's definition of uint32 and int32 2025-04-18 09:32:58 +08:00
irq.h xtensa: support more than 32 cpu interrupts 2025-07-04 11:26:07 -03:00
limits.h arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
loadstore.h arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
setjmp.h arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
simcall.h style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00
spinlock.h arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
stdarg.h arch/xtensa: migrate to SPDX identifier 2024-12-02 17:23:25 +08:00
syscall.h xtensa: change write intset register to syscall instruction 2024-12-27 00:25:55 +08:00
types.h arch/xtensa: use compiler's definition of uint32 and int32 2025-04-18 09:32:58 +08:00