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walnux/arch/xtensa/include
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Tiago Medicci Serrano cdeb720bf8 xtensa/esp32[|s2|s3]: Fix task backtrace dump 
- Fix `MAKE_PC_FROM_RA` macro to consider the instruction region
base address;
- Add sanity check for calculated PC and SP registers;
- Check if the stack pointer is within the interrupt stack to
enable backtrace dump if an exception occurs during the ISR;
2024-09-23 20:40:58 +08:00
..
esp32 esp32/irq: Allow IRAM ISRs to run during SPI flash operation 2023-11-10 09:11:35 +08:00
esp32s2 xtensa/esp32s2: add WiFi support on ESP32S2 2024-09-06 09:46:59 +08:00
esp32s3 esp32s3: add simple boot support 2024-04-17 19:43:05 +08:00
lx6 arch: xtensa: Author Gregory Nutt: update licenses to Apache 2021-04-02 03:14:31 -05:00
lx7 xtensa: Add initial support for ESP32-S3 2022-01-27 13:46:50 -03:00
xtensa Indent the define statement by two spaces 2023-05-21 09:52:08 -03:00
.gitignore Remove exra whitespace from files (#189) 2020-01-31 09:24:49 -06:00
arch.h xtensa/esp32s3: Disable psram as task stack 2023-11-08 16:25:57 -03:00
elf.h xtensa: Implement a few relocations 2020-03-16 07:54:49 -06:00
inttypes.h arch: Omni Hoverboards: update licenses to Apache 2021-09-28 04:37:38 -07:00
irq.h xtensa/esp32[|s2|s3]: Fix task backtrace dump 2024-09-23 20:40:58 +08:00
limits.h arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h 2022-06-03 22:25:49 +03:00
loadstore.h esp32: emulate byte access for module text 2020-03-16 07:54:49 -06:00
setjmp.h xtensa: add setjmp.h include file 2021-11-17 02:23:45 -06:00
simcall.h xtensa: Implement simcall 2020-03-12 09:03:31 -05:00
spinlock.h arch: inline up_testset in arm arm64 riscv xtensa 2024-08-21 01:45:10 +08:00
stdarg.h arch:xtensa: add arch stdarg.h include file for xtensa 2021-08-09 17:58:25 -03:00
syscall.h xtensa: Add missing input operand on sys_call6 inline ASM 2022-05-18 15:46:57 +02:00
types.h types.h: fix windows build error 2024-08-14 22:36:57 +08:00