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arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)

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Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
This commit is contained in:
Serg Podtynnyi 2025-05-22 02:38:16 +07:00 • committed by Xiang Xiao
parent d218334baa
commit 2e7f75f6e0
154 changed files with 41402 additions and 2 deletions
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1
.codespellrc
View file

@ -62,3 +62,4 @@ ignore-words-list =
tolen, tolen,
UE, UE,
WRON, WRON,
SIE,

8
Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/index.rst
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@ -191,7 +191,7 @@ Installation
$ git clone https://github.com/apache/nuttx-apps.git apps $ git clone https://github.com/apache/nuttx-apps.git apps
$ cd nuttx $ cd nuttx
$ make distclean $ make distclean
$ ./tools/configure.sh raspberrypi-pico:nsh $ ./tools/configure.sh raspberrypi-pico-2:nsh
$ make V=1 $ make V=1
5. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL. 5. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
@ -214,6 +214,12 @@ nsh
Basic NuttShell configuration (console enabled in UART0, at 115200 bps). Basic NuttShell configuration (console enabled in UART0, at 115200 bps).
usbnsh
---
Basic NuttShell configuration (console enabled via USB CDC/ACM).
smp smp
--- ---

4
Documentation/platforms/arm/rp23xx/index.rst
View file

@ -7,7 +7,9 @@ RaspberryPi rp2350
The rp2350 is a dual core chip produced by the RaspberryPi Foundation that The rp2350 is a dual core chip produced by the RaspberryPi Foundation that
is based on ARM Cortex-M33 or the Hazard3 RISC-V. is based on ARM Cortex-M33 or the Hazard3 RISC-V.
For now, only the ARM Cortex-M33 is supported. ARM Cortex-M33 and Hazard3 RISC-V cores are supported.
This is ARM Cortex-M33 version of the chip configuration.
This port is experimental and still a work in progress. Use with caution. This port is experimental and still a work in progress. Use with caution.

230
Documentation/platforms/risc-v/rp23xx-rv/boards/raspberrypi-pico-2-rv/index.rst Normal file
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@ -0,0 +1,230 @@
===============================
Raspberry Pi Pico 2 RISC-V
===============================
.. tags:: chip:rp2350
The `Raspberry Pi Pico 2 <https://www.raspberrypi.com/products/raspberry-pi-pico-2/>`_ is a general purpose board supplied by
the Raspberry Pi Foundation.
.. figure:: pico-2.png
:align: center
Features
========
* RP2350 microcontroller chip
* Dual-core Hazard3 RISC-V processor, flexible clock running up to 150 MHz
* 520kB of SRAM, and 4MB of on-board Flash memory
* Castellated module allows soldering direct to carrier boards
* USB 1.1 Host and Device support
* Low-power sleep and dormant modes
* Drag & drop programming using mass storage over USB
* 26 multi-function GPIO pins
* 2× SPI, 2× I2C, 2× UART, 3× 12-bit ADC, 16× controllable PWM channels
* Accurate clock and timer on-chip
* Temperature sensor
* Accelerated floating point libraries on-chip
* 12 × Programmable IO (PIO) state machines for custom peripheral support
Serial Console
==============
By default a serial console appears on pins 1 (TX GPIO0) and pin 2
(RX GPIO1). This console runs a 115200-8N1.
The board can be configured to use the USB connection as the serial console.
See the `usbnsh` configuration.
Buttons and LEDs
================
User LED controlled by GPIO25 and is configured as autoled by default.
A BOOTSEL button, which if held down when power is first
applied to the board, will cause the Pico 2 to boot into programming
mode and appear as a storage device to the computer connected via USB.
Saving a .UF2 file to this device will replace the Flash ROM contents
on the Pico 2.
Pin Mapping
===========
Pads numbered anticlockwise from USB connector.
===== ========== ==========
Pad Signal Notes
===== ========== ==========
1 GPIO0 Default TX for UART0 serial console
2 GPIO1 Default RX for UART1 serial console
3 Ground
4 GPIO2
5 GPIO3
6 GPIO4 Default SDA for I2C0
7 GPIO5 Default SCL for I2C0
8 Ground
9 GPIO6 Default SDA for I2C1
10 GPIO7 Default SCL for I2C1
11 GPIO8 Default RX for SPI1
12 GPIO9 Default CSn for SPI1
13 Ground
14 GPIO10 Default SCK for SPI1
15 GPIO11 Default TX for SPI1
16 GPIO12
17 GPIO13
18 Ground
19 GPIO14
20 GPIO15
21 GPIO16 Default RX for SPI0
22 GPIO17 Default CSn for SPI0
23 Ground
24 GPIO18 Default SCK for SPI0
25 GPIO19 Default TX for SPI0
26 GPIO20 Default TX for UART1 serial console
27 GPIO21 Default RX for UART1 serial console
28 Ground
29 GPIO22
30 Run
31 GPIO26 ADC0
32 GPIO27 ADC1
33 AGND Analog Ground
34 GPIO28 ADC2
35 ADC_VREF Analog reference voltage
36 3V3 Power output to peripherals
37 3V3_EN Pull to ground to turn off.
38 Ground
39 VSYS +5V Supply to board
40 VBUS Connected to USB +5V
===== ========== ==========
Other Pico 2 Pins
=================
GPIO23 Output - Power supply control.
GPIO24 Input - High if USB port or Pad 40 supplying power.
GPIO25 Output - On board LED.
ADC3 Input - Analog voltage equal to one third of VSys voltage.
Separate pins for the Serial Debug Port (SDB) are available
Power Supply
============
The Raspberry Pi Pico 2 can be powered via the USB connector,
or by supplying +5V to pin 39. The board had a diode that prevents
power from pin 39 from flowing back to the USB socket, although
the socket can be power via pin 30.
The Raspberry Pi Pico chip run on 3.3 volts. This is supplied
by an onboard voltage regulator. This regulator can be disabled
by pulling pin 37 to ground.
The regulator can run in two modes. By default the regulator runs
in PFM mode which provides the best efficiency, but may be
switched to PWM mode for improved ripple by outputting a one
on GPIO23.
Supported Capabilities
======================
NuttX supports the following Pico 2 capabilities:
* UART (console port)
* GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
* I2C
* SPI (master only)
* DMAC
* PWM
* ADC
* Watchdog
* USB device
* MSC, CDC/ACM serial and these composite device are supported.
* CDC/ACM serial device can be used for the console.
* PIO (RP2350 Programmable I/O)
* Flash ROM Boot
* SRAM Boot
* If Pico SDK is available, nuttx.uf2 file which can be used in BOOTSEL mode will be created.
* Persistent flash filesystem in unused flash ROM
There is currently no direct user mode access to these RP2350 hardware features:
* SPI Slave Mode
* SSI
* RTC
* Timers
RICS-V toolchain
================
Download and install RISC-V compatible toolchain
with arch `rv32imac` and `ilp32` abi.
https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/
Installation
============
1. Download Raspberry Pi Pico SDK
.. code-block:: console
$ git clone -b 2.1.1 https://github.com/raspberrypi/pico-sdk.git
2. Download and install picotool
Instructions can be found here: https://github.com/raspberrypi/picotool
If you are on Arch Linux, you can install the picotool through the AUR:
.. code-block:: console
$ yay -S picotool
3. Set PICO_SDK_PATH environment variable
.. code-block:: console
$ export PICO_SDK_PATH=<absolute_path_to_pico-sdk_directory>
4. Configure and build NuttX
.. code-block:: console
$ git clone https://github.com/apache/nuttx.git nuttx
$ git clone https://github.com/apache/nuttx-apps.git apps
$ cd nuttx
$ make distclean
$ ./tools/configure.sh raspberrypi-pico-2-rv:nsh
$ make V=1
5. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
The board will be detected as USB Mass Storage Device.
Then copy "nuttx.uf2" into the device.
(Same manner as the standard Pico SDK applications installation.)
6. To access the console, GPIO 0 and 1 pins must be connected to the
device such as USB-serial converter.
`usbnsh` configuration provides the console access by USB CDC/ACM serial
device. The console is available by using a terminal software on the USB
host.
Configurations
==============
nsh
---
Basic NuttShell configuration (console enabled in UART0, at 115200 bps).
usbnsh
---
Basic NuttShell configuration (console enabled via USB CDC/ACM).

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219
Documentation/platforms/risc-v/rp23xx-rv/index.rst Normal file
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@ -0,0 +1,219 @@
=========================
RaspberryPi rp2350 RISC-V
=========================
.. tags:: chip:rp2350
The rp2350 is a dual core chip produced by the RaspberryPi Foundation that
is based on ARM Cortex-M33 or the Hazard3 RISC-V.
ARM Cortex-M33 and Hazard3 RISC-V cores are supported.
This is RISC-V version of the chip configuration.
This port is experimental and still a work in progress. Use with caution.
SMP (dual core configuration not supported yet)
Peripheral Support
==================
Most drivers were copied from the rp2040 port with some modifications.
The following list indicates peripherals currently supported in NuttX:
============== ============ =====
Peripheral Status Notes
============== ============ =====
GPIO Working See Supported Boards documentation for available pins.
UART Working GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
I2C Working
SPI Master Working
SPI Slave Untested
DMAC Working
PWM Working
USB Working
PIO Working
IRQs Working
WDOG Working
DMA Working
FPU/DSP INOP Available in ARM configuration of the chip
Clock Output Untested
Flash ROM Boot Working Does not require boot2 from pico-sdk
If picotool is available a nuttx.uf2 file will be created
SRAM Boot Working Requires external SWD debugger
PSRAM Working Three modes of heap allocation described below
============== ============ =====
Installation
============
1. Download and build picotool, make it available in the PATH::
git clone https://github.com/raspberrypi/picotool.git picotool
cd picotool
mkdir build
cd build
cmake ..
make
cp picotool ~/local/bin # somewhere in your PATH
2. Download NuttX and the companion applications. These must both be
contained in the same directory::
git clone https://github.com/apache/nuttx.git nuttx
git clone https://github.com/apache/nuttx-apps.git apps
3. Download and install RISC-V compatible toolchain
with arch `rv32imac` and `ilp32` abi.
https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/
Building NuttX
==============
1. Change to NuttX directory::
cd nuttx
2. Select a configuration. The available configurations
can be listed with the command::
./tools/configure.sh -L
3. Load the selected configuration.::
make distclean
./tools/configure.sh raspberrypi-pico-2-rv:usbnsh
4. Modify the configuration as needed (optional)::
make menuconfig
5. Build NuttX::
make
Flash boot
==========
By default, the system is built to build and run from the flash
using XIP. By using the default `BOOT_RUNFROMFLASH` configuration,
the full image is run from the flash making most of the internal
SRAM available for the OS and applications, however the execution
is slower. The cache can speed up, but you might want set your
time critical functions to be placed in the SRAM (copied from
the flash on startup).
It is also possible to execute from SRAM, which reduces the
available SRAM to the OS and applications, however it is very
useful when debugging as erasing and rewriting the flash on
every build is tedious and slow. This option is enabled with
`BOOT_RUNFROMISRAM` and requires `openocd`` and/or `gdb`.
There is a third option which is to write the firmware on the
flash and it gets copied to the SRAM. This is enabled with
`CONFIG_BOOT_COPYTORAM` and might be useful for time critical
applications, on the expense of reduced usable internal SRAM
memory.
PSRAM
=====
Some boards like the `pimoroni-pico-2-plus` have a PSRAM
which greatly increases the available memory for applications.
The PSRAM is very slow compared to the internal SRAM,
so depending on the application, different configuration might
be necessary.
To use the PSRAM, enable the `RP23XX_PSRAM` and select the GPIO
pin used as CS1n with `RP23XX_PSRAM_CS1_GPIO`. See the RP2350
datasheet for more information.
The port offers three options for configuring the heaps to use
the external PSRAM, described below. More custom configurations
can be used with custom board initialization functions.
Use PSRAM and SRAM as a single main heap
----------------------------------------
This option is selected with `RP23XX_PSRAM_HEAP_SINGLE` and
requires `MM_REGIONS > 1`, as the PSRAM memory region will
be added to the heap. It is also necessary to disable
`MM_KERNEL_HEAP`, as there will only be a single heap.
This is the simplest configuration because it will unify the
memories into a single main heap. This way you can see the `free`
command output the total amount of usable RAM in the heap.
However, there are some unpredictable performance issues because
there is no control of where the memory is allocated when issuing
`malloc(3)` and `free(3)`. For this reason, you might want to
consider the other options.
Use PSRAM as user heap, SRAM as kernel heap
-------------------------------------------
This option is selected with `RP23XX_PSRAM_HEAP_USER` and
requires `MM_KERNEL_HEAP` to be set.
The external PSRAM is allocated to the default heap, while
the internal SRAM will be used for the kernel heap. This
configuration is useful because it allows drivers to
use the SRAM and behave much faster than if they used
memory on the PSRAM. While user applications can take
the bull benefit of the larger slower heap on the PSRAM.
Use PSRAM as a separate heap
----------------------------
This option is selected with `RP23XX_PSRAM_HEAP_SEPARATE` and
requires `ARCH_HAVE_EXTRA_HEAPS` to be set.
The internal SRAM is used as the main heap for kernel and
applications, as if there was no PSRAM configured. The
external PSRAM is configured as a separate user heap called
`psram` and can be used through the global variable
`g_psramheap` after including `rp23xx_heaps.h`
Programming
============
Programming using BOOTSEL
-------------------------
Connect board to USB port while holding BOOTSEL.
The board will be detected as USB Mass Storage Device.
Then copy "nuttx.uf2" into the device.
(Same manner as the standard Pico SDK applications installation.)
Programming with picotool
-------------------------
You can use picotool to load the elf (or the uf2)::
picotool load nuttx -t elf
Programming using SWD debugger
------------------------------
Most boards provide a serial (SWD) debug port.
The "nuttx" ELF file can be uploaded with an appropriate SDB programmer
module and companion software (openocd and gdb)
Running NuttX
=============
Most builds provide access to the console via UART0. To access this
GPIO 0 and 1 pins must be connected to the device such as USB-serial converter.
The `usbnsh` configuration provides the console access by USB CDC/ACM serial
device. The console is available by using a terminal software on the USB host.
Supported Boards
================
.. toctree::
:glob:
:maxdepth: 1
boards/*/*

23
arch/risc-v/Kconfig
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@ -369,6 +369,24 @@ config ARCH_CHIP_EIC7700X
---help--- ---help---
ESWIN EIC7700X SoC. ESWIN EIC7700X SoC.
config ARCH_CHIP_RP23XX_RV
bool "Raspberry Pi RP23XX RISC-V"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_RESET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ONESHOT
select ALARM_ARCH
select ARCH_HAVE_I2CRESET
select ARCH_BOARD_COMMON
---help---
Raspberry Pi RP23XX architectures (RISC-V dual Hazard3).
config ARCH_CHIP_RISCV_CUSTOM config ARCH_CHIP_RISCV_CUSTOM
bool "Custom RISC-V chip" bool "Custom RISC-V chip"
select ARCH_CHIP_CUSTOM select ARCH_CHIP_CUSTOM
@ -554,6 +572,7 @@ config ARCH_CHIP
default "k230" if ARCH_CHIP_K230 default "k230" if ARCH_CHIP_K230
default "sg2000" if ARCH_CHIP_SG2000 default "sg2000" if ARCH_CHIP_SG2000
default "eic7700x" if ARCH_CHIP_EIC7700X default "eic7700x" if ARCH_CHIP_EIC7700X
default "rp23xx-rv" if ARCH_CHIP_RP23XX_RV
config ARCH_RISCV_INTXCPT_EXTENSIONS config ARCH_RISCV_INTXCPT_EXTENSIONS
bool "RISC-V Integer Context Extensions" bool "RISC-V Integer Context Extensions"
@ -797,4 +816,8 @@ endif
if ARCH_CHIP_EIC7700X if ARCH_CHIP_EIC7700X
source "arch/risc-v/src/eic7700x/Kconfig" source "arch/risc-v/src/eic7700x/Kconfig"
endif endif
if ARCH_CHIP_RP23XX_RV
source "arch/risc-v/src/rp23xx-rv/Kconfig"
endif
endif # ARCH_RISCV endif # ARCH_RISCV

36
arch/risc-v/include/arch.h
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@ -38,6 +38,42 @@
# include <stddef.h> # include <stddef.h>
#endif #endif
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#ifdef CONFIG_PIC
#define PIC_REG x29
#define PIC_REG_STRING "x29"
#define up_getpicbase(ppicbase) \
do { \
uintptr_t picbase; \
__asm__ volatile \
( \
"mv %0, " PIC_REG_STRING \
: "=r"(picbase) \
: \
: \
); \
*(uintptr_t *)ppicbase = picbase; \
} while (0)
#define up_setpicbase(picbase) \
do { \
uintptr_t _picbase = (uintptr_t)picbase; \
__asm__ volatile \
( \
"mv " PIC_REG_STRING ", %0" \
: \
: "r"(_picbase) \
: PIC_REG_STRING \
); \
} while (0)
#endif /* CONFIG_PIC */
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/

26
arch/risc-v/include/rp23xx-rv/chip.h Normal file
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@ -0,0 +1,26 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H
#define __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H */

116
arch/risc-v/include/rp23xx-rv/i2c_slave.h Normal file
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@ -0,0 +1,116 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/i2c_slave.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H
#define __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_slave.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* There is no driver for I2C slave operations. To create an I2C slave,
* include this file (as: <arch/chip/i2c_slave.h>) and use either
* rp23xx_i2c0_slave_initialize or rp23xx_i2c1_slave_initialize to
* initialize the I2C for slave operations.
*/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2c0_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initialized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C0_SLAVE
struct i2c_slave_s *rp23xx_i2c0_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
/****************************************************************************
* Name: rp23xx_i2c1_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initialized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C1_SLAVE
struct i2c_slave_s *rp23xx_i2c1_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H */

134
arch/risc-v/include/rp23xx-rv/irq.h Normal file
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@ -0,0 +1,134 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H
#define __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#define RP23XX_IRQ_EXTINT (RISCV_IRQ_ASYNC + 32) /* Vector 48: Vector number of the first external interrupt */
/* External interrupts (vectors >= 48). These definitions are
* chip-specific
*/
#define RP23XX_TIMER0_IRQ_0 (RP23XX_IRQ_EXTINT+0)
#define RP23XX_TIMER0_IRQ_1 (RP23XX_IRQ_EXTINT+1)
#define RP23XX_TIMER0_IRQ_2 (RP23XX_IRQ_EXTINT+2)
#define RP23XX_TIMER0_IRQ_3 (RP23XX_IRQ_EXTINT+3)
#define RP23XX_TIMER1_IRQ_0 (RP23XX_IRQ_EXTINT+4)
#define RP23XX_TIMER1_IRQ_1 (RP23XX_IRQ_EXTINT+5)
#define RP23XX_TIMER1_IRQ_2 (RP23XX_IRQ_EXTINT+6)
#define RP23XX_TIMER1_IRQ_3 (RP23XX_IRQ_EXTINT+7)
#define RP23XX_RV_PWM_IRQ_WRAP_0 (RP23XX_IRQ_EXTINT+8)
#define RP23XX_RV_PWM_IRQ_WRAP_1 (RP23XX_IRQ_EXTINT+9)
#define RP23XX_DMA_IRQ_0 (RP23XX_IRQ_EXTINT+10)
#define RP23XX_DMA_IRQ_1 (RP23XX_IRQ_EXTINT+11)
#define RP23XX_DMA_IRQ_2 (RP23XX_IRQ_EXTINT+12)
#define RP23XX_DMA_IRQ_3 (RP23XX_IRQ_EXTINT+13)
#define RP23XX_USBCTRL_IRQ (RP23XX_IRQ_EXTINT+14)
#define RP23XX_PIO0_IRQ_0 (RP23XX_IRQ_EXTINT+15)
#define RP23XX_PIO0_IRQ_1 (RP23XX_IRQ_EXTINT+16)
#define RP23XX_PIO1_IRQ_0 (RP23XX_IRQ_EXTINT+17)
#define RP23XX_PIO1_IRQ_1 (RP23XX_IRQ_EXTINT+18)
#define RP23XX_PIO2_IRQ_0 (RP23XX_IRQ_EXTINT+19)
#define RP23XX_PIO2_IRQ_1 (RP23XX_IRQ_EXTINT+20)
#define RP23XX_IO_IRQ_BANK0 (RP23XX_IRQ_EXTINT+21)
#define RP23XX_IO_IRQ_BANK0_NS (RP23XX_IRQ_EXTINT+22)
#define RP23XX_IO_IRQ_QSPI (RP23XX_IRQ_EXTINT+23)
#define RP23XX_IO_IRQ_QSPI_NS (RP23XX_IRQ_EXTINT+24)
#define RP23XX_SIO_IRQ_FIFO (RP23XX_IRQ_EXTINT+25)
#define RP23XX_SIO_IRQ_BELL (RP23XX_IRQ_EXTINT+26)
#define RP23XX_SIO_IRQ_FIFO_NS (RP23XX_IRQ_EXTINT+27)
#define RP23XX_SIO_IRQ_BELL_NS (RP23XX_IRQ_EXTINT+28)
#define RP23XX_SIO_IRQ_MTIMECMP (RP23XX_IRQ_EXTINT+29)
#define RP23XX_CLOCKS_IRQ (RP23XX_IRQ_EXTINT+30)
#define RP23XX_RV_SPI0_IRQ (RP23XX_IRQ_EXTINT+31)
#define RP23XX_RV_SPI1_IRQ (RP23XX_IRQ_EXTINT+32)
#define RP23XX_RV_UART0_IRQ (RP23XX_IRQ_EXTINT+33)
#define RP23XX_RV_UART1_IRQ (RP23XX_IRQ_EXTINT+34)
#define RP23XX_RV_ADC_IRQ_FIFO (RP23XX_IRQ_EXTINT+35)
#define RP23XX_RV_I2C0_IRQ (RP23XX_IRQ_EXTINT+36)
#define RP23XX_RV_I2C1_IRQ (RP23XX_IRQ_EXTINT+37)
#define RP23XX_OTP_IRQ (RP23XX_IRQ_EXTINT+38)
#define RP23XX_TRNG_IRQ (RP23XX_IRQ_EXTINT+39)
#define RP23XX_PROC0_IRQ_CTI (RP23XX_IRQ_EXTINT+40)
#define RP23XX_PROC1_IRQ_CTI (RP23XX_IRQ_EXTINT+41)
#define RP23XX_PLL_SYS_IRQ (RP23XX_IRQ_EXTINT+42)
#define RP23XX_PLL_USB_IRQ (RP23XX_IRQ_EXTINT+43)
#define RP23XX_POWMAN_IRQ_POW (RP23XX_IRQ_EXTINT+44)
#define RP23XX_POWMAN_IRQ_TIMER (RP23XX_IRQ_EXTINT+45)
#define RP23XX_SPAREIRQ_IRQ_0 (RP23XX_IRQ_EXTINT+46)
#define RP23XX_SPAREIRQ_IRQ_1 (RP23XX_IRQ_EXTINT+47)
#define RP23XX_SPAREIRQ_IRQ_2 (RP23XX_IRQ_EXTINT+48)
#define RP23XX_SPAREIRQ_IRQ_3 (RP23XX_IRQ_EXTINT+49)
#define RP23XX_SPAREIRQ_IRQ_4 (RP23XX_IRQ_EXTINT+50)
#define RP23XX_SPAREIRQ_IRQ_5 (RP23XX_IRQ_EXTINT+51)
#define RP23XX_IRQ_NEXTINT (52)
#define RP23XX_IRQ_NIRQS (RP23XX_IRQ_EXTINT+RP23XX_IRQ_NEXTINT)
#define NR_VECTORS RP23XX_IRQ_NIRQS
#define NR_IRQS RP23XX_IRQ_NIRQS
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H */

97
arch/risc-v/include/rp23xx-rv/watchdog.h Normal file
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@ -0,0 +1,97 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/watchdog.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H
#define __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/watchdog.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IOCTL Commands ***********************************************************/
/* The watchdog driver uses a standard character driver framework. However,
* since the watchdog driver is a device control interface and not a data
* transfer interface, the majority of the functionality is implemented in
* driver ioctl calls.
*
* See nuttx/timers/watchdog.h for the IOCTLs handled by the upper half.
*
* These are detected and handled by the "lower half" watchdog timer driver.
*
* WDIOC_SET_SCRATCHn - save a 32-bit "arg" value in a scratch register
* that will be preserved over soft resets. A hard
* reset sets all scratch values to zero.
*
* WDIOC_GET_SCRATCHn - fetch a 32-bit value from a scratch register
* into a uint32_t pointed to by "arg".
*/
#define WDIOC_SET_SCRATCH0 _WDIOC(0x180)
#define WDIOC_SET_SCRATCH1 _WDIOC(0x181)
#define WDIOC_SET_SCRATCH2 _WDIOC(0x182)
#define WDIOC_SET_SCRATCH3 _WDIOC(0x183)
#define WDIOC_SET_SCRATCH4 _WDIOC(0x184)
#define WDIOC_SET_SCRATCH5 _WDIOC(0x185)
#define WDIOC_SET_SCRATCH6 _WDIOC(0x186)
#define WDIOC_SET_SCRATCH7 _WDIOC(0x187)
#define WDIOC_SET_SCRATCH(n) _WDIOC(0x180 + (n))
#define WDIOC_GET_SCRATCH0 _WDIOC(0x1f0)
#define WDIOC_GET_SCRATCH1 _WDIOC(0x1f1)
#define WDIOC_GET_SCRATCH2 _WDIOC(0x1f2)
#define WDIOC_GET_SCRATCH3 _WDIOC(0x1f3)
#define WDIOC_GET_SCRATCH4 _WDIOC(0x1f4)
#define WDIOC_GET_SCRATCH5 _WDIOC(0x1f5)
#define WDIOC_GET_SCRATCH6 _WDIOC(0x1f6)
#define WDIOC_GET_SCRATCH7 _WDIOC(0x1f7)
#define WDIOC_GET_SCRATCH(n) _WDIOC(0x1f0 + (n))
#endif /* CONFIG_WATCHDOG */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H */

7
arch/risc-v/src/common/riscv_internal.h
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@ -168,6 +168,13 @@ static inline void putreg64(uint64_t v, const volatile uintreg_t a)
#endif #endif
/* Non-atomic, but more effective modification of registers */
#define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), (a))
#define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), (a))
#define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), (a))
#define modreg64(v,m,a) putreg64((getreg64(a) & ~(m)) | ((v) & (m)), (a))
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/

816
arch/risc-v/src/rp23xx-rv/Kconfig Normal file
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@ -0,0 +1,816 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "RP23XX Configuration Options"
config RP23XX_RV_RP2350B
bool "Use RP2350B variant (QFN-80)"
default n
config RP23XX_RV_DMAC
bool "DMAC support"
default y
select ARCH_DMA
#####################################################################
# UART Configuration
#####################################################################
config RP23XX_RV_UART0
bool "UART0"
default y
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Most UART parameters are configured here. See also the
Board Selection menu to configure the pins used by UART0
if RP23XX_RV_UART0
config RP23XX_RV_UART0_BAUD
int "RP23XX UART0 BAUD"
default 115200
---help---
RP23XX UART0 communication bit rate. The range of available
baud rates depend on the clock supplied to the UART. Given
the normally configured 125 MHz clock, the baud
rates between 120 and 7 812 500 baud are available.
config RP23XX_RV_UART0_PARITY
int "RP23XX UART0 parity"
default 0
range 0 2
---help---
RP23XX UART0 parity. 0=None, 1=Odd, 2=Even. Default: None
config RP23XX_RV_UART0_BITS
int "RP23XX UART0 number of bits"
default 8
range 5 8
---help---
RP23XX UART0 number of bits. Default: 8
config RP23XX_RV_UART0_2STOP
int "RP23XX UART0 two stop bits"
default 0
---help---
0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
endif # RP23XX_RV_UART0
config RP23XX_RV_UART1
bool "UART1"
default n
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
---help---
Most UART parameters are configured here. See also the
Board Selection menu to configure the pins used by UART1
if RP23XX_RV_UART1
config RP23XX_RV_UART1_BAUD
int "RP23XX UART1 BAUD"
default 115200
---help---
RP23XX UART0 communication bit rate. The range of available
baud rates depend on the clock supplied to the UART. Given
the normally configured 125 MHz clock, the baud
rates between 120 and 7 812 500 baud are available.
config RP23XX_RV_UART1_PARITY
int "RP23XX UART1 parity"
default 0
range 0 2
---help---
RP23XX UART1 parity. 0=None, 1=Odd, 2=Even. Default: None
config RP23XX_RV_UART1_BITS
int "RP23XX UART1 number of bits"
default 8
range 5 8
---help---
RP23XX UART1 number of bits. Default: 8
config RP23XX_RV_UART1_2STOP
int "RP23XX UART1 two stop bits"
default 0
---help---
0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
endif # RP23XX_RV_UART1
#####################################################################
# SPI Configuration
#####################################################################
config RP23XX_RV_SPI
bool "SPI Master Mode Support"
select SPI
if RP23XX_RV_SPI
config RP23XX_RV_SPI0
bool "SPI0"
default n
---help---
Most SPI parameters are configured here. See also the
Board Selection menu to configure the pins used by SPI0
config RP23XX_RV_SPI1
bool "SPI1"
default n
---help---
Most SPI parameters are configured here. See also the
Board Selection menu to configure the pins used by SPI1
config RP23XX_RV_SPI_DMA
bool "SPI DMA"
default y
depends on RP23XX_RV_DMAC
---help---
Use DMA to improve SPI transfer performance.
config RP23XX_RV_SPI_DMATHRESHOLD
int "SPI DMA threshold"
default 4
depends on RP23XX_RV_SPI_DMA
---help---
When SPI DMA is enabled, small DMA transfers will still be performed
by polling logic. But we need a threshold value to determine what
is small. That value is provided by RP23XX_RV_SPI_DMATHRESHOLD.
config RP23XX_RV_SPI_DRIVER
bool "SPI character driver"
default y
select SPI_DRIVER
---help---
Build in support for a character driver at /dev/spi[N] that may be
used to perform SPI bus transfers from applications. The intent of
this driver is to support SPI testing.
endif # RP23XX_RV_SPI
#####################################################################
# I2C Configuration (Master)
#####################################################################
config RP23XX_RV_I2C
bool "I2C Master"
select I2C
---help---
Build in support for I2C master mode.
Note: Do not configure the same port as both master and slave.
if RP23XX_RV_I2C
config RP23XX_RV_I2C0
bool "I2C0"
default n
---help---
See the Board Selection menu to configure the pins used by I2C0.
config RP23XX_RV_I2C1
bool "I2C1"
default n
---help---
See the Board Selection menu to configure the pins used by I2C1.
config RP23XX_RV_I2C_DRIVER
bool "I2C character driver"
default n
select I2C_DRIVER
---help---
Build in support for a character driver at /dev/i2c[N] that may be
used to perform I2C bus transfers from applications. The intent of
this driver is to support I2C testing. It is not suitable for use
in any real driver application.
endif # RP23XX_RV_I2C
#####################################################################
# I2C Configuration (Slave)
#####################################################################
config RP23XX_RV_I2C_SLAVE
bool "I2C Slave"
select I2C_SLAVE
---help---
Build in support for I2C slave mode.
Note: Do not configure the same port as both master and slave.
if RP23XX_RV_I2C_SLAVE
config RP23XX_RV_I2C0_SLAVE
bool "I2C0"
default n
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_I2C0_SLAVE
config RP23XX_RV_I2C0_SLAVE_ADDRESS
int "Slave Address (in decimal)"
default 42
---help---
This is the default address of this device on the I2C bus.
It should be the canonical address (not the shifted address)
in the range 8-119 for 7-bit mode and in the range 0-1023
for 10-bit mode.
config RP23XX_RV_I2C0_SLAVE_10BIT
bool "Enable 10-bit slave address"
default n
---help---
Set to enable 10-bit mode addressing.
endif # RP23XX_RV_I2C0_SLAVE
config RP23XX_RV_I2C1_SLAVE
bool "I2C1"
default n
---help---
See the Board Selection menu to configure the pins used by I2C1.
if RP23XX_RV_I2C1_SLAVE
config RP23XX_RV_I2C1_SLAVE_ADDRESS
int "Slave Address (in decimal)"
default 42
---help---
This is the default address of this device on the I2C bus.
It should be the canonical address (not the shifted address)
in the range 8-119 for 7-bit mode and in the range 0-1023
for 10-bit mode.
config RP23XX_RV_I2C1_SLAVE_10BIT
bool "Enable 10-bit slave address"
default n
---help---
Set to enable 10-bit mode addressing.
endif # RP23XX_RV_I2C1_SLAVE
endif # RP23XX_RV_I2C_SLAVE
#####################################################################
# PWM Configuration
#####################################################################
config RP23XX_RV_PWM
bool "PWM"
select PWM
---help---
After enabling PWM support here, configure the GPIO pins to use
under the Board Selection menu.
if RP23XX_RV_PWM
config RP23XX_RV_PWM_MULTICHAN
bool "Support RP23XX Multi-Channel PWM"
default y
---help---
If support for multi-channel PWM is disabled, the generated code
will only support the A channel of the PWM slices.
if RP23XX_RV_PWM_MULTICHAN
config RP23XX_RV_PWM_NCHANNELS
int "Number of channels"
default 2
range 1 2
---help---
If the number of channels is set to 1, the generated code will
only support the A channel of the PWM slices. This is functionally
identical to disabling multi-channel PWM support.
endif # RP23XX_RV_PWM_MULTICHAN
config RP23XX_RV_PWM0
bool "PWM0"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM0
config RP23XX_RV_PWM0A_INVERT
bool "PWM0 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM0B_INVERT
bool "PWM0 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM0_PHASE_CORRECT
bool "PWM0 phase correct"
default n
endif # RP23XX_RV_PWM0
config RP23XX_RV_PWM1
bool "PWM1"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM1
config RP23XX_RV_PWM1A_INVERT
bool "PWM1 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM1B_INVERT
bool "PWM1 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM1_PHASE_CORRECT
bool "PWM1 phase correct"
default n
endif # RP23XX_RV_PWM1
config RP23XX_RV_PWM2
bool "PWM2"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM2
config RP23XX_RV_PWM2A_INVERT
bool "PWM2 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM2B_INVERT
bool "PWM2 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM2_PHASE_CORRECT
bool "PWM2 phase correct"
default n
endif # RP23XX_RV_PWM2
config RP23XX_RV_PWM3
bool "PWM3"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM3
config RP23XX_RV_PWM3A_INVERT
bool "PWM3 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM3B_INVERT
bool "PWM3 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM3_PHASE_CORRECT
bool "PWM3 phase correct"
default n
endif # RP23XX_RV_PWM3
config RP23XX_RV_PWM4
bool "PWM4"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM4
config RP23XX_RV_PWM4A_INVERT
bool "PWM4 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM4B_INVERT
bool "PWM4 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM4_PHASE_CORRECT
bool "PWM4 phase correct"
default n
endif # RP23XX_RV_PWM4
config RP23XX_RV_PWM5
bool "PWM5"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM5
config RP23XX_RV_PWM5A_INVERT
bool "PWM5 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM5B_INVERT
bool "PWM5 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM5_PHASE_CORRECT
bool "PWM5 phase correct"
default n
endif # RP23XX_RV_PWM5
config RP23XX_RV_PWM6
bool "PWM6"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM6
config RP23XX_RV_PWM6A_INVERT
bool "PWM6 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM6B_INVERT
bool "PWM6 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM6_PHASE_CORRECT
bool "PWM6 phase correct"
default n
endif # RP23XX_RV_PWM6
config RP23XX_RV_PWM7
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM7
config RP23XX_RV_PWM7A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM7B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM7_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_RV_PWM7
config RP23XX_RV_PWM8
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM8
config RP23XX_RV_PWM8A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM8B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM8_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_RV_PWM8
config RP23XX_RV_PWM9
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM9
config RP23XX_RV_PWM9A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM9B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM9_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_RV_PWM9
config RP23XX_RV_PWM10
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM10
config RP23XX_RV_PWM10A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM10B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM10_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_RV_PWM10
config RP23XX_RV_PWM11
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_RV_PWM11
config RP23XX_RV_PWM11A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM11B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_RV_PWM_MULTICHAN && RP23XX_RV_PWM_NCHANNELS > 1
config RP23XX_RV_PWM11_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_RV_PWM11
endif # RP23XX_RV_PWM
#####################################################################
# I2S Configuration
#####################################################################
config RP23XX_RV_I2S
bool "I2S"
select I2S
---help---
See the Board Selection menu to configure the pins used by I2S.
if RP23XX_RV_I2S
config RP23XX_RV_I2S_MAXINFLIGHT
int "I2S queue size"
default 16
---help---
This is the total number of transfers that can be enqueue before
the caller is required to wait. This setting determines the number
certain queue data structures that will be pre-allocated.
config RP23XX_RV_I2S_DATALEN
int "Data width (bits)"
default 16
---help---
Data width in bits. This is a default value and may be change
via the I2S interface
config RP23XX_RV_I2S_PIO
int "RP23XX PIO number used for I2S (0-1)"
default 0
range 0 1
config RP23XX_RV_I2S_PIO_SM
int "RP23XX PIO state machine number used for I2S (0-3)"
default 0
range 0 3
endif # RP23XX_RV_I2S
#####################################################################
# SPISD Configuration
#####################################################################
config RP23XX_RV_SPISD
bool "SPI SD Card"
default n
select MMCSD_SPI
if RP23XX_RV_SPISD
config RP23XX_RV_SPISD_SLOT_NO
int "SPI SD Card Slot Number"
default 0
---help---
Select spi sd card slot number.
config RP23XX_RV_SPISD_SPI_CH
int "SPI channel number"
default 0
range 0 1
---help---
Select spi channel number to use spi sd card.
endif # SPISD Configuration
#####################################################################
# ADC Configuration
#####################################################################
config RP23XX_RV_ADC
bool "Enable ADC Support"
default n
---help---
If y, the RP23XX ADC code will be built.
If the ADC device driver is not built, basic functions
to programmatically access the ADC ports will be added.
if RP23XX_RV_ADC
if ADC
config RP23XX_RV_ADC_CHANNEL0
bool "Read ADC channel 0"
default n
---help---
If y, then ADC0 will be read.
config RP23XX_RV_ADC_CHANNEL1
bool "Read ADC channel 1"
default n
---help---
If y, then ADC1 will be read.
config RP23XX_RV_ADC_CHANNEL2
bool "Read ADC channel 2"
default n
---help---
If y, then ADC2 will be read.
config RP23XX_RV_ADC_CHANNEL3
bool "Read ADC channel 3"
default n
---help---
If y, then ADC3 will be read.
config RP23XX_RV_ADC_CHANNEL4
bool "Read ADC channel 4"
default n
---help---
If y, then ADC4 will be read.
config RP23XX_RV_ADC_CHANNEL5
bool "Read ADC channel 5"
default n
---help---
If y, then ADC5 will be read.
config RP23XX_RV_ADC_CHANNEL6
bool "Read ADC channel 6"
default n
---help---
If y, then ADC6 will be read.
config RP23XX_RV_ADC_CHANNEL7
bool "Read ADC channel 7"
default n
---help---
If y, then ADC7 will be read.
config RP23XX_RV_ADC_TEMPERATURE
bool "Read ADC chip temperature channel"
default n
---help---
If y, then the ADC chip temperature
will be read.
endif # ADC
endif # RP23XX_RV_ADC
#####################################################################
# WS2812 Configuration
#####################################################################
config RP23XX_RV_BOARD_HAS_WS2812
bool "Has ws2812 pixels"
default n
depends on WS2812
select WS2812_NON_SPI_DRIVER
---help---
See the Board Selection menu to configure the pins used
by ws2812.

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############################################################################
# arch/risc-v/src/rp23xx-rv/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include common/Make.defs
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = rp23xx_head.S
CFLAGS += -Wno-array-bounds
CHIP_CSRCS += rp23xx_idle.c
CHIP_CSRCS += rp23xx_irq.c
CHIP_CSRCS += rp23xx_irq_dispatch.c
CHIP_CSRCS += rp23xx_uart.c
CHIP_CSRCS += rp23xx_serial.c
CHIP_CSRCS += rp23xx_start.c
CHIP_CSRCS += rp23xx_timerisr.c
CHIP_CSRCS += rp23xx_gpio.c
CHIP_CSRCS += rp23xx_pio.c
CHIP_CSRCS += rp23xx_clock.c
CHIP_CSRCS += rp23xx_xosc.c
CHIP_CSRCS += rp23xx_pll.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp23xx_cpustart.c
CHIP_CSRCS += rp23xx_smpcall.c
CHIP_CSRCS += rp23xx_cpuidlestack.c
endif
ifeq ($(CONFIG_RP23XX_RV_DMAC),y)
CHIP_CSRCS += rp23xx_dmac.c
endif
ifeq ($(CONFIG_RP23XX_RV_SPI),y)
CHIP_CSRCS += rp23xx_spi.c
endif
ifeq ($(CONFIG_RP23XX_RV_PWM),y)
CHIP_CSRCS += rp23xx_pwm.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2C),y)
CHIP_CSRCS += rp23xx_i2c.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2C_SLAVE),y)
CHIP_CSRCS += rp23xx_i2c_slave.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2S),y)
CHIP_CSRCS += rp23xx_i2s.c
CHIP_CSRCS += rp23xx_i2s_pio.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += rp23xx_usbdev.c
endif
ifeq ($(CONFIG_WS2812),y)
CHIP_CSRCS += rp23xx_ws2812.c
endif
ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += rp23xx_adc.c
endif
ifeq ($(CONFIG_WATCHDOG),y)
CHIP_CSRCS += rp23xx_wdt.c
endif

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arch/risc-v/src/rp23xx-rv/chip.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H
#define __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <nuttx/arch.h>
#endif
/* Include the chip capabilities file */
#include <arch/rp23xx-rv/chip.h>
/****************************************************************************
* Macro Definitions
****************************************************************************/
#ifdef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_accessctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_ACCESSCTRL_LOCK_OFFSET 0x00000000
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_OFFSET 0x00000004
#define RP23XX_ACCESSCTRL_CFGRESET_OFFSET 0x00000008
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0_OFFSET 0x0000000c
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_OFFSET 0x00000010
#define RP23XX_ACCESSCTRL_ROM_OFFSET 0x00000014
#define RP23XX_ACCESSCTRL_XIP_MAIN_OFFSET 0x00000018
#define RP23XX_ACCESSCTRL_SRAM0_OFFSET 0x0000001c
#define RP23XX_ACCESSCTRL_SRAM1_OFFSET 0x00000020
#define RP23XX_ACCESSCTRL_SRAM2_OFFSET 0x00000024
#define RP23XX_ACCESSCTRL_SRAM3_OFFSET 0x00000028
#define RP23XX_ACCESSCTRL_SRAM4_OFFSET 0x0000002c
#define RP23XX_ACCESSCTRL_SRAM5_OFFSET 0x00000030
#define RP23XX_ACCESSCTRL_SRAM6_OFFSET 0x00000034
#define RP23XX_ACCESSCTRL_SRAM7_OFFSET 0x00000038
#define RP23XX_ACCESSCTRL_SRAM8_OFFSET 0x0000003c
#define RP23XX_ACCESSCTRL_SRAM9_OFFSET 0x00000040
#define RP23XX_ACCESSCTRL_DMA_OFFSET 0x00000044
#define RP23XX_ACCESSCTRL_USBCTRL_OFFSET 0x00000048
#define RP23XX_ACCESSCTRL_PIO0_OFFSET 0x0000004c
#define RP23XX_ACCESSCTRL_PIO1_OFFSET 0x00000050
#define RP23XX_ACCESSCTRL_PIO2_OFFSET 0x00000054
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_OFFSET 0x00000058
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_OFFSET 0x0000005c
#define RP23XX_ACCESSCTRL_SYSINFO_OFFSET 0x00000060
#define RP23XX_ACCESSCTRL_RESETS_OFFSET 0x00000064
#define RP23XX_ACCESSCTRL_IO_BANK0_OFFSET 0x00000068
#define RP23XX_ACCESSCTRL_IO_BANK1_OFFSET 0x0000006c
#define RP23XX_ACCESSCTRL_PADS_BANK0_OFFSET 0x00000070
#define RP23XX_ACCESSCTRL_PADS_QSPI_OFFSET 0x00000074
#define RP23XX_ACCESSCTRL_BUSCTRL_OFFSET 0x00000078
#define RP23XX_ACCESSCTRL_ADC0_OFFSET 0x0000007c
#define RP23XX_ACCESSCTRL_HSTX_OFFSET 0x00000080
#define RP23XX_ACCESSCTRL_I2C0_OFFSET 0x00000084
#define RP23XX_ACCESSCTRL_I2C1_OFFSET 0x00000088
#define RP23XX_ACCESSCTRL_PWM_OFFSET 0x0000008c
#define RP23XX_ACCESSCTRL_SPI0_OFFSET 0x00000090
#define RP23XX_ACCESSCTRL_SPI1_OFFSET 0x00000094
#define RP23XX_ACCESSCTRL_TIMER0_OFFSET 0x00000098
#define RP23XX_ACCESSCTRL_TIMER1_OFFSET 0x0000009c
#define RP23XX_ACCESSCTRL_UART0_OFFSET 0x000000a0
#define RP23XX_ACCESSCTRL_UART1_OFFSET 0x000000a4
#define RP23XX_ACCESSCTRL_OTP_OFFSET 0x000000a8
#define RP23XX_ACCESSCTRL_TBMAN_OFFSET 0x000000ac
#define RP23XX_ACCESSCTRL_POWMAN_OFFSET 0x000000b0
#define RP23XX_ACCESSCTRL_TRNG_OFFSET 0x000000b4
#define RP23XX_ACCESSCTRL_SHA256_OFFSET 0x000000b8
#define RP23XX_ACCESSCTRL_SYSCFG_OFFSET 0x000000bc
#define RP23XX_ACCESSCTRL_CLOCKS_OFFSET 0x000000c0
#define RP23XX_ACCESSCTRL_XOSC_OFFSET 0x000000c4
#define RP23XX_ACCESSCTRL_ROSC_OFFSET 0x000000c8
#define RP23XX_ACCESSCTRL_PLL_SYS_OFFSET 0x000000cc
#define RP23XX_ACCESSCTRL_PLL_USB_OFFSET 0x000000d0
#define RP23XX_ACCESSCTRL_TICKS_OFFSET 0x000000d4
#define RP23XX_ACCESSCTRL_WATCHDOG_OFFSET 0x000000d8
#define RP23XX_ACCESSCTRL_RSM_OFFSET 0x000000dc
#define RP23XX_ACCESSCTRL_XIP_CTRL_OFFSET 0x000000e0
#define RP23XX_ACCESSCTRL_XIP_QMI_OFFSET 0x000000e4
#define RP23XX_ACCESSCTRL_XIP_AUX_OFFSET 0x000000e8
/* Register definitions *****************************************************/
#define RP23XX_ACCESSCTRL_LOCK (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_LOCK_OFFSET)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_FORCE_CORE_NS_OFFSET)
#define RP23XX_ACCESSCTRL_CFGRESET (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CFGRESET_OFFSET)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_GPIO_NSMASK0_OFFSET)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_GPIO_NSMASK1_OFFSET)
#define RP23XX_ACCESSCTRL_ROM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ROM_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_MAIN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_MAIN_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM0_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM1_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM2 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM2_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM3 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM3_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM4 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM4_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM5 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM5_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM6 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM6_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM7 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM7_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM8 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM8_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM9 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM9_OFFSET)
#define RP23XX_ACCESSCTRL_DMA (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_DMA_OFFSET)
#define RP23XX_ACCESSCTRL_USBCTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_USBCTRL_OFFSET)
#define RP23XX_ACCESSCTRL_PIO0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO0_OFFSET)
#define RP23XX_ACCESSCTRL_PIO1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO1_OFFSET)
#define RP23XX_ACCESSCTRL_PIO2 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO2_OFFSET)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CORESIGHT_TRACE_OFFSET)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_OFFSET)
#define RP23XX_ACCESSCTRL_SYSINFO (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SYSINFO_OFFSET)
#define RP23XX_ACCESSCTRL_RESETS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_RESETS_OFFSET)
#define RP23XX_ACCESSCTRL_IO_BANK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_IO_BANK0_OFFSET)
#define RP23XX_ACCESSCTRL_IO_BANK1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_IO_BANK1_OFFSET)
#define RP23XX_ACCESSCTRL_PADS_BANK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PADS_BANK0_OFFSET)
#define RP23XX_ACCESSCTRL_PADS_QSPI (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PADS_QSPI_OFFSET)
#define RP23XX_ACCESSCTRL_BUSCTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_BUSCTRL_OFFSET)
#define RP23XX_ACCESSCTRL_ADC0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ADC0_OFFSET)
#define RP23XX_ACCESSCTRL_HSTX (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_HSTX_OFFSET)
#define RP23XX_ACCESSCTRL_I2C0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_I2C0_OFFSET)
#define RP23XX_ACCESSCTRL_I2C1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_I2C1_OFFSET)
#define RP23XX_ACCESSCTRL_PWM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PWM_OFFSET)
#define RP23XX_ACCESSCTRL_SPI0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SPI0_OFFSET)
#define RP23XX_ACCESSCTRL_SPI1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SPI1_OFFSET)
#define RP23XX_ACCESSCTRL_TIMER0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TIMER0_OFFSET)
#define RP23XX_ACCESSCTRL_TIMER1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TIMER1_OFFSET)
#define RP23XX_ACCESSCTRL_UART0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_UART0_OFFSET)
#define RP23XX_ACCESSCTRL_UART1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_UART1_OFFSET)
#define RP23XX_ACCESSCTRL_OTP (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_OTP_OFFSET)
#define RP23XX_ACCESSCTRL_TBMAN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TBMAN_OFFSET)
#define RP23XX_ACCESSCTRL_POWMAN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_POWMAN_OFFSET)
#define RP23XX_ACCESSCTRL_TRNG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TRNG_OFFSET)
#define RP23XX_ACCESSCTRL_SHA256 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SHA256_OFFSET)
#define RP23XX_ACCESSCTRL_SYSCFG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SYSCFG_OFFSET)
#define RP23XX_ACCESSCTRL_CLOCKS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CLOCKS_OFFSET)
#define RP23XX_ACCESSCTRL_XOSC (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XOSC_OFFSET)
#define RP23XX_ACCESSCTRL_ROSC (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ROSC_OFFSET)
#define RP23XX_ACCESSCTRL_PLL_SYS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PLL_SYS_OFFSET)
#define RP23XX_ACCESSCTRL_PLL_USB (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PLL_USB_OFFSET)
#define RP23XX_ACCESSCTRL_TICKS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TICKS_OFFSET)
#define RP23XX_ACCESSCTRL_WATCHDOG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_WATCHDOG_OFFSET)
#define RP23XX_ACCESSCTRL_RSM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_RSM_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_CTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_CTRL_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_QMI (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_QMI_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_AUX (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_AUX_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_ACCESSCTRL_LOCK_MASK (0x0000000f)
#define RP23XX_ACCESSCTRL_LOCK_DEBUG_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_LOCK_DMA_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_LOCK_CORE1_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_LOCK_CORE0_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_CORE1_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CFGRESET_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0_MASK (0xffffffff)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_MASK (0xff00ffff)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_MASK (0xf0000000)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_MASK (1 << 27)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_MASK (1 << 26)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_USB_DM_MASK (1 << 25)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_USB_DP_MASK (1 << 24)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_GPIO_MASK (0x0000ffff)
#define RP23XX_ACCESSCTRL_ROM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ROM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ROM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ROM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ROM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ROM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ROM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ROM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ROM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_MAIN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_MAIN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_MAIN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_MAIN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_MAIN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_MAIN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_MAIN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_MAIN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_MAIN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM2_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM2_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM2_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM2_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM2_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM2_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM2_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM2_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM2_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM3_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM3_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM3_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM3_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM3_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM3_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM3_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM3_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM3_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM4_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM4_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM4_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM4_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM4_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM4_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM4_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM4_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM4_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM5_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM5_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM5_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM5_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM5_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM5_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM5_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM5_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM5_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM6_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM6_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM6_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM6_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM6_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM6_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM6_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM6_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM6_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM7_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM7_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM7_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM7_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM7_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM7_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM7_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM7_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM7_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM8_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM8_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM8_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM8_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM8_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM8_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM8_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM8_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM8_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM9_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM9_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM9_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM9_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM9_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM9_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM9_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM9_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM9_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_DMA_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_DMA_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_DMA_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_DMA_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_DMA_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_DMA_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_DMA_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_DMA_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_DMA_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_USBCTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_USBCTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_USBCTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_USBCTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_USBCTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_USBCTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_USBCTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_USBCTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_USBCTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO2_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO2_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO2_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO2_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO2_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO2_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO2_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO2_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO2_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SYSINFO_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SYSINFO_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SYSINFO_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SYSINFO_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SYSINFO_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SYSINFO_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SYSINFO_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SYSINFO_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SYSINFO_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_RESETS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_RESETS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_RESETS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_RESETS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_RESETS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_RESETS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_RESETS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_RESETS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_RESETS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_IO_BANK0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_IO_BANK0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_IO_BANK0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_IO_BANK0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_IO_BANK0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_IO_BANK0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_IO_BANK0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_IO_BANK0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_IO_BANK0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_IO_BANK1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_IO_BANK1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_IO_BANK1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_IO_BANK1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_IO_BANK1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_IO_BANK1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_IO_BANK1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_IO_BANK1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_IO_BANK1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PADS_BANK0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PADS_BANK0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PADS_BANK0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PADS_BANK0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PADS_BANK0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PADS_BANK0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PADS_BANK0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PADS_BANK0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PADS_BANK0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PADS_QSPI_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PADS_QSPI_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PADS_QSPI_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PADS_QSPI_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PADS_QSPI_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PADS_QSPI_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PADS_QSPI_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PADS_QSPI_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PADS_QSPI_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_BUSCTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_BUSCTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_BUSCTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_BUSCTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_BUSCTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_BUSCTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_BUSCTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_BUSCTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_BUSCTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_ADC0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ADC0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ADC0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ADC0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ADC0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ADC0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ADC0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ADC0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ADC0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_HSTX_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_HSTX_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_HSTX_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_HSTX_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_HSTX_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_HSTX_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_HSTX_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_HSTX_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_HSTX_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_I2C0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_I2C0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_I2C0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_I2C0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_I2C0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_I2C0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_I2C0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_I2C0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_I2C0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_I2C1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_I2C1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_I2C1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_I2C1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_I2C1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_I2C1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_I2C1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_I2C1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_I2C1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PWM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PWM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PWM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PWM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PWM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PWM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PWM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PWM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PWM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SPI0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SPI0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SPI0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SPI0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SPI0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SPI0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SPI0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SPI0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SPI0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SPI1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SPI1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SPI1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SPI1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SPI1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SPI1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SPI1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SPI1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SPI1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TIMER0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TIMER0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TIMER0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TIMER0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TIMER0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TIMER0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TIMER0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TIMER0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TIMER0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TIMER1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TIMER1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TIMER1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TIMER1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TIMER1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TIMER1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TIMER1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TIMER1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TIMER1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_UART0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_UART0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_UART0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_UART0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_UART0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_UART0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_UART0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_UART0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_UART0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_UART1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_UART1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_UART1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_UART1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_UART1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_UART1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_UART1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_UART1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_UART1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_OTP_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_OTP_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_OTP_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_OTP_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_OTP_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_OTP_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_OTP_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_OTP_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_OTP_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TBMAN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TBMAN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TBMAN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TBMAN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TBMAN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TBMAN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TBMAN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TBMAN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TBMAN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_POWMAN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_POWMAN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_POWMAN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_POWMAN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_POWMAN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_POWMAN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_POWMAN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_POWMAN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_POWMAN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TRNG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TRNG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TRNG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TRNG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TRNG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TRNG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TRNG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TRNG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TRNG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SHA256_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SHA256_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SHA256_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SHA256_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SHA256_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SHA256_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SHA256_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SHA256_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SHA256_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SYSCFG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SYSCFG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SYSCFG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SYSCFG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SYSCFG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SYSCFG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SYSCFG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SYSCFG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SYSCFG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CLOCKS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CLOCKS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CLOCKS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CLOCKS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CLOCKS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CLOCKS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CLOCKS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CLOCKS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CLOCKS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XOSC_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XOSC_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XOSC_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XOSC_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XOSC_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XOSC_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XOSC_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XOSC_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XOSC_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_ROSC_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ROSC_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ROSC_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ROSC_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ROSC_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ROSC_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ROSC_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ROSC_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ROSC_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PLL_SYS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PLL_SYS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PLL_SYS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PLL_SYS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PLL_SYS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PLL_SYS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PLL_SYS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PLL_SYS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PLL_SYS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PLL_USB_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PLL_USB_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PLL_USB_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PLL_USB_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PLL_USB_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PLL_USB_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PLL_USB_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PLL_USB_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PLL_USB_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TICKS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TICKS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TICKS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TICKS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TICKS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TICKS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TICKS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TICKS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TICKS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_WATCHDOG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_WATCHDOG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_WATCHDOG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_WATCHDOG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_WATCHDOG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_WATCHDOG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_WATCHDOG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_WATCHDOG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_WATCHDOG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_RSM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_RSM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_RSM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_RSM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_RSM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_RSM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_RSM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_RSM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_RSM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_CTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_CTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_CTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_CTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_CTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_CTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_CTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_CTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_CTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_QMI_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_QMI_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_QMI_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_QMI_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_QMI_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_QMI_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_QMI_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_QMI_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_QMI_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_AUX_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_AUX_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_AUX_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_AUX_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_AUX_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_AUX_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_AUX_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_AUX_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_AUX_NSU_MASK (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_adc.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_adc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_ADC_CS_OFFSET 0x00000000
#define RP23XX_RV_ADC_RESULT_OFFSET 0x00000004
#define RP23XX_RV_ADC_FCS_OFFSET 0x00000008
#define RP23XX_RV_ADC_FIFO_OFFSET 0x0000000c
#define RP23XX_RV_ADC_DIV_OFFSET 0x00000010
#define RP23XX_RV_ADC_INTR_OFFSET 0x00000014
#define RP23XX_RV_ADC_INTE_OFFSET 0x00000018
#define RP23XX_RV_ADC_INTF_OFFSET 0x0000001c
#define RP23XX_RV_ADC_INTS_OFFSET 0x00000020
/* Register definitions *****************************************************/
#define RP23XX_RV_ADC_CS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_CS_OFFSET)
#define RP23XX_RV_ADC_RESULT (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_RESULT_OFFSET)
#define RP23XX_RV_ADC_FCS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_FCS_OFFSET)
#define RP23XX_RV_ADC_FIFO (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_FIFO_OFFSET)
#define RP23XX_RV_ADC_DIV (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_DIV_OFFSET)
#define RP23XX_RV_ADC_INTR (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTR_OFFSET)
#define RP23XX_RV_ADC_INTE (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTE_OFFSET)
#define RP23XX_RV_ADC_INTF (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTF_OFFSET)
#define RP23XX_RV_ADC_INTS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_ADC_CS_MASK (0x01fff70f)
#define RP23XX_RV_ADC_CS_RROBIN_SHIFT (16)
#define RP23XX_RV_ADC_CS_RROBIN_MASK (0x01ff << RP23XX_RV_ADC_CS_RROBIN_SHIFT)
#define RP23XX_RV_ADC_CS_AINSEL_SHIFT (12)
#define RP23XX_RV_ADC_CS_AINSEL_MASK (0x000fl << RP23XX_RV_ADC_CS_AINSEL_SHIFT)
#define RP23XX_RV_ADC_CS_ERR_STICKY (1 << 10)
#define RP23XX_RV_ADC_CS_ERR (1 << 9)
#define RP23XX_RV_ADC_CS_READY (1 << 8)
#define RP23XX_RV_ADC_CS_START_MANY (1 << 3)
#define RP23XX_RV_ADC_CS_START_ONCE (1 << 2)
#define RP23XX_RV_ADC_CS_TS_EN (1 << 1)
#define RP23XX_RV_ADC_CS_EN (1 << 0)
#define RP23XX_RV_ADC_RESULT_MASK (0x00000fff)
#define RP23XX_RV_ADC_FCS_MASK (0x0f0f0f0f)
#define RP23XX_RV_ADC_FCS_THRESH_SHIFT (24)
#define RP23XX_RV_ADC_FCS_THRESH_MASK (0x000fl << RP23XX_RV_ADC_FCS_THRESH_SHIFT)
#define RP23XX_RV_ADC_FCS_LEVEL_SHIFT (16)
#define RP23XX_RV_ADC_FCS_LEVEL_MASK (0x000f << RP23XX_RV_ADC_FCS_LEVEL_SHIFT)
#define RP23XX_RV_ADC_FCS_OVER (1 << 11)
#define RP23XX_RV_ADC_FCS_UNDER (1 << 10)
#define RP23XX_RV_ADC_FCS_FULL (1 << 9)
#define RP23XX_RV_ADC_FCS_EMPTY (1 << 8)
#define RP23XX_RV_ADC_FCS_DREQ_EN (1 << 3)
#define RP23XX_RV_ADC_FCS_ERR (1 << 2)
#define RP23XX_RV_ADC_FCS_SHIFT (1 << 1)
#define RP23XX_RV_ADC_FCS_EN (1 << 0)
#define RP23XX_RV_ADC_FIFO_MASK (0x00008fff)
#define RP23XX_RV_ADC_FIFO_ERR (1 << 15)
#define RP23XX_RV_ADC_FIFO_VAL_MASK (0x00000fff)
#define RP23XX_RV_ADC_DIV_MASK (0x00ffffff)
#define RP23XX_RV_ADC_DIV_INT_MASK (0x00ffff00)
#define RP23XX_RV_ADC_DIV_FRAC_MASK (0x000000ff)
#define RP23XX_RV_ADC_INTR_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTE_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTF_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTS_FIFO (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_bootram.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_bootram.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n) ((n) * 4 + 0x000800)
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET 0x00000808
#define RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n) ((n) * 4 + 0x00080c)
/* Register definitions *****************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n))
#define RP23XX_BOOTRAM_BOOTLOCK_STAT (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET)
#define RP23XX_BOOTRAM_BOOTLOCK(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_MASK 0xffffffff
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_MASK 0x000000ff
#define RP23XX_BOOTRAM_BOOTLOCK_MASK 0xffffffff
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_busctrl.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_busctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define RP23XX_BUSCTRL_PERFCTR_EN_OFFSET 0x00000008
#define RP23XX_BUSCTRL_PERFCTR_OFFSET(n) ((n) * 8 + 0x00000c)
#define RP23XX_BUSCTRL_PERFSEL_OFFSET(n) ((n) * 8 + 0x000010)
/* Register definitions *****************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR_EN (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_EN_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_OFFSET(n))
#define RP23XX_BUSCTRL_PERFSEL(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFSEL_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_MASK 0x00001111
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_W (1 << 12)
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_R (1 << 8)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC1 (1 << 4)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC0 (1 << 0)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_EN (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_MASK 0x00ffffff
#define RP23XX_BUSCTRL_PERFSEL_MASK 0x0000007f
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H */

618
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_clocks.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_clocks.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clock index **************************************************************/
#define RP23XX_CLOCKS_NDX_GPOUT0 0 /* Clock output to GPIO 21 */
#define RP23XX_CLOCKS_NDX_GPOUT1 1 /* Clock output to GPIO 23 */
#define RP23XX_CLOCKS_NDX_GPOUT2 2 /* Clock output to GPIO 24 */
#define RP23XX_CLOCKS_NDX_GPOUT3 3 /* Clock output to GPIO 25 */
#define RP23XX_CLOCKS_NDX_REF 4 /* Reference clock */
#define RP23XX_CLOCKS_NDX_SYS 5 /* System clock */
#define RP23XX_CLOCKS_NDX_PERI 6 /* Peripheral clock */
#define RP23XX_CLOCKS_NDX_HSTX 7 /* HSTX clock */
#define RP23XX_CLOCKS_NDX_USB 8 /* USB clock */
#define RP23XX_CLOCKS_NDX_ADC 9 /* ADC clock */
#define RP23XX_CLOCKS_NDX_MAX 10
/* Register offsets *********************************************************/
#define RP23XX_CLOCKS_CLK_CTRL_OFFSET 0x000000 /* Clock control */
#define RP23XX_CLOCKS_CLK_DIV_OFFSET 0x000004 /* Clock divisor */
#define RP23XX_CLOCKS_CLK_SELECTED_OFFSET 0x000008 /* Indicates which src is currently selected */
#define RP23XX_CLOCKS_CLK_NDX_CTRL_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_NDX_DIV_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_DIV_OFFSET)
#define RP23XX_CLOCKS_CLK_NDX_SELECTED_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_SELECTED_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_OFFSET 0x000078
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_OFFSET 0x00007c
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET 0x000080
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x000084
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x000088
#define RP23XX_CLOCKS_FC0_REF_KHZ_OFFSET 0x00008c /* Reference clock frequency in kHz */
#define RP23XX_CLOCKS_FC0_MIN_KHZ_OFFSET 0x000090 /* Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags */
#define RP23XX_CLOCKS_FC0_MAX_KHZ_OFFSET 0x000094 /* Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags */
#define RP23XX_CLOCKS_FC0_DELAY_OFFSET 0x000098 /* Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period */
#define RP23XX_CLOCKS_FC0_INTERVAL_OFFSET 0x00009c /* The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us */
#define RP23XX_CLOCKS_FC0_SRC_OFFSET 0x0000a0 /* Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count */
#define RP23XX_CLOCKS_FC0_STATUS_OFFSET 0x0000a4 /* Frequency counter status */
#define RP23XX_CLOCKS_FC0_RESULT_OFFSET 0x0000a8 /* Result of frequency measurement, only valid when status_done=1 */
#define RP23XX_CLOCKS_WAKE_EN0_OFFSET 0x0000ac /* enable clock in wake mode */
#define RP23XX_CLOCKS_WAKE_EN1_OFFSET 0x0000b0 /* enable clock in wake mode */
#define RP23XX_CLOCKS_SLEEP_EN0_OFFSET 0x0000b4 /* enable clock in sleep mode */
#define RP23XX_CLOCKS_SLEEP_EN1_OFFSET 0x0000b8 /* enable clock in sleep mode */
#define RP23XX_CLOCKS_ENABLED0_OFFSET 0x0000bc /* indicates the state of the clock enable */
#define RP23XX_CLOCKS_ENABLED1_OFFSET 0x0000c0 /* indicates the state of the clock enable */
#define RP23XX_CLOCKS_INTR_OFFSET 0x0000c4 /* Raw Interrupts */
#define RP23XX_CLOCKS_INTE_OFFSET 0x0000c8 /* Interrupt Enable */
#define RP23XX_CLOCKS_INTF_OFFSET 0x0000cc /* Interrupt Force */
#define RP23XX_CLOCKS_INTS_OFFSET 0x0000d0 /* Interrupt status after masking & forcing */
/* Register definitions *****************************************************/
#define RP23XX_CLOCKS_CLK_NDX_CTRL(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_CTRL_OFFSET(n))
#define RP23XX_CLOCKS_CLK_NDX_DIV(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_DIV_OFFSET(n))
#define RP23XX_CLOCKS_CLK_NDX_SELECTED(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_SELECTED_OFFSET(n))
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT0_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT1_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT2_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_GPOUT3_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_REF_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_REF_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_REF_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_SYS_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_SYS_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_SYS_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_PERI_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_PERI))
#define RP23XX_CLOCKS_CLK_PERI_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_PERI))
#define RP23XX_CLOCKS_CLK_HSTX_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_HSTX_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_HSTX_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_USB_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_USB_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_USB_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_ADC_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_CLK_ADC_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_CLK_ADC_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET)
#define RP23XX_CLOCKS_FC0_REF_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_REF_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_MIN_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_MIN_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_MAX_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_MAX_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_DELAY (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_DELAY_OFFSET)
#define RP23XX_CLOCKS_FC0_INTERVAL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_INTERVAL_OFFSET)
#define RP23XX_CLOCKS_FC0_SRC (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_SRC_OFFSET)
#define RP23XX_CLOCKS_FC0_STATUS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_STATUS_OFFSET)
#define RP23XX_CLOCKS_FC0_RESULT (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_RESULT_OFFSET)
#define RP23XX_CLOCKS_WAKE_EN0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_WAKE_EN0_OFFSET)
#define RP23XX_CLOCKS_WAKE_EN1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_WAKE_EN1_OFFSET)
#define RP23XX_CLOCKS_SLEEP_EN0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_SLEEP_EN0_OFFSET)
#define RP23XX_CLOCKS_SLEEP_EN1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_SLEEP_EN1_OFFSET)
#define RP23XX_CLOCKS_ENABLED0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_ENABLED0_OFFSET)
#define RP23XX_CLOCKS_ENABLED1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_ENABLED1_OFFSET)
#define RP23XX_CLOCKS_INTR (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTR_OFFSET)
#define RP23XX_CLOCKS_INTE (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTE_OFFSET)
#define RP23XX_CLOCKS_INTF (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTF_OFFSET)
#define RP23XX_CLOCKS_INTS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ROSC_CLKSRC (0x5 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ROSC_CLKSRC (0x5 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x5 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x5 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_MASK (0x03 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x3 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_MASK (0x03)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_ROSC_CLKSRC_PH (0x0)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_CLKSRC_CLK_REF_AUX (0x1)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC (0x2)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_LPOSC_CLKSRC (0x3)
#define RP23XX_CLOCKS_CLK_REF_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_REF_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_REF_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_USB (0x1 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_ROSC_CLKSRC (0x2 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_SRC (1 << 0)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX (0x1)
#define RP23XX_CLOCKS_CLK_SYS_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_SYS_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_SYS_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS (0x0 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_USB (0x2 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x3 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_XOSC_CLKSRC (0x4 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN0 (0x5 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN1 (0x6 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_PERI_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_PERI_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLK_SYS (0x0 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_PLL_USB (0x2 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_GPIN0 (0x3 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_GPIN1 (0x4 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_HSTX_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_HSTX_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_USB_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^4 */
#define RP23XX_CLOCKS_CLK_USB_DIV_INT_MASK (0x0f << RP23XX_CLOCKS_CLK_USB_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^4 */
#define RP23XX_CLOCKS_CLK_ADC_DIV_INT_MASK (0x0f << RP23XX_CLOCKS_CLK_ADC_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_CLKSRC_PLL_USB_PRIMARY (0x1)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_CLKSRC_GPIN0 (0x2)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_CLKSRC_PLL_SYS_PRIMARY_ROSC (0x1)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_CLKSRC_GPIN1 (0x2)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_CLKSRC_PLL_USB_PRIMARY_LPOSC (0x1)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_CLKSRC_GPIN1 (0x2)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR (1 << 16) /* For clearing the resus after the fault that triggered it has been corrected */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_FRCE (1 << 12) /* Force a resus, for test purposes only */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE (1 << 8) /* Enable resus */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MASK (0xff) /* This is expressed as a number of clk_ref cycles and must be >= 2x /min_ */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED (1 << 0) /* Clock has been resuscitated, correct the error then send ctrl_clear=1 */
#define RP23XX_CLOCKS_FC0_REF_KHZ_MASK (0xfffff)
#define RP23XX_CLOCKS_FC0_MIN_KHZ_MASK (0x1ffffff)
#define RP23XX_CLOCKS_FC0_MAX_KHZ_MASK (0x1ffffff)
#define RP23XX_CLOCKS_FC0_DELAY_MASK (0x07)
#define RP23XX_CLOCKS_FC0_INTERVAL_MASK (0x0f)
#define RP23XX_CLOCKS_FC0_SRC_MASK (0xff)
#define RP23XX_CLOCKS_FC0_SRC_NULL (0x0)
#define RP23XX_CLOCKS_FC0_SRC_PLL_SYS_CLKSRC_PRIMARY (0x1)
#define RP23XX_CLOCKS_FC0_SRC_PLL_USB_CLKSRC_PRIMARY (0x2)
#define RP23XX_CLOCKS_FC0_SRC_ROSC_CLKSRC (0x3)
#define RP23XX_CLOCKS_FC0_SRC_ROSC_CLKSRC_PH (0x4)
#define RP23XX_CLOCKS_FC0_SRC_XOSC_CLKSRC (0x5)
#define RP23XX_CLOCKS_FC0_SRC_CLKSRC_GPIN0 (0x6)
#define RP23XX_CLOCKS_FC0_SRC_CLKSRC_GPIN1 (0x7)
#define RP23XX_CLOCKS_FC0_SRC_CLK_REF (0x8)
#define RP23XX_CLOCKS_FC0_SRC_CLK_SYS (0x9)
#define RP23XX_CLOCKS_FC0_SRC_CLK_PERI (0xa)
#define RP23XX_CLOCKS_FC0_SRC_CLK_USB (0xb)
#define RP23XX_CLOCKS_FC0_SRC_CLK_ADC (0xc)
#define RP23XX_CLOCKS_FC0_SRC_CLK_HSTX (0xd)
#define RP23XX_CLOCKS_FC0_SRC_CLK_LPOSC_CLKSRC (0xe)
#define RP23XX_CLOCKS_FC0_SRC_CLK_OTP_CLK2FC (0xf)
#define RP23XX_CLOCKS_FC0_SRC_CLK_PLL_USB_CLKSRC_PRIMARY_DFT (0x10)
#define RP23XX_CLOCKS_FC0_STATUS_DIED (1 << 28) /* Test clock stopped during test */
#define RP23XX_CLOCKS_FC0_STATUS_FAST (1 << 24) /* Test clock faster than expected, only valid when status_done=1 */
#define RP23XX_CLOCKS_FC0_STATUS_SLOW (1 << 20) /* Test clock slower than expected, only valid when status_done=1 */
#define RP23XX_CLOCKS_FC0_STATUS_FAIL (1 << 16) /* Test failed */
#define RP23XX_CLOCKS_FC0_STATUS_WAITING (1 << 12) /* Waiting for test clock to start */
#define RP23XX_CLOCKS_FC0_STATUS_RUNNING (1 << 8) /* Test running */
#define RP23XX_CLOCKS_FC0_STATUS_DONE (1 << 4) /* Test complete */
#define RP23XX_CLOCKS_FC0_STATUS_PASS (1 << 0) /* Test passed */
#define RP23XX_CLOCKS_FC0_RESULT_KHZ_SHIFT (5)
#define RP23XX_CLOCKS_FC0_RESULT_KHZ_MASK (0x1ffffff << RP23XX_CLOCKS_FC0_RESULT_KHZ_SHIFT)
#define RP23XX_CLOCKS_FC0_RESULT_FRAC_MASK (0x1f)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_ENABLED0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_ENABLED0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_ENABLED0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_ENABLED0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_ENABLED1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_ENABLED1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_INTR_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTE_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTF_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTS_CLK_SYS_RESUS (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_coresight_trace.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET 0x00000000
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_MASK (0x00000003)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW (1 << 1)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH (1 << 0)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_MASK (0xffffffff)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_dma.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_DMA_READ_ADDR_OFFSET 0x000000 /* DMA Read Address pointer */
#define RP23XX_DMA_WRITE_ADDR_OFFSET 0x000004 /* DMA Write Address pointer */
#define RP23XX_DMA_TRANS_COUNT_OFFSET 0x000008 /* DMA Transfer Count */
#define RP23XX_DMA_CTRL_TRIG_OFFSET 0x00000c /* DMA Control and Status */
#define RP23XX_DMA_AL1_CTRL_OFFSET 0x000010 /* Alias for CTRL register */
#define RP23XX_DMA_AL1_READ_ADDR_OFFSET 0x000014 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL1_WRITE_ADDR_OFFSET 0x000018 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET 0x00001c /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_CTRL_OFFSET 0x000020 /* Alias for CTRL register */
#define RP23XX_DMA_AL2_TRANS_COUNT_OFFSET 0x000024 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_READ_ADDR_OFFSET 0x000028 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET 0x00002c /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_CTRL_OFFSET 0x000030 /* Alias for CTRL register */
#define RP23XX_DMA_AL3_WRITE_ADDR_OFFSET 0x000034 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_TRANS_COUNT_OFFSET 0x000038 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET 0x00003c /* Alias for READ_ADDR register */
#define RP23XX_DMA_INTR_OFFSET 0x000400 /* Interrupt Status (raw) */
#define RP23XX_DMA_INTE0_OFFSET 0x000404 /* Interrupt Enables for IRQ 0 */
#define RP23XX_DMA_INTF0_OFFSET 0x000408 /* Force Interrupts */
#define RP23XX_DMA_INTS0_OFFSET 0x00040c /* Interrupt Status for IRQ 0 */
#define RP23XX_DMA_INTE1_OFFSET 0x000414 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF1_OFFSET 0x000418 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS1_OFFSET 0x00041c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE2_OFFSET 0x000424 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF2_OFFSET 0x000428 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS2_OFFSET 0x00042c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE3_OFFSET 0x000434 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF3_OFFSET 0x000438 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS3_OFFSET 0x00043c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_TIMER0_OFFSET 0x000440 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER1_OFFSET 0x000444 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER2_OFFSET 0x000448 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER3_OFFSET 0x00044c /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET 0x000450 /* Trigger one or more channels simultaneously */
#define RP23XX_DMA_SNIFF_CTRL_OFFSET 0x000454 /* Sniffer Control */
#define RP23XX_DMA_SNIFF_DATA_OFFSET 0x000458 /* Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. */
#define RP23XX_DMA_FIFO_LEVELS_OFFSET 0x000460 /* Debug RAF, WAF, TDF levels */
#define RP23XX_DMA_CHAN_ABORT_OFFSET 0x000464 /* Abort an in-progress transfer sequence on one or more channels */
#define RP23XX_DMA_N_CHANNELS_OFFSET 0x000468 /* The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */
#define RP23XX_DMA_SECCFG_OFFSET(n) (0x000480 + (n) * 0x0004)
#define RP23XX_DMA_DBG_SECCFG_IRQ_OFFSET(n) (0x0004c4 + (n) * 0x0004)
#define RP23XX_DMA_SECCFG_MISC_OFFSET 0x0004d0
#define RP23XX_DMA_DBG_CTDREQ_OFFSET(n) (0x000800 + (n) * 0x0040)
#define RP23XX_DMA_DBG_TCR_OFFSET(n) (0x000804 + (n) * 0x0040)
#define RP23XX_DMA_MPU_CTRL_OFFSET 0x000500
#define RP23XX_DMA_MPU_BAR_OFFSET(n) (0x000504 + (n) * 0x0008)
#define RP23XX_DMA_MPU_LAR_OFFSET(n) (0x000508 + (n) * 0x0008)
/* Register definitions *****************************************************/
#define RP23XX_DMA_CH(n) (RP23XX_DMA_BASE + (0x0040 * (n)))
#define RP23XX_DMA_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_READ_ADDR_OFFSET)
#define RP23XX_DMA_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_CTRL_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_CTRL_TRIG_OFFSET)
#define RP23XX_DMA_AL1_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_CTRL_OFFSET)
#define RP23XX_DMA_AL1_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL1_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET)
#define RP23XX_DMA_AL2_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_CTRL_OFFSET)
#define RP23XX_DMA_AL2_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL2_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_AL3_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_CTRL_OFFSET)
#define RP23XX_DMA_AL3_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL3_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL3_READ_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_INTR (RP23XX_DMA_BASE + RP23XX_DMA_INTR_OFFSET)
#define RP23XX_DMA_INTE0 (RP23XX_DMA_BASE + RP23XX_DMA_INTE0_OFFSET)
#define RP23XX_DMA_INTF0 (RP23XX_DMA_BASE + RP23XX_DMA_INTF0_OFFSET)
#define RP23XX_DMA_INTS0 (RP23XX_DMA_BASE + RP23XX_DMA_INTS0_OFFSET)
#define RP23XX_DMA_INTE1 (RP23XX_DMA_BASE + RP23XX_DMA_INTE1_OFFSET)
#define RP23XX_DMA_INTF1 (RP23XX_DMA_BASE + RP23XX_DMA_INTF1_OFFSET)
#define RP23XX_DMA_INTS1 (RP23XX_DMA_BASE + RP23XX_DMA_INTS1_OFFSET)
#define RP23XX_DMA_INTE2 (RP23XX_DMA_BASE + RP23XX_DMA_INTE2_OFFSET)
#define RP23XX_DMA_INTF2 (RP23XX_DMA_BASE + RP23XX_DMA_INTF2_OFFSET)
#define RP23XX_DMA_INTS2 (RP23XX_DMA_BASE + RP23XX_DMA_INTS2_OFFSET)
#define RP23XX_DMA_INTE3 (RP23XX_DMA_BASE + RP23XX_DMA_INTE3_OFFSET)
#define RP23XX_DMA_INTF3 (RP23XX_DMA_BASE + RP23XX_DMA_INTF3_OFFSET)
#define RP23XX_DMA_INTS3 (RP23XX_DMA_BASE + RP23XX_DMA_INTS3_OFFSET)
#define RP23XX_DMA_TIMER0 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER0_OFFSET)
#define RP23XX_DMA_TIMER1 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER1_OFFSET)
#define RP23XX_DMA_TIMER2 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER2_OFFSET)
#define RP23XX_DMA_TIMER3 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER3_OFFSET)
#define RP23XX_DMA_MULTI_CHAN_TRIGGER (RP23XX_DMA_BASE + RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET)
#define RP23XX_DMA_SNIFF_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_CTRL_OFFSET)
#define RP23XX_DMA_SNIFF_DATA (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_DATA_OFFSET)
#define RP23XX_DMA_FIFO_LEVELS (RP23XX_DMA_BASE + RP23XX_DMA_FIFO_LEVELS_OFFSET)
#define RP23XX_DMA_CHAN_ABORT (RP23XX_DMA_BASE + RP23XX_DMA_CHAN_ABORT_OFFSET)
#define RP23XX_DMA_N_CHANNELS (RP23XX_DMA_BASE + RP23XX_DMA_N_CHANNELS_OFFSET)
#define RP23XX_DMA_SECCFG(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_OFFSET(n))
#define RP23XX_DMA_SECCFG_IRQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_IRQ_OFFSET(n))
#define RP23XX_DMA_SECCFG_MISC (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_MISC_OFFSET)
#define RP23XX_DMA_DBG_CTDREQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_CTDREQ_OFFSET(n))
#define RP23XX_DMA_DBG_TCR(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_TCR_OFFSET(n))
#define RP23XX_DMA_MPU_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_MPU_CTRL_OFFSET)
#define RP23XX_DMA_MPU_BAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_BAR_OFFSET(n))
#define RP23XX_DMA_MPU_LAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_LAR_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_DMA_CTRL_TRIG_AHB_ERROR (1 << 31) /* Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */
#define RP23XX_DMA_CTRL_TRIG_READ_ERROR (1 << 30) /* If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_WRITE_ERROR (1 << 29) /* If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_BUSY (1 << 26) /* This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. */
#define RP23XX_DMA_CTRL_TRIG_SNIFF_EN (1 << 25) /* If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. */
#define RP23XX_DMA_CTRL_TRIG_BSWAP (1 << 24) /* Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. */
#define RP23XX_DMA_CTRL_TRIG_IRQ_QUIET (1 << 23) /* In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT (17) /* Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_MASK (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER0 (0x3b << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 0 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER1 (0x3c << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 1 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER2 (0x3d << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 2 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER3 (0x3e << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 3 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_PERMANENT (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Permanent request, for unpaced transfers. */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT (13) /* When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0). */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SEL (1 << 12) /* Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT (8) /* Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_RING_NONE (0x0 << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE_REV (1 << 7) /* If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.*/
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE (1 << 6) /* If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ_REV (1 << 5) /* If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ (1 << 4) /* If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT (2) /* Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_MASK (0x03 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_BYTE (0x0 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD (0x1 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_WORD (0x2 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_HIGH_PRIORITY (1 << 1) /* HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. */
#define RP23XX_DMA_CTRL_TRIG_EN (1 << 0) /* DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) */
#define RP23XX_DMA_INTR_MASK (0xffff) /* Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. */
#define RP23XX_DMA_INTE0_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 0. */
#define RP23XX_DMA_INTF0_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS0_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE1_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 1. */
#define RP23XX_DMA_INTF1_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE1. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS1_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE2_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 2. */
#define RP23XX_DMA_INTF2_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE2. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS2_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE3_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 3. */
#define RP23XX_DMA_INTF3_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE3. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS3_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_TIMER0_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER0_X_MASK (0xffff << RP23XX_DMA_TIMER0_X_SHIFT)
#define RP23XX_DMA_TIMER0_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_MASK (0xffff << RP23XX_DMA_TIMER1_X_SHIFT)
#define RP23XX_DMA_TIMER1_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_MASK (0xffff << RP23XX_DMA_TIMER2_X_SHIFT)
#define RP23XX_DMA_TIMER2_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_MASK (0xffff << RP23XX_DMA_TIMER3_X_SHIFT)
#define RP23XX_DMA_TIMER3_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_MASK (0xffff) /* Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_INV (1 << 11) /* If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_REV (1 << 10) /* If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_BSWAP (1 << 9) /* Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT (5)
#define RP23XX_DMA_SNIFF_CTRL_CALC_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32 (0x0 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32R (0x1 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16 (0x2 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16R (0x3 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_EVEN (0xe << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* XOR reduction over all data. == 1 if the total 1 population count is odd. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SUM (0xf << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT (1) /* DMA channel for Sniffer to observe */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_EN (1 << 0) /* Enable sniffer */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT (16) /* Current Read-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT (8) /* Current Write-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_TDF_LVL_MASK (0xff) /* Current Transfer-Data-FIFO fill level */
#define RP23XX_DMA_CHAN_ABORT_MASK (0xffff) /* Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. */
#define RP23XX_DMA_N_CHANNELS_MASK (0x1f)
#define RP23XX_DMA_SECCFG_MASK (0x00000007)
#define RP23XX_DMA_SECCFG_LOCK (1 << 2) /* LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel’s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. */
#define RP23XX_DMA_SECCFG_S (1 << 1) /* Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. */
#define RP23XX_DMA_SECCFG_P (1 << 0) /* Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. */
#define RP23XX_DMA_SECCFG_IRQ_MASK (0x00000003)
#define RP23XX_DMA_SECCFG_IRQ_S (1 << 1) /* Secure IRQ. If 1, this IRQ’s control registers can only be accessed from a Secure context. If 0, this IRQ’s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Secure channels. */
#define RP23XX_DMA_SECCFG_IRQ_P (1 << 0) /* Privileged IRQ. If 1, this IRQ’s control registers can only be accessed from a Privileged context. If 0, this IRQ’s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Privileged channels. */
#define RP23XX_DMA_SECCFG_MISC_MASK (0x000003ff)
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9) /* If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. */
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9)
#define RP23XX_DMA_DBG_CTDREQ_MASK (0x3f)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_dreq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_DMA_DREQ_PIO0_TX0 0
#define RP23XX_DMA_DREQ_PIO0_TX1 1
#define RP23XX_DMA_DREQ_PIO0_TX2 2
#define RP23XX_DMA_DREQ_PIO0_TX3 3
#define RP23XX_DMA_DREQ_PIO0_RX0 4
#define RP23XX_DMA_DREQ_PIO0_RX1 5
#define RP23XX_DMA_DREQ_PIO0_RX2 6
#define RP23XX_DMA_DREQ_PIO0_RX3 7
#define RP23XX_DMA_DREQ_PIO1_TX0 8
#define RP23XX_DMA_DREQ_PIO1_TX1 9
#define RP23XX_DMA_DREQ_PIO1_TX2 10
#define RP23XX_DMA_DREQ_PIO1_TX3 11
#define RP23XX_DMA_DREQ_PIO1_RX0 12
#define RP23XX_DMA_DREQ_PIO1_RX1 13
#define RP23XX_DMA_DREQ_PIO1_RX2 14
#define RP23XX_DMA_DREQ_PIO1_RX3 15
#define RP23XX_DMA_DREQ_PIO2_TX0 16
#define RP23XX_DMA_DREQ_PIO2_TX1 17
#define RP23XX_DMA_DREQ_PIO2_TX2 18
#define RP23XX_DMA_DREQ_PIO2_TX3 19
#define RP23XX_DMA_DREQ_PIO2_RX0 20
#define RP23XX_DMA_DREQ_PIO2_RX1 21
#define RP23XX_DMA_DREQ_PIO2_RX2 22
#define RP23XX_DMA_DREQ_PIO2_RX3 23
#define RP23XX_DMA_DREQ_SPI0_TX 24
#define RP23XX_DMA_DREQ_SPI0_RX 25
#define RP23XX_DMA_DREQ_SPI1_TX 26
#define RP23XX_DMA_DREQ_SPI1_RX 27
#define RP23XX_DMA_DREQ_UART0_TX 28
#define RP23XX_DMA_DREQ_UART0_RX 29
#define RP23XX_DMA_DREQ_UART1_TX 30
#define RP23XX_DMA_DREQ_UART1_RX 31
#define RP23XX_DMA_DREQ_PWM_WRAP0 32
#define RP23XX_DMA_DREQ_PWM_WRAP1 33
#define RP23XX_DMA_DREQ_PWM_WRAP2 34
#define RP23XX_DMA_DREQ_PWM_WRAP3 35
#define RP23XX_DMA_DREQ_PWM_WRAP4 36
#define RP23XX_DMA_DREQ_PWM_WRAP5 37
#define RP23XX_DMA_DREQ_PWM_WRAP6 38
#define RP23XX_DMA_DREQ_PWM_WRAP7 39
#define RP23XX_DMA_DREQ_PWM_WRAP8 40
#define RP23XX_DMA_DREQ_PWM_WRAP9 41
#define RP23XX_DMA_DREQ_PWM_WRAP10 42
#define RP23XX_DMA_DREQ_PWM_WRAP11 43
#define RP23XX_DMA_DREQ_I2C0_TX 44
#define RP23XX_DMA_DREQ_I2C0_RX 45
#define RP23XX_DMA_DREQ_I2C1_TX 46
#define RP23XX_DMA_DREQ_I2C1_RX 47
#define RP23XX_DMA_DREQ_ADC 48
#define RP23XX_DMA_DREQ_XIP_STREAM 49
#define RP23XX_DMA_DREQ_XIP_QMITX 50
#define RP23XX_DMA_DREQ_XIP_QMIRX 51
#define RP23XX_DMA_DREQ_HSTX 52
#define RP23XX_DMA_DREQ_CORESIGHT 53
#define RP23XX_DMA_DREQ_SHA256 54
#define RP23XX_DMA_DREQ_DMA_TIMER0 59
#define RP23XX_DMA_DREQ_DMA_TIMER1 60
#define RP23XX_DMA_DREQ_DMA_TIMER2 61
#define RP23XX_DMA_DREQ_DMA_TIMER3 62
#define RP23XX_DMA_DREQ_FORCE 63
#define RP23XX_DMA_DREQ_COUNT 64
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_glitch_detector.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_glitch_detector.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_OFFSET 0x00000000
#define RP23XX_GLITCH_DETECTOR_DISARM_OFFSET 0x00000004
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET 0x00000008
#define RP23XX_GLITCH_DETECTOR_LOCK_OFFSET 0x0000000c
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET 0x00000010
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET 0x00000014
/* Register definitions *****************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_ARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_DISARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_DISARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET)
#define RP23XX_GLITCH_DETECTOR_LOCK (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_LOCK_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_DISARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_MASK 0xff00ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MASK 0xff000000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MASK 0x0000c000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MASK 0x00003000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MASK 0x00000c00
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MASK 0x00000300
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_MASK 0x000000c0
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_MASK 0x00000030
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_MASK 0x0000000c
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_MASK 0x00000003
#define RP23XX_GLITCH_DETECTOR_LOCK_MASK 0x000000ff
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_MASK 0x0000000f
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET3_MASK 0x00000008
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET2_MASK 0x00000004
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET1_MASK 0x00000002
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET0_MASK 0x00000001
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_MASK 0x0000000f
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http: *www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_RP23XX_HARDWARE_RP23XX_HAZARD3_H
#define __ARCH_RISCV_SRC_RP23XX_HARDWARE_RP23XX_HAZARD3_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define hazard3_irqarray_read(csr, index) (READ_AND_SET_CSR(csr, (index)) >> 16)
#define hazard3_irqarray_write(csr, index, data) (WRITE_CSR(csr, (index) | ((uint32_t)(data) << 16)))
#define hazard3_irqarray_set(csr, index, data) (SET_CSR(csr, (index) | ((uint32_t)(data) << 16)))
#define hazard3_irqarray_clear(csr, index, data) (CLEAR_CSR(csr, (index) | ((uint32_t)(data) << 16)))
/****************************************************************************
* This is a Hazard3 custom CSR.
****************************************************************************/
#define RVCSR_PMPCFGM0_OFFSET 0x00000bd0
#define RVCSR_PMPCFGM0_BITS 0x0000ffff
#define RVCSR_PMPCFGM0_RESET 0x00000000
#define RVCSR_PMPCFGM0_MSB 15
#define RVCSR_PMPCFGM0_LSB 0
#define RVCSR_PMPCFGM0_ACCESS "RW"
/****************************************************************************
* Register : RVCSR_MEIEA
* Description : External interrupt enable array.
*
* The array contains a read-write bit for each external interrupt
* request: a `1` bit indicates that interrupt is currently
* enabled. At reset, all external interrupts are disabled.
*
* If enabled, an external interrupt can cause assertion of the
* standard RISC-V machine external interrupt pending flag
* (`mip.meip`), and therefore cause the processor to enter the
* external interrupt vector. See `meipa`.
*
* There are up to 512 external interrupts. The upper half of this
* register contains a 16-bit window into the full 512-bit vector.
* The window is indexed by the 5 LSBs of the write data.
****************************************************************************/
#define RVCSR_MEIEA_OFFSET 0x00000be0
#define RVCSR_MEIEA_BITS 0xffff001f
#define RVCSR_MEIEA_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MEIEA_WINDOW
* Description : 16-bit read/write window into the external interrupt enable
* array
****************************************************************************/
#define RVCSR_MEIEA_WINDOW_RESET 0x0000
#define RVCSR_MEIEA_WINDOW_BITS 0xffff0000
#define RVCSR_MEIEA_WINDOW_MSB 31
#define RVCSR_MEIEA_WINDOW_LSB 16
#define RVCSR_MEIEA_WINDOW_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEIEA_INDEX
* Description : Write-only self-clearing field (no value is stored) used to
* control which window of the array appears in `window`.
****************************************************************************/
#define RVCSR_MEIEA_INDEX_RESET 0x00
#define RVCSR_MEIEA_INDEX_BITS 0x0000001f
#define RVCSR_MEIEA_INDEX_MSB 4
#define RVCSR_MEIEA_INDEX_LSB 0
#define RVCSR_MEIEA_INDEX_ACCESS "WO"
/****************************************************************************
* Register : RVCSR_MEIPA
* Description : External interrupt pending array
*
* Contains a read-only bit for each external interrupt request.
* Similarly to `meiea`, this register is a window into an array
* of up to 512 external interrupt flags. The status appears in
* the upper 16 bits of the value read from `meipa`, and the lower
* 5 bits of the value _written_ by the same CSR instruction (or 0
* if no write takes place) select a 16-bit window of the full
* interrupt pending array.
*
* A `1` bit indicates that interrupt is currently asserted. IRQs
* are assumed to be level-sensitive, and the relevant `meipa` bit
* is cleared by servicing the requester so that it deasserts its
* interrupt request.
*
* When any interrupt of sufficient priority is both set in
* `meipa` and enabled in `meiea`, the standard RISC-V external
* interrupt pending bit `mip.meip` is asserted. In other words,
* `meipa` is filtered by `meiea` to generate the standard
* `mip.meip` flag.
****************************************************************************/
#define RVCSR_MEIPA_OFFSET 0x00000be1
#define RVCSR_MEIPA_BITS 0xffff001f
#define RVCSR_MEIPA_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MEIPA_WINDOW
* Description : 16-bit read-only window into the external interrupt pending
* array
****************************************************************************/
#define RVCSR_MEIPA_WINDOW_RESET "-"
#define RVCSR_MEIPA_WINDOW_BITS 0xffff0000
#define RVCSR_MEIPA_WINDOW_MSB 31
#define RVCSR_MEIPA_WINDOW_LSB 16
#define RVCSR_MEIPA_WINDOW_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MEIPA_INDEX
* Description : Write-only, self-clearing field (no value is stored) used to
* control which window of the array appears in `window`.
****************************************************************************/
#define RVCSR_MEIPA_INDEX_RESET 0x00
#define RVCSR_MEIPA_INDEX_BITS 0x0000001f
#define RVCSR_MEIPA_INDEX_MSB 4
#define RVCSR_MEIPA_INDEX_LSB 0
#define RVCSR_MEIPA_INDEX_ACCESS "WO"
/****************************************************************************
* Register : RVCSR_MEIFA
* Description : External interrupt force array
*
* Contains a read-write bit for every interrupt request. Writing
* a 1 to a bit in the interrupt force array causes the
* corresponding bit to become pending in `meipa`. Software can
* use this feature to manually trigger a particular interrupt.
*
* There are no restrictions on using `meifa` inside of an
* interrupt. The more useful case here is to schedule some lower-
* priority handler from within a high-priority interrupt, so that
* it will execute before the core returns to the foreground code.
* Implementers may wish to reserve some external IRQs with their
* external inputs tied to 0 for this purpose.
*
* Bits can be cleared by software, and are cleared automatically
* by hardware upon a read of `meinext` which returns the
* corresponding IRQ number in `meinext.irq` with `mienext.noirq`
* clear (no matter whether `meinext.update` is written).
*
* `meifa` implements the same array window indexing scheme as
* `meiea` and `meipa`.
****************************************************************************/
#define RVCSR_MEIFA_OFFSET 0x00000be2
#define RVCSR_MEIFA_BITS 0xffff001f
#define RVCSR_MEIFA_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MEIFA_WINDOW
* Description : 16-bit read/write window into the external interrupt force
* array
****************************************************************************/
#define RVCSR_MEIFA_WINDOW_RESET 0x0000
#define RVCSR_MEIFA_WINDOW_BITS 0xffff0000
#define RVCSR_MEIFA_WINDOW_MSB 31
#define RVCSR_MEIFA_WINDOW_LSB 16
#define RVCSR_MEIFA_WINDOW_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEIFA_INDEX
* Description : Write-only, self-clearing field (no value is stored) used to
* control which window of the array appears in `window`.
****************************************************************************/
#define RVCSR_MEIFA_INDEX_RESET 0x00
#define RVCSR_MEIFA_INDEX_BITS 0x0000001f
#define RVCSR_MEIFA_INDEX_MSB 4
#define RVCSR_MEIFA_INDEX_LSB 0
#define RVCSR_MEIFA_INDEX_ACCESS "WO"
/****************************************************************************
* Register : RVCSR_MEIPRA
* Description : External interrupt priority array
*
* Each interrupt has an (up to) 4-bit priority value associated
* with it, and each access to this register reads and/or writes a
* 16-bit window containing four such priority values. When less
* than 16 priority levels are available, the LSBs of the priority
* fields are hardwired to 0.
*
* When an interrupt's priority is lower than the current
* preemption priority `meicontext.preempt`, it is treated as not
* being pending for the purposes of `mip.meip`. The pending bit
* in `meipa` will still assert, but the machine external
* interrupt pending bit `mip.meip` will not, so the processor
* will ignore this interrupt. See `meicontext`.
****************************************************************************/
#define RVCSR_MEIPRA_OFFSET 0x00000be3
#define RVCSR_MEIPRA_BITS 0xffff001f
#define RVCSR_MEIPRA_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MEIPRA_WINDOW
* Description : 16-bit read/write window into the external interrupt
* priority array, containing four 4-bit priority values.
****************************************************************************/
#define RVCSR_MEIPRA_WINDOW_RESET 0x0000
#define RVCSR_MEIPRA_WINDOW_BITS 0xffff0000
#define RVCSR_MEIPRA_WINDOW_MSB 31
#define RVCSR_MEIPRA_WINDOW_LSB 16
#define RVCSR_MEIPRA_WINDOW_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEIPRA_INDEX
* Description : Write-only, self-clearing field (no value is stored) used to
* control which window of the array appears in `window`.
****************************************************************************/
#define RVCSR_MEIPRA_INDEX_RESET 0x00
#define RVCSR_MEIPRA_INDEX_BITS 0x0000001f
#define RVCSR_MEIPRA_INDEX_MSB 4
#define RVCSR_MEIPRA_INDEX_LSB 0
#define RVCSR_MEIPRA_INDEX_ACCESS "WO"
/****************************************************************************
* Register : RVCSR_MEINEXT
* Description : Get next external interrupt
*
* Contains the index of the highest-priority external interrupt
* which is both asserted in `meipa` and enabled in `meiea`, left-
* shifted by 2 so that it can be used to index an array of 32-bit
* function pointers. If there is no such interrupt, the MSB is
* set.
*
* When multiple interrupts of the same priority are both pending
* and enabled, the lowest-numbered wins. Interrupts with priority
* less than `meicontext.ppreempt` -- the _previous_ preemption
* priority -- are treated as though they are not pending. This is
* to ensure that a preempting interrupt frame does not service
* interrupts which may be in progress in the frame that was
* preempted.
****************************************************************************/
#define RVCSR_MEINEXT_OFFSET 0x00000be4
#define RVCSR_MEINEXT_BITS 0x800007fd
#define RVCSR_MEINEXT_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MEINEXT_NOIRQ
* Description : Set when there is no external interrupt which is enabled,
* pending, and has priority greater than or equal to
* `meicontext.ppreempt`. Can be efficiently tested with a `bltz`
* or `bgez` instruction.
****************************************************************************/
#define RVCSR_MEINEXT_NOIRQ_RESET 0x0
#define RVCSR_MEINEXT_NOIRQ_BITS 0x80000000
#define RVCSR_MEINEXT_NOIRQ_MSB 31
#define RVCSR_MEINEXT_NOIRQ_LSB 31
#define RVCSR_MEINEXT_NOIRQ_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MEINEXT_IRQ
* Description : Index of the highest-priority active external interrupt.
* Zero when no external interrupts with sufficient priority
* are both pending and enabled.
****************************************************************************/
#define RVCSR_MEINEXT_IRQ_RESET 0x000
#define RVCSR_MEINEXT_IRQ_BITS 0x000007fc
#define RVCSR_MEINEXT_IRQ_MSB 10
#define RVCSR_MEINEXT_IRQ_LSB 2
#define RVCSR_MEINEXT_IRQ_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MEINEXT_UPDATE
* Description : Writing 1 (self-clearing) causes hardware to update
* `meicontext` according to the IRQ number and preemption
* priority of the interrupt indicated in `noirq`/`irq`. This
* should be done in a single atomic operation, i.e. `csrrsi a0,
* meinext, 0x1`.
****************************************************************************/
#define RVCSR_MEINEXT_UPDATE_RESET 0x0
#define RVCSR_MEINEXT_UPDATE_BITS 0x00000001
#define RVCSR_MEINEXT_UPDATE_MSB 0
#define RVCSR_MEINEXT_UPDATE_LSB 0
#define RVCSR_MEINEXT_UPDATE_ACCESS "SC"
/****************************************************************************
* Register : RVCSR_MEICONTEXT
* Description : External interrupt context register
*
* Configures the priority level for interrupt preemption, and
* helps software track which interrupt it is currently in. The
* latter is useful when a common interrupt service routine
* handles interrupt requests from multiple instances of the same
* peripheral.
*
* A three-level stack of preemption priorities is maintained in
* the `preempt`, `ppreempt` and `pppreempt` fields. The priority
* stack is saved when hardware enters the external interrupt
* vector, and restored by an `mret` instruction if
* `meicontext.mreteirq` is set.
*
* The top entry of the priority stack, `preempt`, is used by
* hardware to ensure that only higher-priority interrupts can
* preempt the current interrupt. The next entry, `ppreempt`, is
* used to avoid servicing interrupts which may already be in
* progress in a frame that was preempted. The third entry,
* `pppreempt`, has no hardware effect, but ensures that `preempt`
* and `ppreempt` can be correctly saved/restored across arbitrary
* levels of preemption.
****************************************************************************/
#define RVCSR_MEICONTEXT_OFFSET 0x00000be5
#define RVCSR_MEICONTEXT_BITS 0xff1f9fff
#define RVCSR_MEICONTEXT_RESET 0x00008000
/****************************************************************************
* Field : RVCSR_MEICONTEXT_PPPREEMPT
* Description : Previous `ppreempt`. Set to `ppreempt` on priority save,
* set to zero on priority restore. Has no hardware effect,
* but ensures that when `meicontext` is saved/restored correctly,
* `preempt` and `ppreempt` stack correctly through arbitrarily many
* preemption frames.
****************************************************************************/
#define RVCSR_MEICONTEXT_PPPREEMPT_RESET 0x0
#define RVCSR_MEICONTEXT_PPPREEMPT_BITS 0xf0000000
#define RVCSR_MEICONTEXT_PPPREEMPT_MSB 31
#define RVCSR_MEICONTEXT_PPPREEMPT_LSB 28
#define RVCSR_MEICONTEXT_PPPREEMPT_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_PPREEMPT
* Description : Previous `preempt`. Set to `preempt` on priority save,
* restored to to `pppreempt` on priority restore.
*
* IRQs of lower priority than `ppreempt` are not visible in
* `meinext`, so that a preemptee is not re-taken in the
* preempting frame.
****************************************************************************/
#define RVCSR_MEICONTEXT_PPREEMPT_RESET 0x0
#define RVCSR_MEICONTEXT_PPREEMPT_BITS 0x0f000000
#define RVCSR_MEICONTEXT_PPREEMPT_MSB 27
#define RVCSR_MEICONTEXT_PPREEMPT_LSB 24
#define RVCSR_MEICONTEXT_PPREEMPT_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_PREEMPT
* Description : Minimum interrupt priority to preempt the current interrupt.
* Interrupts with lower priority than `preempt` do not cause the
* core to transfer to an interrupt handler. Updated by hardware
* when when `meinext.update` is written, or when hardware enters
* the external interrupt vector.
*
* If an interrupt is present in `meinext` when this field is
* updated, then `preempt` is set to one level greater than that
* interrupt's priority. Otherwise, `ppreempt` is set to one level
* greater than the maximum interrupt priority, disabling
* preemption.
****************************************************************************/
#define RVCSR_MEICONTEXT_PREEMPT_RESET 0x00
#define RVCSR_MEICONTEXT_PREEMPT_BITS 0x001f0000
#define RVCSR_MEICONTEXT_PREEMPT_MSB 20
#define RVCSR_MEICONTEXT_PREEMPT_LSB 16
#define RVCSR_MEICONTEXT_PREEMPT_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_NOIRQ
* Description : Not in interrupt (read/write). Set to 1 at reset. Set to
* `meinext.noirq` when `meinext.update` is written.
* No hardware effect.
****************************************************************************/
#define RVCSR_MEICONTEXT_NOIRQ_RESET 0x1
#define RVCSR_MEICONTEXT_NOIRQ_BITS 0x00008000
#define RVCSR_MEICONTEXT_NOIRQ_MSB 15
#define RVCSR_MEICONTEXT_NOIRQ_LSB 15
#define RVCSR_MEICONTEXT_NOIRQ_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_IRQ
* Description : Current IRQ number (read/write). Set to `meinext.irq` when
* `meinext.update` is written. No hardware effect.
****************************************************************************/
#define RVCSR_MEICONTEXT_IRQ_RESET 0x000
#define RVCSR_MEICONTEXT_IRQ_BITS 0x00001ff0
#define RVCSR_MEICONTEXT_IRQ_MSB 12
#define RVCSR_MEICONTEXT_IRQ_LSB 4
#define RVCSR_MEICONTEXT_IRQ_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_MTIESAVE
* Description : Reads as the current value of `mie.mtie`, if `clearts`
* is set by the same CSR access instruction. Otherwise reads as 0.
* Writes are ORed into `mie.mtie`.
****************************************************************************/
#define RVCSR_MEICONTEXT_MTIESAVE_RESET 0x0
#define RVCSR_MEICONTEXT_MTIESAVE_BITS 0x00000008
#define RVCSR_MEICONTEXT_MTIESAVE_MSB 3
#define RVCSR_MEICONTEXT_MTIESAVE_LSB 3
#define RVCSR_MEICONTEXT_MTIESAVE_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_MSIESAVE
* Description : Reads as the current value of `mie.msie`, if `clearts`
* is set by the same CSR access instruction. Otherwise reads as 0.
* Writes are ORed into `mie.msie`.
****************************************************************************/
#define RVCSR_MEICONTEXT_MSIESAVE_RESET 0x0
#define RVCSR_MEICONTEXT_MSIESAVE_BITS 0x00000004
#define RVCSR_MEICONTEXT_MSIESAVE_MSB 2
#define RVCSR_MEICONTEXT_MSIESAVE_LSB 2
#define RVCSR_MEICONTEXT_MSIESAVE_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_CLEARTS
* Description : Write-1 self-clearing field. Writing 1 will clear `mie.mtie`
* and `mie.msie`, and present their prior values in the
* `mtiesave` and `msiesave` of this register. This makes it safe
* to re-enable IRQs (via `mstatus.mie`) without the possibility
* of being preempted by the standard timer and soft interrupt
* handlers, which may not be aware of Hazard3's interrupt
* hardware.
*
* The clear due to `clearts` takes precedence over the set due to
* `mtiesave`/`msiesave`, although it would be unusual for
* software to write both on the same cycle.
****************************************************************************/
#define RVCSR_MEICONTEXT_CLEARTS_RESET 0x0
#define RVCSR_MEICONTEXT_CLEARTS_BITS 0x00000002
#define RVCSR_MEICONTEXT_CLEARTS_MSB 1
#define RVCSR_MEICONTEXT_CLEARTS_LSB 1
#define RVCSR_MEICONTEXT_CLEARTS_ACCESS "SC"
/****************************************************************************
* Field : RVCSR_MEICONTEXT_MRETEIRQ
* Description : If 1, enable restore of the preemption priority stack on
* `mret`. This bit is set on entering the external interrupt
* vector, cleared by `mret`, and cleared upon taking any trap
* other than an external interrupt.
*
* Provided `meicontext` is saved on entry to the external
* interrupt vector (before enabling preemption), is restored
* before exiting, and the standard software/timer IRQs are
* prevented from preempting (e.g. by using `clearts`), this flag
* allows the hardware to safely manage the preemption priority
* stack even when an external interrupt handler may take
* exceptions.
****************************************************************************/
#define RVCSR_MEICONTEXT_MRETEIRQ_RESET 0x0
#define RVCSR_MEICONTEXT_MRETEIRQ_BITS 0x00000001
#define RVCSR_MEICONTEXT_MRETEIRQ_MSB 0
#define RVCSR_MEICONTEXT_MRETEIRQ_LSB 0
#define RVCSR_MEICONTEXT_MRETEIRQ_ACCESS "RW"
/****************************************************************************
* Register : RVCSR_MSLEEP
* Description : M-mode sleep control register
****************************************************************************/
#define RVCSR_MSLEEP_OFFSET 0x00000bf0
#define RVCSR_MSLEEP_BITS 0x00000007
#define RVCSR_MSLEEP_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MSLEEP_SLEEPONBLOCK
* Description : Enter the deep sleep state configured by
* msleep.deepsleep/msleep.powerdown on a `h3.block` instruction,
* as well as a standard `wfi`. If this bit is clear, a `h3.block`
* is always implemented as a simple pipeline stall.
****************************************************************************/
#define RVCSR_MSLEEP_SLEEPONBLOCK_RESET 0x0
#define RVCSR_MSLEEP_SLEEPONBLOCK_BITS 0x00000004
#define RVCSR_MSLEEP_SLEEPONBLOCK_MSB 2
#define RVCSR_MSLEEP_SLEEPONBLOCK_LSB 2
#define RVCSR_MSLEEP_SLEEPONBLOCK_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MSLEEP_POWERDOWN
* Description : Release the external power request when going to sleep. The
* function of this is platform-defined -- it may do nothing, it
* may do something simple like clock-gating the fabric, or it may
* be tied to some complex system-level power controller.
*
* When waking, the processor reasserts its external power-up
* request, and will not fetch any instructions until the request
* is acknowledged. This may add considerable latency to the
* wakeup.
****************************************************************************/
#define RVCSR_MSLEEP_POWERDOWN_RESET 0x0
#define RVCSR_MSLEEP_POWERDOWN_BITS 0x00000002
#define RVCSR_MSLEEP_POWERDOWN_MSB 1
#define RVCSR_MSLEEP_POWERDOWN_LSB 1
#define RVCSR_MSLEEP_POWERDOWN_ACCESS "RW"
/****************************************************************************
* Field : RVCSR_MSLEEP_DEEPSLEEP
* Description : Deassert the processor clock enable when entering the sleep
* state. If a clock gate is instantiated, this allows most of the
* processor (everything except the power state machine and the
* interrupt and halt input registers) to be clock gated whilst
* asleep, which may reduce the sleep current. This adds one cycle
* to the wakeup latency.
****************************************************************************/
#define RVCSR_MSLEEP_DEEPSLEEP_RESET 0x0
#define RVCSR_MSLEEP_DEEPSLEEP_BITS 0x00000001
#define RVCSR_MSLEEP_DEEPSLEEP_MSB 0
#define RVCSR_MSLEEP_DEEPSLEEP_LSB 0
#define RVCSR_MSLEEP_DEEPSLEEP_ACCESS "RW"
/****************************************************************************
* Register : RVCSR_DMDATA0
* Description : The Debug Module's DATA0 register is mapped into
* Hazard3's CSR space so that the Debug Module can exchange
* data with the core by executing CSR access instructions
* (this is used to implementthe Abstract Access Register command).
* Only accessible in Debug Mode.
****************************************************************************/
#define RVCSR_DMDATA0_OFFSET 0x00000bff
#define RVCSR_DMDATA0_BITS 0xffffffff
#define RVCSR_DMDATA0_RESET 0x00000000
#define RVCSR_DMDATA0_MSB 31
#define RVCSR_DMDATA0_LSB 0
#define RVCSR_DMDATA0_ACCESS "RW"
/****************************************************************************
* Register : RVCSR_CYCLE
* Description : Read-only U-mode alias of mcycle, accessible when
* `mcounteren.cy` is set
****************************************************************************/
#define RVCSR_CYCLE_OFFSET 0x00000c00
#define RVCSR_CYCLE_BITS 0xffffffff
#define RVCSR_CYCLE_RESET 0x00000000
#define RVCSR_CYCLE_MSB 31
#define RVCSR_CYCLE_LSB 0
#define RVCSR_CYCLE_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_INSTRET
* Description : Read-only U-mode alias of minstret, accessible when
* `mcounteren.ir` is set
****************************************************************************/
#define RVCSR_INSTRET_OFFSET 0x00000c02
#define RVCSR_INSTRET_BITS 0xffffffff
#define RVCSR_INSTRET_RESET 0x00000000
#define RVCSR_INSTRET_MSB 31
#define RVCSR_INSTRET_LSB 0
#define RVCSR_INSTRET_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_CYCLEH
* Description : Read-only U-mode alias of mcycleh, accessible when
* `mcounteren.cy` is set
****************************************************************************/
#define RVCSR_CYCLEH_OFFSET 0x00000c80
#define RVCSR_CYCLEH_BITS 0xffffffff
#define RVCSR_CYCLEH_RESET 0x00000000
#define RVCSR_CYCLEH_MSB 31
#define RVCSR_CYCLEH_LSB 0
#define RVCSR_CYCLEH_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_INSTRETH
* Description : Read-only U-mode alias of minstreth, accessible when
* `mcounteren.ir` is set
****************************************************************************/
#define RVCSR_INSTRETH_OFFSET 0x00000c82
#define RVCSR_INSTRETH_BITS 0xffffffff
#define RVCSR_INSTRETH_RESET 0x00000000
#define RVCSR_INSTRETH_MSB 31
#define RVCSR_INSTRETH_LSB 0
#define RVCSR_INSTRETH_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_MVENDORID
* Description : Vendor ID
****************************************************************************/
#define RVCSR_MVENDORID_OFFSET 0x00000f11
#define RVCSR_MVENDORID_BITS 0xffffffff
#define RVCSR_MVENDORID_RESET 0x00000000
/****************************************************************************
* Field : RVCSR_MVENDORID_BANK
****************************************************************************/
#define RVCSR_MVENDORID_BANK_RESET "-"
#define RVCSR_MVENDORID_BANK_BITS 0xffffff80
#define RVCSR_MVENDORID_BANK_MSB 31
#define RVCSR_MVENDORID_BANK_LSB 7
#define RVCSR_MVENDORID_BANK_ACCESS "RO"
/****************************************************************************
* Field : RVCSR_MVENDORID_OFFSET
****************************************************************************/
#define RVCSR_MVENDORID_OFFSET_RESET "-"
#define RVCSR_MVENDORID_OFFSET_BITS 0x0000007f
#define RVCSR_MVENDORID_OFFSET_MSB 6
#define RVCSR_MVENDORID_OFFSET_LSB 0
#define RVCSR_MVENDORID_OFFSET_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_MARCHID
* Description : Architecture ID (Hazard3
****************************************************************************/
#define RVCSR_MARCHID_OFFSET 0x00000f12
#define RVCSR_MARCHID_BITS 0xffffffff
#define RVCSR_MARCHID_RESET 0x0000001b
#define RVCSR_MARCHID_MSB 31
#define RVCSR_MARCHID_LSB 0
#define RVCSR_MARCHID_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_MIMPID
* Description : Implementation ID
****************************************************************************/
#define RVCSR_MIMPID_OFFSET 0x00000f13
#define RVCSR_MIMPID_BITS 0xffffffff
#define RVCSR_MIMPID_RESET "-"
#define RVCSR_MIMPID_MSB 31
#define RVCSR_MIMPID_LSB 0
#define RVCSR_MIMPID_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_MHARTID
* Description : Hardware thread ID
* On RP2350, core 0 has a hart ID of 0, and core 1 has a hart ID
* of 1.
****************************************************************************/
#define RVCSR_MHARTID_OFFSET 0x00000f14
#define RVCSR_MHARTID_BITS 0xffffffff
#define RVCSR_MHARTID_RESET "-"
#define RVCSR_MHARTID_MSB 31
#define RVCSR_MHARTID_LSB 0
#define RVCSR_MHARTID_ACCESS "RO"
/****************************************************************************
* Register : RVCSR_MCONFIGPTR
* Description : Pointer to configuration data structure (hardwired to 0
****************************************************************************/
#define RVCSR_MCONFIGPTR_OFFSET 0x00000f15
#define RVCSR_MCONFIGPTR_BITS 0xffffffff
#define RVCSR_MCONFIGPTR_RESET 0x00000000
#define RVCSR_MCONFIGPTR_MSB 31
#define RVCSR_MCONFIGPTR_LSB 0
#define RVCSR_MCONFIGPTR_ACCESS "RO"
#endif /* __ARCH_RISCV_SRC_RP23XX_HARDWARE_RP23XX_HAZARD3_H */

79
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_ctrl.h Normal file
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@ -0,0 +1,79 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_ctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_CTRL_CSR_OFFSET 0x00000000
#define RP23XX_HSTX_CTRL_BIT_OFFSET(n) ((n) * 4 + 0x000004)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET 0x00000024
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET 0x00000028
/* Register definitions *****************************************************/
#define RP23XX_HSTX_CTRL_CSR (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_CSR_OFFSET)
#define RP23XX_HSTX_CTRL_BIT(n) (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_BIT_OFFSET(n))
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_CTRL_CSR_MASK (0xff1f1f73)
#define RP23XX_HSTX_CTRL_CSR_CLKDIV_MASK (0xf0000000)
#define RP23XX_HSTX_CTRL_CSR_CLKPHASE_MASK (0x0f000000)
#define RP23XX_HSTX_CTRL_CSR_N_SHIFTS_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_CSR_SHIFT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_SEL_MASK (0x00000060)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_MODE (1 << 4)
#define RP23XX_HSTX_CTRL_CSR_EXPAND_EN (1 << 1)
#define RP23XX_HSTX_CTRL_CSR_EN (1 << 0)
#define RP23XX_HSTX_CTRL_BIT_MASK (0x00031f1f)
#define RP23XX_HSTX_CTRL_BIT_CLK_MASK (1 << 25)
#define RP23XX_HSTX_CTRL_BIT_INV_MASK (1 << 24)
#define RP23XX_HSTX_CTRL_BIT_SEL_N_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_BIT_SEL_P_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_MASK (0x1f1f1f1f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MASK (0x1f000000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_MASK (0x00ffffff)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MASK (0x00e00000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_ROT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MASK (0x0000e000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_ROT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MASK (0x000000e0)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_ROT_MASK (0x0000001f)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_fifo.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_fifo.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_FIFO_STAT_OFFSET 0x00000000
#define RP23XX_HSTX_FIFO_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_HSTX_FIFO_STAT (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_STAT_OFFSET)
#define RP23XX_HSTX_FIFO_FIFO (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_FIFO_STAT_MASK (0x000007ff)
#define RP23XX_HSTX_FIFO_STAT_WOF (1 << 10)
#define RP23XX_HSTX_FIFO_STAT_EMPTY (1 << 9)
#define RP23XX_HSTX_FIFO_STAT_FULL (1 << 8)
#define RP23XX_HSTX_FIFO_STAT_LEVEL_MASK (0x000000ff)
#define RP23XX_HSTX_FIFO_FIFO_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_i2c.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_i2c.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_I2C_IC_CON_OFFSET 0x000000 /* I2C Control Register */
#define RP23XX_RV_I2C_IC_TAR_OFFSET 0x000004 /* I2C Target Address Register */
#define RP23XX_RV_I2C_IC_SAR_OFFSET 0x000008 /* I2C Slave Address Register */
#define RP23XX_RV_I2C_IC_DATA_CMD_OFFSET 0x000010 /* I2C Rx/Tx Data Buffer and Command Register */
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT_OFFSET 0x000014 /* Standard Speed I2C Clock SCL High Count Register */
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT_OFFSET 0x000018 /* Standard Speed I2C Clock SCL Low Count Register */
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT_OFFSET 0x00001c /* Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT_OFFSET 0x000020 /* Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */
#define RP23XX_RV_I2C_IC_INTR_STAT_OFFSET 0x00002c /* I2C Interrupt Status Register */
#define RP23XX_RV_I2C_IC_INTR_MASK_OFFSET 0x000030 /* I2C Interrupt Mask Register */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_OFFSET 0x000034 /* I2C Raw Interrupt Status Register */
#define RP23XX_RV_I2C_IC_RX_TL_OFFSET 0x000038 /* I2C Receive FIFO Threshold Register */
#define RP23XX_RV_I2C_IC_TX_TL_OFFSET 0x00003c /* I2C Transmit FIFO Threshold Register */
#define RP23XX_RV_I2C_IC_CLR_INTR_OFFSET 0x000040 /* Clear Combined and Individual Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER_OFFSET 0x000044 /* Clear RX_UNDER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_OVER_OFFSET 0x000048 /* Clear RX_OVER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_TX_OVER_OFFSET 0x00004c /* Clear TX_OVER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RD_REQ_OFFSET 0x000050 /* Clear RD_REQ Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT_OFFSET 0x000054 /* Clear TX_ABRT Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_DONE_OFFSET 0x000058 /* Clear RX_DONE Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY_OFFSET 0x00005c /* Clear ACTIVITY Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_STOP_DET_OFFSET 0x000060 /* Clear STOP_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_START_DET_OFFSET 0x000064 /* Clear START_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL_OFFSET 0x000068 /* Clear GEN_CALL Interrupt Register */
#define RP23XX_RV_I2C_IC_ENABLE_OFFSET 0x00006c /* I2C Enable Register */
#define RP23XX_RV_I2C_IC_STATUS_OFFSET 0x000070 /* I2C Status Register */
#define RP23XX_RV_I2C_IC_TXFLR_OFFSET 0x000074 /* I2C Transmit FIFO Level Register */
#define RP23XX_RV_I2C_IC_RXFLR_OFFSET 0x000078 /* I2C Receive FIFO Level Register */
#define RP23XX_RV_I2C_IC_SDA_HOLD_OFFSET 0x00007c /* I2C SDA Hold Time Length Register */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_OFFSET 0x000080 /* I2C Transmit Abort Source Register */
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x000084 /* Generate Slave Data NACK Register */
#define RP23XX_RV_I2C_IC_DMA_CR_OFFSET 0x000088 /* DMA Control Register */
#define RP23XX_RV_I2C_IC_DMA_TDLR_OFFSET 0x00008c /* DMA Transmit Data Level Register */
#define RP23XX_RV_I2C_IC_DMA_RDLR_OFFSET 0x000090 /* I2C Receive Data Level Register */
#define RP23XX_RV_I2C_IC_SDA_SETUP_OFFSET 0x000094 /* I2C SDA Setup Register */
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_OFFSET 0x000098 /* I2C ACK General Call Register */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_OFFSET 0x00009c /* I2C Enable Status Register */
#define RP23XX_RV_I2C_IC_FS_SPKLEN_OFFSET 0x0000a0 /* I2C SS, FS or FM+ spike suppression limit */
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET_OFFSET 0x0000a8 /* Clear RESTART_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_OFFSET 0x0000f4 /* Component Parameter Register 1 */
#define RP23XX_RV_I2C_IC_COMP_VERSION_OFFSET 0x0000f8 /* I2C Component Version Register */
#define RP23XX_RV_I2C_IC_COMP_TYPE_OFFSET 0x0000fc /* I2C Component Type Register */
/* Register definitions *****************************************************/
#define RP23XX_RV_I2C_IC_CON(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CON_OFFSET)
#define RP23XX_RV_I2C_IC_TAR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TAR_OFFSET)
#define RP23XX_RV_I2C_IC_SAR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SAR_OFFSET)
#define RP23XX_RV_I2C_IC_DATA_CMD(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DATA_CMD_OFFSET)
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SS_SCL_HCNT_OFFSET)
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SS_SCL_LCNT_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SCL_HCNT_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SCL_LCNT_OFFSET)
#define RP23XX_RV_I2C_IC_INTR_STAT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_INTR_STAT_OFFSET)
#define RP23XX_RV_I2C_IC_INTR_MASK(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_INTR_MASK_OFFSET)
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RAW_INTR_STAT_OFFSET)
#define RP23XX_RV_I2C_IC_RX_TL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RX_TL_OFFSET)
#define RP23XX_RV_I2C_IC_TX_TL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TX_TL_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_INTR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_INTR_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_UNDER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_OVER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_OVER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_TX_OVER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_TX_OVER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RD_REQ(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RD_REQ_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_TX_ABRT_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_DONE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_DONE_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_ACTIVITY_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_STOP_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_STOP_DET_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_START_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_START_DET_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_GEN_CALL_OFFSET)
#define RP23XX_RV_I2C_IC_ENABLE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ENABLE_OFFSET)
#define RP23XX_RV_I2C_IC_STATUS(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_STATUS_OFFSET)
#define RP23XX_RV_I2C_IC_TXFLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TXFLR_OFFSET)
#define RP23XX_RV_I2C_IC_RXFLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RXFLR_OFFSET)
#define RP23XX_RV_I2C_IC_SDA_HOLD(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SDA_HOLD_OFFSET)
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_OFFSET)
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_CR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_CR_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_TDLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_TDLR_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_RDLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_RDLR_OFFSET)
#define RP23XX_RV_I2C_IC_SDA_SETUP(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SDA_SETUP_OFFSET)
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_OFFSET)
#define RP23XX_RV_I2C_IC_ENABLE_STATUS(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ENABLE_STATUS_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SPKLEN(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SPKLEN_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RESTART_DET_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_PARAM_1_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_VERSION(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_VERSION_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_TYPE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_TYPE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE (1 << 10) /* Master issues the STOP_DET interrupt irrespective of whether master is active or not */
#define RP23XX_RV_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL (1 << 9) /* Hold bus when RX_FIFO is full */
#define RP23XX_RV_I2C_IC_CON_TX_EMPTY_CTRL (1 << 8) /* Controlled generation of TX_EMPTY interrupt */
#define RP23XX_RV_I2C_IC_CON_STOP_DET_IFADDRESSED (1 << 7) /* slave issues STOP_DET intr only if addressed */
#define RP23XX_RV_I2C_IC_CON_IC_SLAVE_DISABLE (1 << 6) /* Slave mode is disabled */
#define RP23XX_RV_I2C_IC_CON_IC_RESTART_EN (1 << 5) /* Master restart enabled */
#define RP23XX_RV_I2C_IC_CON_IC_10BITADDR_MASTER (1 << 4) /* Master 10Bit addressing mode */
#define RP23XX_RV_I2C_IC_CON_IC_10BITADDR_SLAVE (1 << 3) /* Slave 10Bit addressing */
#define RP23XX_RV_I2C_IC_CON_SPEED_SHIFT (1) /* These bits control at which speed the DW_apb_i2c operates */
#define RP23XX_RV_I2C_IC_CON_SPEED_MASK (0x03 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_STANDARD (0x1 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_FAST (0x2 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_HIGH (0x3 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_MASTER_MODE (1 << 0) /* Master mode is enabled */
#define RP23XX_RV_I2C_IC_TAR_SPECIAL (1 << 11) /* Enables programming of GENERAL_CALL or START_BYTE transmission */
#define RP23XX_RV_I2C_IC_TAR_GC_OR_START (1 << 10) /* START byte transmission */
#define RP23XX_RV_I2C_IC_TAR_MASK (0x3ff) /* This is the target address for any master transaction. */
#define RP23XX_RV_I2C_IC_SAR_MASK (0x3ff) /* The IC_SAR holds the slave address when the I2C is operating as a slave. */
#define RP23XX_RV_I2C_IC_DATA_CMD_FIRST_DATA_BYTE (1 << 11) /* Non sequential data byte received */
#define RP23XX_RV_I2C_IC_DATA_CMD_RESTART (1 << 10) /* Issue RESTART before this command */
#define RP23XX_RV_I2C_IC_DATA_CMD_STOP (1 << 9) /* Issue STOP after this command */
#define RP23XX_RV_I2C_IC_DATA_CMD_CMD (1 << 8) /* Master Read Command */
#define RP23XX_RV_I2C_IC_DATA_CMD_DAT_MASK (0xff) /* This register contains the data to be transmitted or received on the I2C bus. */
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD (1 << 13) /* R_MASTER_ON_HOLD interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RESTART_DET (1 << 12) /* R_RESTART_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_GEN_CALL (1 << 11) /* R_GEN_CALL interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_START_DET (1 << 10) /* R_START_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET (1 << 9) /* R_STOP_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_ACTIVITY (1 << 8) /* R_ACTIVITY interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_DONE (1 << 7) /* R_RX_DONE interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT (1 << 6) /* R_TX_ABRT interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RD_REQ (1 << 5) /* R_RD_REQ interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY (1 << 4) /* R_TX_EMPTY interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_OVER (1 << 3) /* R_TX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL (1 << 2) /* R_RX_FULL interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_OVER (1 << 1) /* R_RX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_UNDER (1 << 0) /* RX_UNDER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY (1 << 13) /* MASTER_ON_HOLD interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RESTART_DET (1 << 12) /* RESTART_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_GEN_CALL (1 << 11) /* GEN_CALL interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_START_DET (1 << 10) /* START_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_STOP_DET (1 << 9) /* STOP_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_ACTIVITY (1 << 8) /* ACTIVITY interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_DONE (1 << 7) /* RX_DONE interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_ABRT (1 << 6) /* TX_ABORT interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RD_REQ (1 << 5) /* RD_REQ interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_EMPTY (1 << 4) /* TX_EMPTY interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_OVER (1 << 3) /* TX_OVER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_FULL (1 << 2) /* RX_FULL interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_OVER (1 << 1) /* RX_OVER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_UNDER (1 << 0) /* RX_UNDER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD (1 << 13) /* MASTER_ON_HOLD interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RESTART_DET (1 << 12) /* RESTART_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_GEN_CALL (1 << 11) /* GEN_CALL interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_START_DET (1 << 10) /* START_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_STOP_DET (1 << 9) /* STOP_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_ACTIVITY (1 << 8) /* RAW_INTR_ACTIVITY interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_DONE (1 << 7) /* RX_DONE interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_ABRT (1 << 6) /* TX_ABRT interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RD_REQ (1 << 5) /* RD_REQ interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_EMPTY (1 << 4) /* TX_EMPTY interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_OVER (1 << 3) /* TX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_FULL (1 << 2) /* RX_FULL interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_OVER (1 << 1) /* RX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_UNDER (1 << 0) /* RX_UNDER interrupt is active */
#define RP23XX_RV_I2C_IC_RX_TL_RX_TL_MASK (0xff) /* Receive FIFO Threshold Level. */
#define RP23XX_RV_I2C_IC_TX_TL_TX_TL_MASK (0xff) /* Transmit FIFO Threshold Level. */
#define RP23XX_RV_I2C_IC_CLR_INTR_CLR_INTR (1 << 0) /* Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. */
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER (1 << 0) /* Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_RX_OVER_CLR_RX_OVER (1 << 0) /* Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_TX_OVER_CLR_TX_OVER (1 << 0) /* Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_RD_REQ_CLR_RD_REQ (1 << 0) /* Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT (1 << 0) /* Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. */
#define RP23XX_RV_I2C_IC_CLR_RX_DONE_CLR_RX_DONE (1 << 0) /* Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY (1 << 0) /* Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. */
#define RP23XX_RV_I2C_IC_CLR_STOP_DET_CLR_STOP_DET (1 << 0) /* Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_START_DET_CLR_START_DET (1 << 0) /* Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL (1 << 0) /* Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_ENABLE_TX_CMD_BLOCK (1 << 2) /* Tx Command execution blocked */
#define RP23XX_RV_I2C_IC_ENABLE_ABORT (1 << 1) /* ABORT operation in progress */
#define RP23XX_RV_I2C_IC_ENABLE_ENABLE (1 << 0) /* I2C is enabled */
#define RP23XX_RV_I2C_IC_STATUS_SLV_ACTIVITY (1 << 6) /* Slave not idle */
#define RP23XX_RV_I2C_IC_STATUS_MST_ACTIVITY (1 << 5) /* Master not idle */
#define RP23XX_RV_I2C_IC_STATUS_RFF (1 << 4) /* Rx FIFO is full */
#define RP23XX_RV_I2C_IC_STATUS_RFNE (1 << 3) /* Rx FIFO not empty */
#define RP23XX_RV_I2C_IC_STATUS_TFE (1 << 2) /* Tx FIFO is empty */
#define RP23XX_RV_I2C_IC_STATUS_TFNF (1 << 1) /* Tx FIFO not full */
#define RP23XX_RV_I2C_IC_STATUS_ACTIVITY (1 << 0) /* I2C is active */
#define RP23XX_RV_I2C_IC_TXFLR_TXFLR_MASK (0x1f) /* Transmit FIFO Level. */
#define RP23XX_RV_I2C_IC_RXFLR_RXFLR_MASK (0x1f) /* Receive FIFO Level. */
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SHIFT (16) /* Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. */
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MASK (0xff << RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SHIFT)
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MASK (0xffff) /* Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SHIFT (23) /* This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MASK (0x1ff << RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SHIFT)
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT (1 << 16) /* Transfer abort detected by master */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX (1 << 15) /* Slave trying to transmit to remote master in read mode */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST (1 << 14) /* Slave lost arbitration to remote master */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO (1 << 13) /* Slave flushes existing data in TX-FIFO upon getting read command */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ARB_LOST (1 << 12) /* Master or Slave-Transmitter lost arbitration */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS (1 << 11) /* User initiating master operation when MASTER disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT (1 << 10) /* Master trying to read in 10Bit addressing mode when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT (1 << 9) /* User trying to send START byte when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT (1 << 8) /* User trying to switch Master to HS mode when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET (1 << 7) /* ACK detected for START byte */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET (1 << 6) /* HS Master code ACKed in HS Mode */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ (1 << 5) /* GCALL is followed by read from bus */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK (1 << 4) /* GCALL not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK (1 << 3) /* Transmitted data not ACKed by addressed slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK (1 << 2) /* Byte 2 of 10Bit Address not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK (1 << 1) /* Byte 1 of 10Bit Address not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK (1 << 0) /* This abort is generated because of NOACK for 7-bit address */
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_NACK (1 << 0) /* Slave receiver generates NACK upon data reception only */
#define RP23XX_RV_I2C_IC_DMA_CR_TDMAE (1 << 1) /* Transmit FIFO DMA channel enabled */
#define RP23XX_RV_I2C_IC_DMA_CR_RDMAE (1 << 0) /* Receive FIFO DMA channel enabled */
#define RP23XX_RV_I2C_IC_DMA_TDLR_DMATDL_MASK (0x0f) /* Transmit Data Level. */
#define RP23XX_RV_I2C_IC_DMA_RDLR_DMARDL_MASK (0x0f) /* Receive Data Level. */
#define RP23XX_RV_I2C_IC_SDA_SETUP_SDA_SETUP_MASK (0xff) /* SDA Setup. */
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL (1 << 0) /* Generate ACK for a General Call */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST (1 << 2) /* Slave RX Data is lost */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (1 << 1) /* Slave is disabled when it is active */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_IC_EN (1 << 0) /* I2C enabled */
#define RP23XX_RV_I2C_IC_FS_SPKLEN_MASK (0xff) /* This register must be set before any I2C bus transaction can take place to ensure stable operation. */
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET (1 << 0) /* Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT (16) /* TX Buffer Depth = 16 */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MASK (0xff << RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT (8) /* RX Buffer Depth = 16 */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MASK (0xff << RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS (1 << 7) /* Encoded parameters not visible */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_HAS_DMA (1 << 6) /* DMA handshaking signals are enabled */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_INTR_IO (1 << 5) /* COMBINED Interrupt outputs */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES (1 << 4) /* Programmable count values for each mode. */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT (2) /* MAX SPEED MODE = FAST MODE */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MASK (0x03 << RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MASK (0x03) /* APB data bus width is 32 bits */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_intctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_TIMER0_IRQ_0 0
#define RP23XX_TIMER0_IRQ_1 1
#define RP23XX_TIMER0_IRQ_2 2
#define RP23XX_TIMER0_IRQ_3 3
#define RP23XX_TIMER1_IRQ_0 4
#define RP23XX_TIMER1_IRQ_1 5
#define RP23XX_TIMER1_IRQ_2 6
#define RP23XX_TIMER1_IRQ_3 7
#define RP23XX_RV_PWM_IRQ_WRAP_0 8
#define RP23XX_RV_PWM_IRQ_WRAP_1 9
#define RP23XX_DMA_IRQ_0 10
#define RP23XX_DMA_IRQ_1 11
#define RP23XX_DMA_IRQ_2 12
#define RP23XX_DMA_IRQ_3 13
#define RP23XX_USBCTRL_IRQ 14
#define RP23XX_PIO0_IRQ_0 15
#define RP23XX_PIO0_IRQ_1 16
#define RP23XX_PIO1_IRQ_0 17
#define RP23XX_PIO1_IRQ_1 18
#define RP23XX_PIO2_IRQ_0 19
#define RP23XX_PIO2_IRQ_1 20
#define RP23XX_IO_IRQ_BANK0 21
#define RP23XX_IO_IRQ_BANK0_NS 22
#define RP23XX_IO_IRQ_QSPI 23
#define RP23XX_IO_IRQ_QSPI_NS 24
#define RP23XX_SIO_IRQ_FIFO 25
#define RP23XX_SIO_IRQ_BELL 26
#define RP23XX_SIO_IRQ_FIFO_NS 27
#define RP23XX_SIO_IRQ_BELL_NS 28
#define RP23XX_SIO_IRQ_MTIMECMP 29
#define RP23XX_CLOCKS_IRQ 30
#define RP23XX_RV_SPI0_IRQ 31
#define RP23XX_RV_SPI1_IRQ 32
#define RP23XX_RV_UART0_IRQ 33
#define RP23XX_RV_UART1_IRQ 34
#define RP23XX_RV_ADC_IRQ_FIFO 35
#define RP23XX_RV_I2C0_IRQ 36
#define RP23XX_RV_I2C1_IRQ 37
#define RP23XX_OTP_IRQ 38
#define RP23XX_TRNG_IRQ 39
#define RP23XX_PROC0_IRQ_CTI 40
#define RP23XX_PROC1_IRQ_CTI 41
#define RP23XX_PLL_SYS_IRQ 42
#define RP23XX_PLL_USB_IRQ 43
#define RP23XX_POWMAN_IRQ_POW 44
#define RP23XX_POWMAN_IRQ_TIMER 45
#define RP23XX_SPARE_IRQ_0 46
#define RP23XX_SPARE_IRQ_1 47
#define RP23XX_SPARE_IRQ_2 48
#define RP23XX_SPARE_IRQ_3 49
#define RP23XX_SPARE_IRQ_4 50
#define RP23XX_SPARE_IRQ_5 51
#define RP23XX_IRQ_COUNT 52
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_bank0.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_bank0.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n) ((n) * 8 + 0x000000)
#define RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n) ((n) * 8 + 0x000004)
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000200)
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000208)
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000220)
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000228)
#define RP23XX_IO_BANK0_INTR_OFFSET(n) (((n) >> 3) * 4 + 0x000230)
#define RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000248)
#define RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000260)
#define RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000278)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n) (((n) >> 3) * 4 + 0x0002d8)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n) (((n) >> 3) * 4 + 0x0002f0)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n) (((n) >> 3) * 4 + 0x000308)
/* Register definitions *****************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n))
#define RP23XX_IO_BANK0_GPIO_CTRL(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n))
#define RP23XX_IO_BANK0_INTR(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_INTR_OFFSET(n))
#define RP23XX_IO_BANK0_PROC_INTE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p))
#define RP23XX_IO_BANK0_PROC_INTF(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p))
#define RP23XX_IO_BANK0_PROC_INTS(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n))
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p))
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p))
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n))
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS_IRQTOPROC (1 << 26) /* interrupt to processors, after override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_INFROMPAD (1 << 17) /* input signal from pad, before override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_OETOPAD (1 << 13) /* output enable to pad after register override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_OUTTOPAD (1 << 9) /* output signal to pad after register override is applied */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_SHIFT (28)
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* don't invert the interrupt */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* invert the interrupt */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt low */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt high */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_SHIFT (16)
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* don't invert the peri input */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* invert the peri input */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input low */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input high */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_SHIFT (14)
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from inverse of peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_DISABLE (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* disable output */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_ENABLE (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* enable output */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_SHIFT (12)
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from inverse of peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output low */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output high */
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK (0x1f)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_HSTX (0x0)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SPI (0x1)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART (0x2)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_I2C (0x3)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PWM (0x4)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SIO (0x5)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO0 (0x6)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO1 (0x7)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO2 (0x8)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_GPCK (0x9)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_USB (0xa)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART_AUX (0xb)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL (0x1f)
#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_HIGH(n) (1 << (((n) & 0x7) * 4 + 3))
#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_LOW(n) (1 << (((n) & 0x7) * 4 + 2))
#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_HIGH(n) (1 << (((n) & 0x7) * 4 + 1))
#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_LOW(n) (1 << (((n) & 0x7) * 4))
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_qspi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_QSPI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_OFFSET 0x00000000
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_OFFSET 0x00000004
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_OFFSET 0x00000008
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_OFFSET 0x0000000c
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET 0x00000010
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET 0x00000014
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET 0x00000018
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET 0x0000001c
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET 0x00000020
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET 0x00000024
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET 0x00000028
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET 0x0000002c
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET 0x00000030
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET 0x00000034
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET 0x00000038
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET 0x0000003c
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET 0x00000200
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET 0x00000204
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET 0x00000208
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET 0x0000020c
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET 0x00000210
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET 0x00000214
#define RP23XX_IO_QSPI_INTR_OFFSET 0x00000218
#define RP23XX_IO_QSPI_PROC0_INTE_OFFSET 0x0000021c
#define RP23XX_IO_QSPI_PROC0_INTF_OFFSET 0x00000220
#define RP23XX_IO_QSPI_PROC0_INTS_OFFSET 0x00000224
#define RP23XX_IO_QSPI_PROC1_INTE_OFFSET 0x00000228
#define RP23XX_IO_QSPI_PROC1_INTF_OFFSET 0x0000022c
#define RP23XX_IO_QSPI_PROC1_INTS_OFFSET 0x00000230
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_OFFSET 0x00000234
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_OFFSET 0x00000238
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_OFFSET 0x0000023c
/* Register definitions *****************************************************/
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_USBPHY_DP_STATUS_OFFSET)
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_USBPHY_DP_CTRL_OFFSET)
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_USBPHY_DM_STATUS_OFFSET)
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_USBPHY_DM_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET)
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET)
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET)
#define RP23XX_IO_QSPI_INTR (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_INTR_OFFSET)
#define RP23XX_IO_QSPI_PROC0_INTE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC0_INTE_OFFSET)
#define RP23XX_IO_QSPI_PROC0_INTF (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC0_INTF_OFFSET)
#define RP23XX_IO_QSPI_PROC0_INTS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC0_INTS_OFFSET)
#define RP23XX_IO_QSPI_PROC1_INTE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC1_INTE_OFFSET)
#define RP23XX_IO_QSPI_PROC1_INTF (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC1_INTF_OFFSET)
#define RP23XX_IO_QSPI_PROC1_INTS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_PROC1_INTS_OFFSET)
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_DORMANT_WAKE_INTE_OFFSET)
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_DORMANT_WAKE_INTF_OFFSET)
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS (RP23XX_IO_QSPI_BASE + RP23XX_IO_QSPI_DORMANT_WAKE_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_MASK 0x04022200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MASK 0x04000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MASK 0x00020000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MASK 0x00002000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MASK 0x00000200
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_MASK 0x3003f01f
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MASK 0x30000000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MASK 0x00030000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MASK 0x0000c000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MASK 0x00003000
#define RP23XX_IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MASK 0x0000001f
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_MASK 0x000000ff
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_MASK 0x00000080
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_MASK 0x00000040
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_MASK 0x00000020
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_MASK 0x00000010
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_MASK 0x00000008
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_MASK 0x00000004
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_MASK 0x00000002
#define RP23XX_IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_MASK 0x00000001
#define RP23XX_IO_QSPI_INTR_MASK 0xffffffff
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC0_INTE_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC0_INTF_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC0_INTS_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC1_INTE_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC1_INTF_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_PROC1_INTS_MASK 0xffffffff
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_MASK 0xffffffff
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_MASK 0xffffffff
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_MASK 0xffffffff
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MASK 0x80000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MASK 0x40000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MASK 0x20000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MASK 0x10000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MASK 0x08000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MASK 0x04000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MASK 0x02000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MASK 0x01000000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MASK 0x00800000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MASK 0x00400000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MASK 0x00200000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MASK 0x00100000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MASK 0x00080000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MASK 0x00040000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MASK 0x00020000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MASK 0x00010000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MASK 0x00008000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MASK 0x00004000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MASK 0x00002000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MASK 0x00001000
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MASK 0x00000800
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MASK 0x00000400
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MASK 0x00000200
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MASK 0x00000100
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_MASK 0x00000080
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_MASK 0x00000040
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_MASK 0x00000020
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_MASK 0x00000010
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_MASK 0x00000008
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_MASK 0x00000004
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_MASK 0x00000002
#define RP23XX_IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_MASK 0x00000001
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_QSPI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "riscv_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_FLASH_BASE 0x10000000 /* -0x001fffff: FLASH memory space (2048KB) */
#define RP23XX_SRAM_BASE 0x20000000 /* -0x20041fff: SRAM memory space (520KB) */
#define RP23XX_SYSINFO_BASE 0x40000000
#define RP23XX_SYSCFG_BASE 0x40008000 /* Register block for various chip control signals */
#define RP23XX_CLOCKS_BASE 0x40010000
#define RP23XX_RESETS_BASE 0x40020000
#define RP23XX_PSM_BASE 0x40018000
#define RP23XX_IO_BANK0_BASE 0x40028000
#define RP23XX_IO_QSPI_BASE 0x40030000
#define RP23XX_PADS_BANK0_BASE 0x40038000
#define RP23XX_PADS_QSPI_BASE 0x40040000
#define RP23XX_XOSC_BASE 0x40048000 /* Controls the crystal oscillator */
#define RP23XX_PLL_SYS_BASE 0x40050000
#define RP23XX_PLL_USB_BASE 0x40058000
#define RP23XX_BUSCTRL_BASE 0x40068000 /* Register block for busfabric control signals and performance counters */
#define RP23XX_RV_UART0_BASE 0x40070000
#define RP23XX_RV_UART1_BASE 0x40078000
#define RP23XX_RV_UART_BASE(n) (0x40070000 + (n) * 0x8000)
#define RP23XX_RV_SPI0_BASE 0x40080000
#define RP23XX_RV_SPI1_BASE 0x40088000
#define RP23XX_RV_SPI_BASE(n) (0x40080000 + (n) * 0x8000)
#define RP23XX_RV_I2C0_BASE 0x40090000 /* DW_apb_i2c address block */
#define RP23XX_RV_I2C1_BASE 0x40098000 /* DW_apb_i2c address block */
#define RP23XX_RV_I2C_BASE(n) (0x40090000 + (n) * 0x8000)
#define RP23XX_RV_ADC_BASE 0x400a0000 /* Control and data interface to SAR ADC */
#define RP23XX_RV_PWM_BASE 0x400a8000 /* Simple PWM */
#define RP23XX_TIMER0_BASE 0x400b0000
#define RP23XX_TIMER1_BASE 0x400b8000
#define RP23XX_TIMER_BASE(n) (0x400b0000 + (n) * 0x8000)
#define RP23XX_HSTX_CTRL_BASE 0x400c0000
#define RP23XX_XIP_CTRL_BASE 0x400c8000 /* QSPI flash execute-in-place block */
#define RP23XX_XIP_QMI_BASE 0x400d0000
#define RP23XX_WATCHDOG_BASE 0x400d8000
#define RP23XX_BOOTRAM_BASE 0x400e0000
#define RP23XX_ROSC_BASE 0x400e8000
#define RP23XX_TRNG_BASE 0x400f0000
#define RP23XX_SHA256_BASE 0x400f8000
#define RP23XX_POWMAN_BASE 0x40100000 /* Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use */
#define RP23XX_TICKS_BASE 0x40108000
#define RP23XX_OTP_BASE 0x40120000
#define RP23XX_OTP_DATA_BASE 0x40130000
#define RP23XX_OTP_DATA_RAW_BASE 0x40134000
#define RP23XX_OTP_DATA_GUARDED_BASE 0x40138000
#define RP23XX_OTP_DATA_RAW_GUARDED_BASE 0x4013c000
#define RP23XX_DFT_BASE 0x40150000
#define RP23XX_GLITCH_DETECTOR_BASE 0x40158000
#define RP23XX_OTP_BASE 0x40120000
#define RP23XX_TBMAN_BASE 0x40160000 /* Testbench manager. Allows the programmer to know what platform their software is running on. */
#define RP23XX_DMA_BASE 0x50000000 /* DMA with separate read and write masters */
#define RP23XX_USBCTRL_DPSRAM_BASE 0x50100000 /* USB Dual Port SRAM */
#define RP23XX_USBCTRL_REGS_BASE 0x50110000 /* USB FS/LS controller device registers */
#define RP23XX_PIO0_BASE 0x50200000 /* Programmable IO block */
#define RP23XX_PIO1_BASE 0x50300000 /* Programmable IO block */
#define RP23XX_PIO2_BASE 0x50400000 /* Programmable IO block */
#define RP23XX_PIO_BASE(n) (0x50200000 + (n) * 0x100000)
#define RP23XX_XIP_AUX_BASE 0x50500000
#define RP23XX_HSTX_FIFO_BASE 0x50600000
#define RP23XX_CORESIGHT_TRACE_BASE 0x50700000
#define RP23XX_SIO_BASE 0xd0000000 /* Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. */
#define RP23XX_SIO_NONSEC_BASE 0xd0020000
#define RP23XX_PPB_BASE 0xe0000000
#define RP23XX_PPB_NONSEC_BASE 0xe0020000
#define RP23XX_EPPB_BASE 0xe0080000
#define RP23XX_ATOMIC_XOR_REG_OFFSET 0x1000
#define RP23XX_ATOMIC_SET_REG_OFFSET 0x2000
#define RP23XX_ATOMIC_CLR_REG_OFFSET 0x3000
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#define RP23XX_IDLESTACK_BASE (uintptr_t)_ebss
#else
#define RP23XX_IDLESTACK_BASE _ebss
#endif
#define RP23XX_IDLE_STACK (RP23XX_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
# define xorbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_XOR_REG_OFFSET)
# define setbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_SET_REG_OFFSET)
# define clrbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_CLR_REG_OFFSET)
# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_otp.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_OTP_SW_LOCK_OFFSET(n) (0x000000 + (n) * 4)
#define RP23XX_OTP_SBPI_INSTR_OFFSET 0x00000100
#define RP23XX_OTP_SBPI_WDATA_0_OFFSET 0x00000104
#define RP23XX_OTP_SBPI_WDATA_1_OFFSET 0x00000108
#define RP23XX_OTP_SBPI_WDATA_2_OFFSET 0x0000010c
#define RP23XX_OTP_SBPI_WDATA_3_OFFSET 0x00000110
#define RP23XX_OTP_SBPI_RDATA_0_OFFSET 0x00000114
#define RP23XX_OTP_SBPI_RDATA_1_OFFSET 0x00000118
#define RP23XX_OTP_SBPI_RDATA_2_OFFSET 0x0000011c
#define RP23XX_OTP_SBPI_RDATA_3_OFFSET 0x00000120
#define RP23XX_OTP_SBPI_STATUS_OFFSET 0x00000124
#define RP23XX_OTP_USR_OFFSET 0x00000128
#define RP23XX_OTP_DBG_OFFSET 0x0000012c
#define RP23XX_OTP_BIST_OFFSET 0x00000134
#define RP23XX_OTP_CRT_KEY_W0_OFFSET 0x00000138
#define RP23XX_OTP_CRT_KEY_W1_OFFSET 0x0000013c
#define RP23XX_OTP_CRT_KEY_W2_OFFSET 0x00000140
#define RP23XX_OTP_CRT_KEY_W3_OFFSET 0x00000144
#define RP23XX_OTP_CRITICAL_OFFSET 0x00000148
#define RP23XX_OTP_KEY_VALID_OFFSET 0x0000014c
#define RP23XX_OTP_DEBUGEN_OFFSET 0x00000150
#define RP23XX_OTP_DEBUGEN_LOCK_OFFSET 0x00000154
#define RP23XX_OTP_ARCHSEL_OFFSET 0x00000158
#define RP23XX_OTP_ARCHSEL_STATUS_OFFSET 0x0000015c
#define RP23XX_OTP_BOOTDIS_OFFSET 0x00000160
#define RP23XX_OTP_INTR_OFFSET 0x00000164
#define RP23XX_OTP_INTE_OFFSET 0x00000168
#define RP23XX_OTP_INTF_OFFSET 0x0000016c
#define RP23XX_OTP_INTS_OFFSET 0x00000170
/* Register definitions *****************************************************/
#define RP23XX_OTP_SW_LOCK(n) (RP23XX_OTP_BASE + RP23XX_OTP_SW_LOCK_OFFSET(n))
#define RP23XX_OTP_SBPI_INSTR (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_INSTR_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_0 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_0_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_1 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_1_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_2 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_2_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_3 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_3_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_0 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_0_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_1 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_1_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_2 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_2_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_3 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_3_OFFSET)
#define RP23XX_OTP_SBPI_STATUS (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_STATUS_OFFSET)
#define RP23XX_OTP_USR (RP23XX_OTP_BASE + RP23XX_OTP_USR_OFFSET)
#define RP23XX_OTP_DBG (RP23XX_OTP_BASE + RP23XX_OTP_DBG_OFFSET)
#define RP23XX_OTP_BIST (RP23XX_OTP_BASE + RP23XX_OTP_BIST_OFFSET)
#define RP23XX_OTP_CRT_KEY_W0 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W0_OFFSET)
#define RP23XX_OTP_CRT_KEY_W1 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W1_OFFSET)
#define RP23XX_OTP_CRT_KEY_W2 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W2_OFFSET)
#define RP23XX_OTP_CRT_KEY_W3 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W3_OFFSET)
#define RP23XX_OTP_CRITICAL (RP23XX_OTP_BASE + RP23XX_OTP_CRITICAL_OFFSET)
#define RP23XX_OTP_KEY_VALID (RP23XX_OTP_BASE + RP23XX_OTP_KEY_VALID_OFFSET)
#define RP23XX_OTP_DEBUGEN (RP23XX_OTP_BASE + RP23XX_OTP_DEBUGEN_OFFSET)
#define RP23XX_OTP_DEBUGEN_LOCK (RP23XX_OTP_BASE + RP23XX_OTP_DEBUGEN_LOCK_OFFSET)
#define RP23XX_OTP_ARCHSEL (RP23XX_OTP_BASE + RP23XX_OTP_ARCHSEL_OFFSET)
#define RP23XX_OTP_ARCHSEL_STATUS (RP23XX_OTP_BASE + RP23XX_OTP_ARCHSEL_STATUS_OFFSET)
#define RP23XX_OTP_BOOTDIS (RP23XX_OTP_BASE + RP23XX_OTP_BOOTDIS_OFFSET)
#define RP23XX_OTP_INTR (RP23XX_OTP_BASE + RP23XX_OTP_INTR_OFFSET)
#define RP23XX_OTP_INTE (RP23XX_OTP_BASE + RP23XX_OTP_INTE_OFFSET)
#define RP23XX_OTP_INTF (RP23XX_OTP_BASE + RP23XX_OTP_INTF_OFFSET)
#define RP23XX_OTP_INTS (RP23XX_OTP_BASE + RP23XX_OTP_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_OTP_SW_LOCK_MASK 0x0000000f
#define RP23XX_OTP_SW_LOCK_NSEC_MASK 0x0000000c
#define RP23XX_OTP_SW_LOCK_SEC_MASK 0x00000003
#define RP23XX_OTP_SBPI_INSTR_MASK 0x7fffffff
#define RP23XX_OTP_SBPI_INSTR_EXEC (1 << 30)
#define RP23XX_OTP_SBPI_INSTR_IS_WR (1 << 29)
#define RP23XX_OTP_SBPI_INSTR_HAS_PAYLOAD (1 << 28)
#define RP23XX_OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_MASK 0x0f000000
#define RP23XX_OTP_SBPI_INSTR_TARGET_MASK 0x00ff0000
#define RP23XX_OTP_SBPI_INSTR_CMD_MASK 0x0000ff00
#define RP23XX_OTP_SBPI_INSTR_SHORT_WDATA_MASK 0x000000ff
#define RP23XX_OTP_SBPI_STATUS_MASK 0x00ff1111
#define RP23XX_OTP_SBPI_STATUS_MISO_MASK 0x00ff0000
#define RP23XX_OTP_SBPI_STATUS_FLAG (1 << 12)
#define RP23XX_OTP_SBPI_STATUS_INSTR_MISS (1 << 8)
#define RP23XX_OTP_SBPI_STATUS_INSTR_DONE (1 << 4)
#define RP23XX_OTP_SBPI_STATUS_RDATA_VLD (1 << 0)
#define RP23XX_OTP_USR_MASK 0x00000011
#define RP23XX_OTP_USR_PD (1 << 4)
#define RP23XX_OTP_USR_DCTRL (1 << 0)
#define RP23XX_OTP_DBG_MASK 0x000010ff
#define RP23XX_OTP_DBG_CUSTOMER_RMA_FLAG (1 << 12)
#define RP23XX_OTP_DBG_PSM_STATE_MASK 0x000000f0
#define RP23XX_OTP_DBG_ROSC_UP (1 << 3)
#define RP23XX_OTP_DBG_ROSC_UP_SEEN (1 << 2)
#define RP23XX_OTP_DBG_BOOT_DONE (1 << 1)
#define RP23XX_OTP_DBG_PSM_DONE (1 << 0)
#define RP23XX_OTP_BIST_MASK 0x7fff1fff
#define RP23XX_OTP_BIST_CNT_FAIL (1 << 30)
#define RP23XX_OTP_BIST_CNT_CLR (1 << 29)
#define RP23XX_OTP_BIST_CNT_ENA (1 << 28)
#define RP23XX_OTP_BIST_CNT_MAX_MASK 0x0fff0000
#define RP23XX_OTP_BIST_CNT_MASK 0x00001fff
#define RP23XX_OTP_CRITICAL_MASK 0x0003007f
#define RP23XX_OTP_CRITICAL_RISCV_DISABLE (1 << 17)
#define RP23XX_OTP_CRITICAL_ARM_DISABLE (1 << 16)
#define RP23XX_OTP_CRITICAL_GLITCH_DETECTOR_SENS_MASK 0x00000060
#define RP23XX_OTP_CRITICAL_GLITCH_DETECTOR_ENABLE (1 << 4)
#define RP23XX_OTP_CRITICAL_DEFAULT_ARCHSEL (1 << 3)
#define RP23XX_OTP_CRITICAL_DEBUG_DISABLE (1 << 2)
#define RP23XX_OTP_CRITICAL_SECURE_DEBUG_DISABLE (1 << 1)
#define RP23XX_OTP_CRITICAL_SECURE_BOOT_ENABLE (1 << 0)
#define RP23XX_OTP_KEY_VALID_MASK 0x000000ff
#define RP23XX_OTP_DEBUGEN_MASK 0x0000010f
#define RP23XX_OTP_DEBUGEN_MISC (1 << 8)
#define RP23XX_OTP_DEBUGEN_PROC1_SECURE (1 << 3)
#define RP23XX_OTP_DEBUGEN_PROC1 (1 << 2)
#define RP23XX_OTP_DEBUGEN_PROC0_SECURE (1 << 1)
#define RP23XX_OTP_DEBUGEN_PROC0 (1 << 0)
#define RP23XX_OTP_DEBUGEN_LOCK_MASK 0x0000010f
#define RP23XX_OTP_DEBUGEN_LOCK_MISC (1 << 8)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC1_SECURE (1 << 3)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC1 (1 << 2)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC0_SECURE (1 << 1)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC0 (1 << 0)
#define RP23XX_OTP_ARCHSEL_MASK 0x00000003
#define RP23XX_OTP_ARCHSEL_CORE1 (1 << 1)
#define RP23XX_OTP_ARCHSEL_CORE0 (1 << 0)
#define RP23XX_OTP_ARCHSEL_STATUS_MASK 0x00000003
#define RP23XX_OTP_ARCHSEL_STATUS_CORE1 (1 << 1)
#define RP23XX_OTP_ARCHSEL_STATUS_CORE0 (1 << 0)
#define RP23XX_OTP_BOOTDIS_MASK 0x00000003
#define RP23XX_OTP_BOOTDIS_NEXT (1 << 1)
#define RP23XX_OTP_BOOTDIS_NOW (1 << 0)
#define RP23XX_OTP_INTR_MASK 0x0000001f
#define RP23XX_OTP_INTR_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTR_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTR_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTR_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTR_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTE_MASK 0x0000001f
#define RP23XX_OTP_INTE_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTE_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTE_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTE_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTE_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTF_MASK 0x0000001f
#define RP23XX_OTP_INTF_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTF_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTF_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTF_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTF_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTS_MASK 0x0000001f
#define RP23XX_OTP_INTS_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTS_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTS_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTS_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTS_SBPI_FLAG_N (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_bank0.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x000000 /* Voltage select. Per bank control */
#define RP23XX_PADS_BANK0_GPIO_OFFSET(n) ((n) * 4 + 0x000004) /* Pad control register */
#define RP23XX_PADS_BANK0_SWCLK_OFFSET 0x0000c4 /* Pad control register */
#define RP23XX_PADS_BANK0_SWD_OFFSET 0x0000c8 /* Pad control register */
/* Register definitions *****************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_VOLTAGE_SELECT_OFFSET)
#define RP23XX_PADS_BANK0_GPIO(n) (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_GPIO_OFFSET(n))
#define RP23XX_PADS_BANK0_SWCLK (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_SWCLK_OFFSET)
#define RP23XX_PADS_BANK0_SWD (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_SWD_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT_1_8V (1 << 0) /* Set voltage to 1.8V (DVDD <= 1V8) */
#define RP23XX_PADS_BANK0_GPIO_ISO (1 << 8) /* Pad isolation control. Remove this once the pad is configured by software */
#define RP23XX_PADS_BANK0_GPIO_OD (1 << 7) /* Output disable. Has priority over output enable from peripherals */
#define RP23XX_PADS_BANK0_GPIO_IE (1 << 6) /* Input enable */
#define RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT (4) /* Drive strength */
#define RP23XX_PADS_BANK0_GPIO_DRIVE_MASK (0x03 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_2MA (0x0 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_4MA (0x1 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_8MA (0x2 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_12MA (0x3 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_PUE (1 << 3) /* Pull up enable */
#define RP23XX_PADS_BANK0_GPIO_PDE (1 << 2) /* Pull down enable */
#define RP23XX_PADS_BANK0_GPIO_SCHMITT (1 << 1) /* Enable schmitt trigger */
#define RP23XX_PADS_BANK0_GPIO_SLEWFAST (1 << 0) /* Slew rate control. 1 = Fast, 0 = Slow */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_qspi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018
/* Register definitions *****************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_VOLTAGE_SELECT_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_SLEWFAST (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PIO_CTRL_OFFSET 0x000000 /* PIO control register */
#define RP23XX_PIO_FSTAT_OFFSET 0x000004 /* FIFO status register */
#define RP23XX_PIO_FDEBUG_OFFSET 0x000008 /* FIFO debug register */
#define RP23XX_PIO_FLEVEL_OFFSET 0x00000c /* FIFO levels */
#define RP23XX_PIO_TXF_OFFSET(m) (0x000010 + (m) * 4) /* Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. */
#define RP23XX_PIO_RXF_OFFSET(m) (0x000020 + (m) * 4) /* Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. */
#define RP23XX_PIO_IRQ_OFFSET 0x000030 /* Interrupt request register. Write 1 to clear */
#define RP23XX_PIO_IRQ_FORCE_OFFSET 0x000034 /* Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. */
#define RP23XX_PIO_INPUT_SYNC_BYPASS_OFFSET 0x000038 /* There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. */
#define RP23XX_PIO_DBG_PADOUT_OFFSET 0x00003c /* Read to sample the pad output values PIO is currently driving to the GPIOs. */
#define RP23XX_PIO_DBG_PADOE_OFFSET 0x000040 /* Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. */
#define RP23XX_PIO_DBG_CFGINFO_OFFSET 0x000044 /* The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. */
#define RP23XX_PIO_INSTR_MEM_OFFSET(m) (0x000048 + (m) * 4) /* Write-only access to instruction memory location m */
#define RP23XX_PIO_SM_CLKDIV_OFFSET(m) (0x0000c8 + (m) * 0x18) /* Clock divider register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */
#define RP23XX_PIO_SM_EXECCTRL_OFFSET(m) (0x0000cc + (m) * 0x18) /* Execution/behavioural settings for state machine 0 */
#define RP23XX_PIO_SM_SHIFTCTRL_OFFSET(m) (0x0000d0 + (m) * 0x18) /* Control behaviour of the input/output shift registers for state machine 0 */
#define RP23XX_PIO_SM_ADDR_OFFSET(m) (0x0000d4 + (m) * 0x18) /* Current instruction address of state machine 0 */
#define RP23XX_PIO_SM_INSTR_OFFSET(m) (0x0000d8 + (m) * 0x18) /* Instruction currently being executed by state machine 0 Write to execute an instruction immediately (including jumps) and then resume execution. */
#define RP23XX_PIO_SM_PINCTRL_OFFSET(m) (0x0000dc + (m) * 0x18) /* State machine pin control */
#define RP23XX_PIO_RXF_PUTGET0_OFFSET(m) (0x000128 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET1_OFFSET(m) (0x00012c + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET2_OFFSET(m) (0x000130 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET3_OFFSET(m) (0x000134 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_GPIOBASE_OFFSET 0x000168 /* Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable) */
#define RP23XX_PIO_INTR_OFFSET 0x00016c /* Raw Interrupts */
#define RP23XX_PIO_IRQ0_INTE_OFFSET 0x000170 /* Interrupt Enable for irq0 */
#define RP23XX_PIO_IRQ0_INTF_OFFSET 0x000174 /* Interrupt Force for irq0 */
#define RP23XX_PIO_IRQ0_INTS_OFFSET 0x000178 /* Interrupt status after masking & forcing for irq0 */
#define RP23XX_PIO_IRQ1_INTE_OFFSET 0x00017c /* Interrupt Enable for irq1 */
#define RP23XX_PIO_IRQ1_INTF_OFFSET 0x000180 /* Interrupt Force for irq1 */
#define RP23XX_PIO_IRQ1_INTS_OFFSET 0x000184 /* Interrupt status after masking & forcing for irq1 */
/* Register definitions *****************************************************/
#define RP23XX_PIO_CTRL(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_CTRL_OFFSET)
#define RP23XX_PIO_FSTAT(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FSTAT_OFFSET)
#define RP23XX_PIO_FDEBUG(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FDEBUG_OFFSET)
#define RP23XX_PIO_FLEVEL(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FLEVEL_OFFSET)
#define RP23XX_PIO_TXF(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_TXF_OFFSET(m))
#define RP23XX_PIO_RXF(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_OFFSET(m))
#define RP23XX_PIO_IRQ(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_IRQ_OFFSET)
#define RP23XX_PIO_IRQ_FORCE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_IRQ_FORCE_OFFSET)
#define RP23XX_PIO_INPUT_SYNC_BYPASS(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_INPUT_SYNC_BYPASS_OFFSET)
#define RP23XX_PIO_DBG_PADOUT(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_PADOUT_OFFSET)
#define RP23XX_PIO_DBG_PADOE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_PADOE_OFFSET)
#define RP23XX_PIO_DBG_CFGINFO(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_CFGINFO_OFFSET)
#define RP23XX_PIO_INSTR_MEM(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_INSTR_MEM_OFFSET(m))
#define RP23XX_PIO_SM_CLKDIV(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_CLKDIV_OFFSET(m))
#define RP23XX_PIO_SM_EXECCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_EXECCTRL_OFFSET(m))
#define RP23XX_PIO_SM_SHIFTCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_SHIFTCTRL_OFFSET(m))
#define RP23XX_PIO_SM_ADDR(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_ADDR_OFFSET(m))
#define RP23XX_PIO_SM_INSTR(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_INSTR_OFFSET(m))
#define RP23XX_PIO_SM_PINCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_PINCTRL_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET0(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET0_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET1(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET1_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET2(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET2_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET3(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET3_OFFSET(m))
#define RP23XX_PIO_GPIOBASE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_GPIOBASE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PIO_CTRL_NEXTPREV_CLKDIV_RESTART (1 << 26) /* Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers */
#define RP23XX_PIO_CTRL_NEXTPREV_SM_DISABLE (1 << 25) /* Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers */
#define RP23XX_PIO_CTRL_NEXTPREV_SM_ENABLE (1 << 24) /* Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence */
#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT (20) /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
#define RP23XX_PIO_NEXT_PIO_MASK_MASK (0xf)
#define RP23XX_PIO_PREV_PIO_MASK_SHIFT (16) /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
#define RP23XX_PIO_PREV_PIO_MASK_MASK (0xf)
#define RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT (8) /* Force clock dividers to restart their count and clear fractional accumulators. Restart multiple dividers to synchronise them. */
#define RP23XX_PIO_CTRL_CLKDIV_RESTART_MASK (0x0f << RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT)
#define RP23XX_PIO_CTRL_SM_RESTART_SHIFT (4) /* Clear internal SM state which is otherwise difficult to access (e.g. shift counters). Self-clearing. */
#define RP23XX_PIO_CTRL_SM_RESTART_MASK (0x0f << RP23XX_PIO_CTRL_SM_RESTART_SHIFT)
#define RP23XX_PIO_CTRL_SM_ENABLE_MASK (0x0f) /* Enable state machine */
#define RP23XX_PIO_FSTAT_TXEMPTY_SHIFT (24) /* State machine TX FIFO is empty */
#define RP23XX_PIO_FSTAT_TXEMPTY_MASK (0x0f << RP23XX_PIO_FSTAT_TXEMPTY_SHIFT)
#define RP23XX_PIO_FSTAT_TXFULL_SHIFT (16) /* State machine TX FIFO is full */
#define RP23XX_PIO_FSTAT_TXFULL_MASK (0x0f << RP23XX_PIO_FSTAT_TXFULL_SHIFT)
#define RP23XX_PIO_FSTAT_RXEMPTY_SHIFT (8) /* State machine RX FIFO is empty */
#define RP23XX_PIO_FSTAT_RXEMPTY_MASK (0x0f << RP23XX_PIO_FSTAT_RXEMPTY_SHIFT)
#define RP23XX_PIO_FSTAT_RXFULL_SHIFT (0) /* State machine RX FIFO is full */
#define RP23XX_PIO_FSTAT_RXFULL_MASK (0x0f) /* State machine RX FIFO is full */
#define RP23XX_PIO_FDEBUG_TXSTALL_SHIFT (24) /* State machine has stalled on empty TX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_TXSTALL_MASK (0x0f << RP23XX_PIO_FDEBUG_TXSTALL_SHIFT)
#define RP23XX_PIO_FDEBUG_TXOVER_SHIFT (16) /* TX FIFO overflow has occurred. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_TXOVER_MASK (0x0f << RP23XX_PIO_FDEBUG_TXOVER_SHIFT)
#define RP23XX_PIO_FDEBUG_RXUNDER_SHIFT (8) /* RX FIFO underflow has occurred. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_RXUNDER_MASK (0x0f << RP23XX_PIO_FDEBUG_RXUNDER_SHIFT)
#define RP23XX_PIO_FDEBUG_RXSTALL_SHIFT (0) /* State machine has stalled on full RX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_RXSTALL_MASK (0x0f) /* State machine has stalled on full RX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FLEVEL_RX3_SHIFT (28)
#define RP23XX_PIO_FLEVEL_RX3_MASK (0x0f << RP23XX_PIO_FLEVEL_RX3_SHIFT)
#define RP23XX_PIO_FLEVEL_TX3_SHIFT (24)
#define RP23XX_PIO_FLEVEL_TX3_MASK (0x0f << RP23XX_PIO_FLEVEL_TX3_SHIFT)
#define RP23XX_PIO_FLEVEL_RX2_SHIFT (20)
#define RP23XX_PIO_FLEVEL_RX2_MASK (0x0f << RP23XX_PIO_FLEVEL_RX2_SHIFT)
#define RP23XX_PIO_FLEVEL_TX2_SHIFT (16)
#define RP23XX_PIO_FLEVEL_TX2_MASK (0x0f << RP23XX_PIO_FLEVEL_TX2_SHIFT)
#define RP23XX_PIO_FLEVEL_RX1_SHIFT (12)
#define RP23XX_PIO_FLEVEL_RX1_MASK (0x0f << RP23XX_PIO_FLEVEL_RX1_SHIFT)
#define RP23XX_PIO_FLEVEL_TX1_SHIFT (8)
#define RP23XX_PIO_FLEVEL_TX1_MASK (0x0f << RP23XX_PIO_FLEVEL_TX1_SHIFT)
#define RP23XX_PIO_FLEVEL_RX0_SHIFT (4)
#define RP23XX_PIO_FLEVEL_RX0_MASK (0x0f << RP23XX_PIO_FLEVEL_RX0_SHIFT)
#define RP23XX_PIO_FLEVEL_TX0_SHIFT (0)
#define RP23XX_PIO_FLEVEL_TX0_MASK (0x0f)
#define RP23XX_PIO_FLEVEL_TX_MASK(n) (0x0f << 8*n)
#define RP23XX_PIO_FLEVEL_RX_MASK(n) (0xf0 << 8*n)
#define RP23XX_PIO_IRQ_MASK (0xff)
#define RP23XX_PIO_IRQ_FORCE_MASK (0xff)
#define RP23XX_PIO_DBG_CFGINFO_VERSION_SHIFT (28) /* Version of the core PIO hardware */
#define RP23XX_PIO_DBG_CFGINFO_VERSION_MASK (0xf << RP23XX_PIO_DBG_CFGINFO_VERSION_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_SHIFT (16) /* The size of the instruction memory, measured in units of one instruction */
#define RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_MASK (0x3f << RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_SM_COUNT_SHIFT (8) /* The number of state machines this PIO instance is equipped with. */
#define RP23XX_PIO_DBG_CFGINFO_SM_COUNT_MASK (0x0f << RP23XX_PIO_DBG_CFGINFO_SM_COUNT_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_FIFO_DEPTH_MASK (0x3f) /* The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth. */
#define RP23XX_PIO_INSTR_MEM_MASK (0xffff)
#define RP23XX_PIO_SM_CLKDIV_INT_SHIFT (16) /* Effective frequency is sysclk/int. Value of 0 is interpreted as max possible value */
#define RP23XX_PIO_SM_CLKDIV_INT_MASK (0xffff << RP23XX_PIO_SM_CLKDIV_INT_SHIFT)
#define RP23XX_PIO_SM_CLKDIV_FRAC_SHIFT (8) /* Fractional part of clock divider */
#define RP23XX_PIO_SM_CLKDIV_FRAC_MASK (0xff << RP23XX_PIO_SM_CLKDIV_FRAC_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_EXEC_STALLED (1 << 31) /* An instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear once the instruction completes. */
#define RP23XX_PIO_SM_EXECCTRL_SIDE_EN (1 << 30) /* If 1, the delay MSB is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction. */
#define RP23XX_PIO_SM_EXECCTRL_SIDE_PINDIR (1 << 29) /* Side-set data is asserted to pin OEs instead of pin values */
#define RP23XX_PIO_SM_EXECCTRL_JMP_PIN_SHIFT (24) /* The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */
#define RP23XX_PIO_SM_EXECCTRL_JMP_PIN_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_JMP_PIN_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_SHIFT (19) /* Which data bit to use for inline OUT enable */
#define RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_INLINE_OUT_EN (1 << 18) /* If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) */
#define RP23XX_PIO_SM_EXECCTRL_OUT_STICKY (1 << 17) /* Continuously assert the most recent OUT/SET to the pins */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_SHIFT (12) /* After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_SHIFT (7) /* After reaching wrap_top, execution is wrapped to this address. */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_SHIFT (5) /* Comparison used for the MOV x, STATUS instruction */
#define RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_MASK (0x3 << RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_STATUS_N_MASK (0x0f) /* : Comparison level or IRQ index for the MOV x, STATUS instruction */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_RX (1 << 31) /* When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_TX (1 << 30) /* When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */
#define RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_SHIFT (25) /* Number of bits shifted out of TXSR before autopull or conditional pull. Write 0 for value of 32. */
#define RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_MASK (0x1f << RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_SHIFT)
#define RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_SHIFT (20) /* Number of bits shifted into RXSR before autopush or conditional push. Write 0 for value of 32. */
#define RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_MASK (0x1f << RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_SHIFT)
#define RP23XX_PIO_SM_SHIFTCTRL_OUT_SHIFTDIR (1 << 19) /* 1 = shift out of output shift register to right. 0 = to left. */
#define RP23XX_PIO_SM_SHIFTCTRL_IN_SHIFTDIR (1 << 18) /* 1 = shift input shift register to right (data enters from left). 0 = to left. */
#define RP23XX_PIO_SM_SHIFTCTRL_AUTOPULL (1 << 17) /* Pull automatically when the output shift register is emptied */
#define RP23XX_PIO_SM_SHIFTCTRL_AUTOPUSH (1 << 16) /* Push automatically when the input shift register is filled */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_RX_PUT (1 << 15) /* If 1, disable this state machine’s RX FIFO, make its storage available for random write access by the state machine (using the put instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_TX_GET (1 << 14) /* If 1, disable this state machine’s RX FIFO, make its storage available for random read access by the state machine (using the get instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers) */
#define RP23XX_PIO_SM_ADDR_MASK (0x1f)
#define RP23XX_PIO_SM_INSTR_MASK (0xffff)
#define RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_SHIFT (29) /* The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. */
#define RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_MASK (0x07 << RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT (26) /* The number of pins asserted by a SET. Max of 5 */
#define RP23XX_PIO_SM_PINCTRL_SET_COUNT_MASK (0x07 << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_OUT_COUNT_SHIFT (20) /* The number of pins asserted by an OUT. Value of 0 -> 32 pins */
#define RP23XX_PIO_SM_PINCTRL_OUT_COUNT_MASK (0x3f << RP23XX_PIO_SM_PINCTRL_OUT_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_IN_BASE_SHIFT (15) /* The virtual pin corresponding to IN bit 0 */
#define RP23XX_PIO_SM_PINCTRL_IN_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_IN_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_SHIFT (10) /* The virtual pin corresponding to delay field bit 0 */
#define RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT (5) /* The virtual pin corresponding to SET bit 0 */
#define RP23XX_PIO_SM_PINCTRL_SET_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_OUT_BASE_SHIFT (0) /* The virtual pin corresponding to OUT bit 0 */
#define RP23XX_PIO_SM_PINCTRL_OUT_BASE_MASK (0x1f) /* The virtual pin corresponding to OUT bit 0 */
#define RP23XX_PIO_GPIOBASE_MASK (1 << 4) /* Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO */
#define RP23XX_PIO_INTR_SM7 (1 << 15)
#define RP23XX_PIO_INTR_SM6 (1 << 14)
#define RP23XX_PIO_INTR_SM5 (1 << 13)
#define RP23XX_PIO_INTR_SM4 (1 << 12)
#define RP23XX_PIO_INTR_SM3 (1 << 11)
#define RP23XX_PIO_INTR_SM2 (1 << 10)
#define RP23XX_PIO_INTR_SM1 (1 << 9)
#define RP23XX_PIO_INTR_SM0 (1 << 8)
#define RP23XX_PIO_INTR_SM3_TXNFULL (1 << 7)
#define RP23XX_PIO_INTR_SM2_TXNFULL (1 << 6)
#define RP23XX_PIO_INTR_SM1_TXNFULL (1 << 5)
#define RP23XX_PIO_INTR_SM0_TXNFULL (1 << 4)
#define RP23XX_PIO_INTR_SM3_RXNEMPTY (1 << 3)
#define RP23XX_PIO_INTR_SM2_RXNEMPTY (1 << 2)
#define RP23XX_PIO_INTR_SM1_RXNEMPTY (1 << 1)
#define RP23XX_PIO_INTR_SM0_RXNEMPTY (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pll.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PLL_CS_OFFSET 0x00000000
#define RP23XX_PLL_PWR_OFFSET 0x00000004
#define RP23XX_PLL_FBDIV_INT_OFFSET 0x00000008
#define RP23XX_PLL_PRIM_OFFSET 0x0000000c
#define RP23XX_PLL_INTR_OFFSET 0x00000010
#define RP23XX_PLL_INTE_OFFSET 0x00000014
#define RP23XX_PLL_INTF_OFFSET 0x00000018
#define RP23XX_PLL_INTS_OFFSET 0x0000001c
/* Register definitions *****************************************************/
#define RP23XX_PLL_CS (RP23XX_PLL_BASE + RP23XX_PLL_CS_OFFSET)
#define RP23XX_PLL_PWR (RP23XX_PLL_BASE + RP23XX_PLL_PWR_OFFSET)
#define RP23XX_PLL_FBDIV_INT (RP23XX_PLL_BASE + RP23XX_PLL_FBDIV_INT_OFFSET)
#define RP23XX_PLL_PRIM (RP23XX_PLL_BASE + RP23XX_PLL_PRIM_OFFSET)
#define RP23XX_PLL_INTR (RP23XX_PLL_BASE + RP23XX_PLL_INTR_OFFSET)
#define RP23XX_PLL_INTE (RP23XX_PLL_BASE + RP23XX_PLL_INTE_OFFSET)
#define RP23XX_PLL_INTF (RP23XX_PLL_BASE + RP23XX_PLL_INTF_OFFSET)
#define RP23XX_PLL_INTS (RP23XX_PLL_BASE + RP23XX_PLL_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PLL_CS_MASK (0xc000013f)
#define RP23XX_PLL_CS_LOCK (1 << 31)
#define RP23XX_PLL_CS_LOCK_N (1 << 30)
#define RP23XX_PLL_CS_BYPASS (1 << 8)
#define RP23XX_PLL_CS_REFDIV_MASK (0x0000003f)
#define RP23XX_PLL_PWR_MASK (0x0000002d)
#define RP23XX_PLL_PWR_VCOPD (1 << 5)
#define RP23XX_PLL_PWR_POSTDIVPD (1 << 3)
#define RP23XX_PLL_PWR_DSMPD (1 << 2)
#define RP23XX_PLL_PWR_PD (1 << 0)
#define RP23XX_PLL_FBDIV_INT_MASK (0x00000fff)
#define RP23XX_PLL_PRIM_MASK (0x00077000)
#define RP23XX_PLL_PRIM_POSTDIV1_SHIFT (16) /* divide by 1-7 */
#define RP23XX_PLL_PRIM_POSTDIV1_MASK (0x07 << RP23XX_PLL_PRIM_POSTDIV1_SHIFT)
#define RP23XX_PLL_PRIM_POSTDIV2_SHIFT (12) /* divide by 1-7 */
#define RP23XX_PLL_PRIM_POSTDIV2_MASK (0x07 << RP23XX_PLL_PRIM_POSTDIV2_SHIFT)
#define RP23XX_PLL_INTR_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTE_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTF_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTS_LOCK_N_STICKY (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_powman.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_POWMAN_BADPASSWD_OFFSET 0x00000000
#define RP23XX_POWMAN_VREG_CTRL_OFFSET 0x00000004
#define RP23XX_POWMAN_VREG_STS_OFFSET 0x00000008
#define RP23XX_POWMAN_VREG_OFFSET 0x0000000c
#define RP23XX_POWMAN_VREG_LP_ENTRY_OFFSET 0x00000010
#define RP23XX_POWMAN_VREG_LP_EXIT_OFFSET 0x00000014
#define RP23XX_POWMAN_BOD_CTRL_OFFSET 0x00000018
#define RP23XX_POWMAN_BOD_OFFSET 0x0000001c
#define RP23XX_POWMAN_BOD_LP_ENTRY_OFFSET 0x00000020
#define RP23XX_POWMAN_BOD_LP_EXIT_OFFSET 0x00000024
#define RP23XX_POWMAN_LPOSC_OFFSET 0x00000028
#define RP23XX_POWMAN_CHIP_RESET_OFFSET 0x0000002c
#define RP23XX_POWMAN_WDSEL_OFFSET 0x00000030
#define RP23XX_POWMAN_SEQ_CFG_OFFSET 0x00000034
#define RP23XX_POWMAN_STATE_OFFSET 0x00000038
#define RP23XX_POWMAN_POW_FASTDIV_OFFSET 0x0000003c
#define RP23XX_POWMAN_POW_DELAY_OFFSET 0x00000040
#define RP23XX_POWMAN_EXT_CTRL0_OFFSET 0x00000044
#define RP23XX_POWMAN_EXT_CTRL1_OFFSET 0x00000048
#define RP23XX_POWMAN_EXT_TIME_REF_OFFSET 0x0000004c
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET 0x00000050
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET 0x00000054
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_OFFSET 0x00000058
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET 0x0000005c
#define RP23XX_POWMAN_SET_TIME_63TO48_OFFSET 0x00000060
#define RP23XX_POWMAN_SET_TIME_47TO32_OFFSET 0x00000064
#define RP23XX_POWMAN_SET_TIME_31TO16_OFFSET 0x00000068
#define RP23XX_POWMAN_SET_TIME_15TO0_OFFSET 0x0000006c
#define RP23XX_POWMAN_READ_TIME_UPPER_OFFSET 0x00000070
#define RP23XX_POWMAN_READ_TIME_LOWER_OFFSET 0x00000074
#define RP23XX_POWMAN_ALARM_TIME_63TO48_OFFSET 0x00000078
#define RP23XX_POWMAN_ALARM_TIME_47TO32_OFFSET 0x0000007c
#define RP23XX_POWMAN_ALARM_TIME_31TO16_OFFSET 0x00000080
#define RP23XX_POWMAN_ALARM_TIME_15TO0_OFFSET 0x00000084
#define RP23XX_POWMAN_TIMER_OFFSET 0x00000088
#define RP23XX_POWMAN_PWRUP0_OFFSET 0x0000008c
#define RP23XX_POWMAN_PWRUP1_OFFSET 0x00000090
#define RP23XX_POWMAN_PWRUP2_OFFSET 0x00000094
#define RP23XX_POWMAN_PWRUP3_OFFSET 0x00000098
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ_OFFSET 0x0000009c
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP_OFFSET 0x000000a0
#define RP23XX_POWMAN_DBG_PWRCFG_OFFSET 0x000000a4
#define RP23XX_POWMAN_BOOTDIS_OFFSET 0x000000a8
#define RP23XX_POWMAN_DBGCONFIG_OFFSET 0x000000ac
#define RP23XX_POWMAN_SCRATCH0_OFFSET 0x000000b0
#define RP23XX_POWMAN_SCRATCH1_OFFSET 0x000000b4
#define RP23XX_POWMAN_SCRATCH2_OFFSET 0x000000b8
#define RP23XX_POWMAN_SCRATCH3_OFFSET 0x000000bc
#define RP23XX_POWMAN_SCRATCH4_OFFSET 0x000000c0
#define RP23XX_POWMAN_SCRATCH5_OFFSET 0x000000c4
#define RP23XX_POWMAN_SCRATCH6_OFFSET 0x000000c8
#define RP23XX_POWMAN_SCRATCH7_OFFSET 0x000000cc
#define RP23XX_POWMAN_BOOT0_OFFSET 0x000000d0
#define RP23XX_POWMAN_BOOT1_OFFSET 0x000000d4
#define RP23XX_POWMAN_BOOT2_OFFSET 0x000000d8
#define RP23XX_POWMAN_BOOT3_OFFSET 0x000000dc
#define RP23XX_POWMAN_INTR_OFFSET 0x000000e0
#define RP23XX_POWMAN_INTE_OFFSET 0x000000e4
#define RP23XX_POWMAN_INTF_OFFSET 0x000000e8
#define RP23XX_POWMAN_INTS_OFFSET 0x000000ec
/* Register definitions *****************************************************/
#define RP23XX_POWMAN_BADPASSWD (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BADPASSWD_OFFSET)
#define RP23XX_POWMAN_VREG_CTRL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_CTRL_OFFSET)
#define RP23XX_POWMAN_VREG_STS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_STS_OFFSET)
#define RP23XX_POWMAN_VREG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_OFFSET)
#define RP23XX_POWMAN_VREG_LP_ENTRY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_LP_ENTRY_OFFSET)
#define RP23XX_POWMAN_VREG_LP_EXIT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_LP_EXIT_OFFSET)
#define RP23XX_POWMAN_BOD_CTRL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_CTRL_OFFSET)
#define RP23XX_POWMAN_BOD (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_OFFSET)
#define RP23XX_POWMAN_BOD_LP_ENTRY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_LP_ENTRY_OFFSET)
#define RP23XX_POWMAN_BOD_LP_EXIT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_LP_EXIT_OFFSET)
#define RP23XX_POWMAN_LPOSC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_OFFSET)
#define RP23XX_POWMAN_CHIP_RESET (RP23XX_POWMAN_BASE + RP23XX_POWMAN_CHIP_RESET_OFFSET)
#define RP23XX_POWMAN_WDSEL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_WDSEL_OFFSET)
#define RP23XX_POWMAN_SEQ_CFG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SEQ_CFG_OFFSET)
#define RP23XX_POWMAN_STATE (RP23XX_POWMAN_BASE + RP23XX_POWMAN_STATE_OFFSET)
#define RP23XX_POWMAN_POW_FASTDIV (RP23XX_POWMAN_BASE + RP23XX_POWMAN_POW_FASTDIV_OFFSET)
#define RP23XX_POWMAN_POW_DELAY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_POW_DELAY_OFFSET)
#define RP23XX_POWMAN_EXT_CTRL0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_CTRL0_OFFSET)
#define RP23XX_POWMAN_EXT_CTRL1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_CTRL1_OFFSET)
#define RP23XX_POWMAN_EXT_TIME_REF (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_TIME_REF_OFFSET)
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET)
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET)
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_OFFSET)
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET)
#define RP23XX_POWMAN_SET_TIME_63TO48 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_63TO48_OFFSET)
#define RP23XX_POWMAN_SET_TIME_47TO32 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_47TO32_OFFSET)
#define RP23XX_POWMAN_SET_TIME_31TO16 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_31TO16_OFFSET)
#define RP23XX_POWMAN_SET_TIME_15TO0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_15TO0_OFFSET)
#define RP23XX_POWMAN_READ_TIME_UPPER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_READ_TIME_UPPER_OFFSET)
#define RP23XX_POWMAN_READ_TIME_LOWER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_READ_TIME_LOWER_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_63TO48 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_63TO48_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_47TO32 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_47TO32_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_31TO16 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_31TO16_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_15TO0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_15TO0_OFFSET)
#define RP23XX_POWMAN_TIMER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_TIMER_OFFSET)
#define RP23XX_POWMAN_PWRUP0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP0_OFFSET)
#define RP23XX_POWMAN_PWRUP1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP1_OFFSET)
#define RP23XX_POWMAN_PWRUP2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP2_OFFSET)
#define RP23XX_POWMAN_PWRUP3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP3_OFFSET)
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ (RP23XX_POWMAN_BASE + RP23XX_POWMAN_CURRENT_PWRUP_REQ_OFFSET)
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LAST_SWCORE_PWRUP_OFFSET)
#define RP23XX_POWMAN_DBG_PWRCFG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_DBG_PWRCFG_OFFSET)
#define RP23XX_POWMAN_BOOTDIS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOTDIS_OFFSET)
#define RP23XX_POWMAN_DBGCONFIG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_DBGCONFIG_OFFSET)
#define RP23XX_POWMAN_SCRATCH0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH0_OFFSET)
#define RP23XX_POWMAN_SCRATCH1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH1_OFFSET)
#define RP23XX_POWMAN_SCRATCH2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH2_OFFSET)
#define RP23XX_POWMAN_SCRATCH3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH3_OFFSET)
#define RP23XX_POWMAN_SCRATCH4 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH4_OFFSET)
#define RP23XX_POWMAN_SCRATCH5 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH5_OFFSET)
#define RP23XX_POWMAN_SCRATCH6 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH6_OFFSET)
#define RP23XX_POWMAN_SCRATCH7 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH7_OFFSET)
#define RP23XX_POWMAN_BOOT0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT0_OFFSET)
#define RP23XX_POWMAN_BOOT1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT1_OFFSET)
#define RP23XX_POWMAN_BOOT2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT2_OFFSET)
#define RP23XX_POWMAN_BOOT3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT3_OFFSET)
#define RP23XX_POWMAN_INTR (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTR_OFFSET)
#define RP23XX_POWMAN_INTE (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTE_OFFSET)
#define RP23XX_POWMAN_INTF (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTF_OFFSET)
#define RP23XX_POWMAN_INTS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_POWMAN_BADPASSWD (1 << 0)
#define RP23XX_POWMAN_VREG_CTRL_RST_N (1 << 15)
#define RP23XX_POWMAN_VREG_CTRL_UNLOCK (1 << 13)
#define RP23XX_POWMAN_VREG_CTRL_ISOLATE (1 << 12)
#define RP23XX_POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT (1 << 8)
#define RP23XX_POWMAN_VREG_CTRL_HT_TH_MASK (0x00000070)
#define RP23XX_POWMAN_VREG_STS_VOUT_OK (1 << 4)
#define RP23XX_POWMAN_VREG_STS_STARTUP (1 << 0)
#define RP23XX_POWMAN_VREG_UPDATE_IN_PROGRESS (1 << 15)
#define RP23XX_POWMAN_VREG_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_HIZ (1 << 1)
#define RP23XX_POWMAN_VREG_LP_ENTRY_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_LP_ENTRY_MODE (1 << 2)
#define RP23XX_POWMAN_VREG_LP_ENTRY_HIZ (1 << 1)
#define RP23XX_POWMAN_VREG_LP_EXIT_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_LP_EXIT_MODE (1 << 2)
#define RP23XX_POWMAN_VREG_LP_EXIT_HIZ (1 << 1)
#define RP23XX_POWMAN_BOD_CTRL (1 << 12)
#define RP23XX_POWMAN_BOD_CTRL_ISOLATE (1 << 12)
#define RP23XX_POWMAN_BOD_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_EN (1 << 0)
#define RP23XX_POWMAN_BOD_LP_ENTRY_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_LP_ENTRY_EN (1 << 0)
#define RP23XX_POWMAN_BOD_LP_EXIT_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_LP_EXIT_EN (1 << 0)
#define RP23XX_POWMAN_LPOSC_TRIM_MASK 0x000003f0
#define RP23XX_POWMAN_LPOSC_MODE_MASK 0x00000003
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM (1 << 28)
#define RP23XX_POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ (1 << 27)
#define RP23XX_POWMAN_CHIP_RESET_HAD_GLITCH_DETECT (1 << 26)
#define RP23XX_POWMAN_CHIP_RESET_HAD_SWCORE_PD (1 << 25)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE (1 << 24)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN (1 << 23)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC (1 << 22)
#define RP23XX_POWMAN_CHIP_RESET_HAD_RESCUE (1 << 21)
#define RP23XX_POWMAN_CHIP_RESET_HAD_DP_RESET_REQ (1 << 19)
#define RP23XX_POWMAN_CHIP_RESET_HAD_RUN_LOW (1 << 18)
#define RP23XX_POWMAN_CHIP_RESET_HAD_BOR (1 << 17)
#define RP23XX_POWMAN_CHIP_RESET_HAD_POR (1 << 16)
#define RP23XX_POWMAN_CHIP_RESET_RESCUE_FLAG (1 << 4)
#define RP23XX_POWMAN_CHIP_RESET_DOUBLE_TAP (1 << 0)
#define RP23XX_POWMAN_WDSEL_RESET_RSM (1 << 12)
#define RP23XX_POWMAN_WDSEL_RESET_SWCORE (1 << 8)
#define RP23XX_POWMAN_WDSEL_RESET_POWMAN (1 << 4)
#define RP23XX_POWMAN_WDSEL_RESET_POWMAN_ASYNC (1 << 0)
#define RP23XX_POWMAN_SEQ_CFG_USING_FAST_POWCK (1 << 20)
#define RP23XX_POWMAN_SEQ_CFG_USING_BOD_LP (1 << 17)
#define RP23XX_POWMAN_SEQ_CFG_USING_VREG_LP (1 << 16)
#define RP23XX_POWMAN_SEQ_CFG_USE_FAST_POWCK (1 << 12)
#define RP23XX_POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP (1 << 8)
#define RP23XX_POWMAN_SEQ_CFG_USE_BOD_HP (1 << 7)
#define RP23XX_POWMAN_SEQ_CFG_USE_BOD_LP (1 << 6)
#define RP23XX_POWMAN_SEQ_CFG_USE_VREG_HP (1 << 5)
#define RP23XX_POWMAN_SEQ_CFG_USE_VREG_LP (1 << 4)
#define RP23XX_POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 (1 << 1)
#define RP23XX_POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 (1 << 0)
#define RP23XX_POWMAN_STATE_CHANGING (1 << 13)
#define RP23XX_POWMAN_STATE_WAITING (1 << 12)
#define RP23XX_POWMAN_STATE_BAD_HW_REQ (1 << 11)
#define RP23XX_POWMAN_STATE_BAD_SW_REQ (1 << 10)
#define RP23XX_POWMAN_STATE_PWRUP_WHILE_WAITING (1 << 9)
#define RP23XX_POWMAN_STATE_REQ_IGNORED (1 << 8)
#define RP23XX_POWMAN_STATE_REQ_MASK 0x000000f0
#define RP23XX_POWMAN_STATE_CURRENT_MASK 0x0000000f
#define RP23XX_POWMAN_POW_FASTDIV_MASK 0x000007ff
#define RP23XX_POWMAN_POW_DELAY_SRAM_STEP_MASK 0x0000ff00
#define RP23XX_POWMAN_POW_DELAY_XIP_STEP_MASK 0x000000f0
#define RP23XX_POWMAN_POW_DELAY_SWCORE_STEP_MASK 0x0000000f
#define RP23XX_POWMAN_EXT_CTRL0_LP_EXIT_STATE (1 << 14)
#define RP23XX_POWMAN_EXT_CTRL0_LP_ENTRY_STATE (1 << 13)
#define RP23XX_POWMAN_EXT_CTRL0_INIT_STATE (1 << 12)
#define RP23XX_POWMAN_EXT_CTRL0_INIT (1 << 8)
#define RP23XX_POWMAN_EXT_CTRL0_GPIO_SELECT_MASK 0x0000003f
#define RP23XX_POWMAN_EXT_CTRL1_LP_EXIT_STATE (1 << 14)
#define RP23XX_POWMAN_EXT_CTRL1_LP_ENTRY_STATE (1 << 13)
#define RP23XX_POWMAN_EXT_CTRL1_INIT_STATE (1 << 12)
#define RP23XX_POWMAN_EXT_CTRL1_INIT (1 << 8)
#define RP23XX_POWMAN_EXT_CTRL1_GPIO_SELECT_MASK 0x0000003f
#define RP23XX_POWMAN_EXT_TIME_REF_MASK 0x00000013
#define RP23XX_POWMAN_EXT_TIME_REF_DRIVE_LPCK (1 << 4)
#define RP23XX_POWMAN_EXT_TIME_REF_SOURCE_SEL_MASK 0x00000003
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_MASK 0x0000003f
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_MASK 0x0000ffff
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_MASK 0x0000ffff
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_63TO48_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_47TO32_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_31TO16_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_15TO0_MASK 0x0000ffff
#define RP23XX_POWMAN_READ_TIME_UPPER_MASK 0xffffffff
#define RP23XX_POWMAN_READ_TIME_LOWER_MASK 0xffffffff
#define RP23XX_POWMAN_ALARM_TIME_63TO48_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_47TO32_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_31TO16_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_15TO0_MASK 0x0000ffff
#define RP23XX_POWMAN_TIMER_USING_GPIO_1HZ (1 << 19)
#define RP23XX_POWMAN_TIMER_USING_GPIO_1KHZ (1 << 18)
#define RP23XX_POWMAN_TIMER_USING_LPOSC (1 << 17)
#define RP23XX_POWMAN_TIMER_USING_XOSC (1 << 16)
#define RP23XX_POWMAN_TIMER_USE_GPIO_1HZ (1 << 13)
#define RP23XX_POWMAN_TIMER_USE_GPIO_1KHZ (1 << 10)
#define RP23XX_POWMAN_TIMER_USE_XOSC (1 << 9)
#define RP23XX_POWMAN_TIMER_USE_LPOSC (1 << 8)
#define RP23XX_POWMAN_TIMER_ALARM (1 << 6)
#define RP23XX_POWMAN_TIMER_PWRUP_ON_ALARM (1 << 5)
#define RP23XX_POWMAN_TIMER_ALARM_ENAB (1 << 4)
#define RP23XX_POWMAN_TIMER_CLEAR (1 << 2)
#define RP23XX_POWMAN_TIMER_RUN (1 << 1)
#define RP23XX_POWMAN_TIMER_NONSEC_WRITE (1 << 0)
#define RP23XX_POWMAN_PWRUP0_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP0_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP0_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP0_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP0_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP0_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP1_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP1_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP1_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP1_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP1_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP1_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP2_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP2_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP2_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP2_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP2_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP2_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP3_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP3_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP3_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP3_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP3_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP3_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ_MASK 0x0000007f
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP_MASK 0x0000007f
#define RP23XX_POWMAN_DBG_PWRCFG (1 << 0)
#define RP23XX_POWMAN_DBG_PWRCFG_IGNORE (1 << 0)
#define RP23XX_POWMAN_BOOTDIS_MASK 0x00000003
#define RP23XX_POWMAN_BOOTDIS_NEXT (1 << 1)
#define RP23XX_POWMAN_BOOTDIS_NOW (1 << 0)
#define RP23XX_POWMAN_DBGCONFIG_MASK 0x0000000f
#define RP23XX_POWMAN_DBGCONFIG_DP_INSTID_MASK 0x0000000f
#define RP23XX_POWMAN_INTR_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTR_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTR_TIMER (1 << 1)
#define RP23XX_POWMAN_INTR_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTE_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTE_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTE_TIMER (1 << 1)
#define RP23XX_POWMAN_INTE_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTF_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTF_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTF_TIMER (1 << 1)
#define RP23XX_POWMAN_INTF_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTS_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTS_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTS_TIMER (1 << 1)
#define RP23XX_POWMAN_INTS_VREG_OUTPUT_LOW (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PSM_FRCE_ON_OFFSET 0x000000 /* Force block out of reset (i.e. power it on) */
#define RP23XX_PSM_FRCE_OFF_OFFSET 0x000004 /* Force into reset (i.e. power it off) */
#define RP23XX_PSM_WDSEL_OFFSET 0x000008 /* Set to 1 if this peripheral should be reset when the watchdog fires. */
#define RP23XX_PSM_DONE_OFFSET 0x00000c /* Indicates the peripheral's registers are ready to access. */
/* Register definitions *****************************************************/
#define RP23XX_PSM_FRCE_ON (RP23XX_PSM_BASE + RP23XX_PSM_FRCE_ON_OFFSET)
#define RP23XX_PSM_FRCE_OFF (RP23XX_PSM_BASE + RP23XX_PSM_FRCE_OFF_OFFSET)
#define RP23XX_PSM_WDSEL (RP23XX_PSM_BASE + RP23XX_PSM_WDSEL_OFFSET)
#define RP23XX_PSM_DONE (RP23XX_PSM_BASE + RP23XX_PSM_DONE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PSM_PROC1 (1 << 24)
#define RP23XX_PSM_PROC0 (1 << 23)
#define RP23XX_PSM_ACCESSCTRL (1 << 22)
#define RP23XX_PSM_SIO (1 << 21)
#define RP23XX_PSM_XIP (1 << 20)
#define RP23XX_PSM_SRAM9 (1 << 19)
#define RP23XX_PSM_SRAM8 (1 << 18)
#define RP23XX_PSM_SRAM7 (1 << 17)
#define RP23XX_PSM_SRAM6 (1 << 16)
#define RP23XX_PSM_SRAM5 (1 << 15)
#define RP23XX_PSM_SRAM4 (1 << 14)
#define RP23XX_PSM_SRAM3 (1 << 13)
#define RP23XX_PSM_SRAM2 (1 << 12)
#define RP23XX_PSM_SRAM1 (1 << 11)
#define RP23XX_PSM_SRAM0 (1 << 10)
#define RP23XX_PSM_BOOTRAM (1 << 9)
#define RP23XX_PSM_ROM (1 << 8)
#define RP23XX_PSM_BUSFABRIC (1 << 7)
#define RP23XX_PSM_PSM_READY (1 << 6)
#define RP23XX_PSM_CLOCKS (1 << 5)
#define RP23XX_PSM_RESETS (1 << 4)
#define RP23XX_PSM_XOSC (1 << 3)
#define RP23XX_PSM_ROSC (1 << 2)
#define RP23XX_PSM_OTP (1 << 1)
#define RP23XX_PSM_PROC_COLD (1 << 0)
#define RP23XX_PSM_WDSEL_BITS 0x01ffffff
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pwm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_PWM_CSR_OFFSET(n) (0x000000 + (n) * 20) /* PWM control and status register */
#define RP23XX_RV_PWM_DIV_OFFSET(n) (0x000004 + (n) * 20) /* PWM clock divisor register */
#define RP23XX_RV_PWM_CTR_OFFSET(n) (0x000008 + (n) * 20) /* PWM counter register */
#define RP23XX_RV_PWM_CC_OFFSET(n) (0x00000c + (n) * 20) /* PWM compare register */
#define RP23XX_RV_PWM_TOP_OFFSET(n) (0x000010 + (n) * 20) /* PWM wrap value register */
#define RP23XX_RV_PWM_EN_OFFSET 0x0000f0 /* PWM enable register */
#define RP23XX_RV_PWM_INTR_OFFSET 0x0000f4 /* PWM raw interrupt register */
#define RP23XX_RV_PWM_IRQ0_INTE_OFFSET 0x0000f8 /* PWM interrupt enable register */
#define RP23XX_RV_PWM_IRQ0_INTF_OFFSET 0x0000fC /* PWM interrupt force register */
#define RP23XX_RV_PWM_IRQ0_INTS_OFFSET 0x000100 /* PWM interrupt status register */
#define RP23XX_RV_PWM_IRQ1_INTE_OFFSET 0x000104
#define RP23XX_RV_PWM_IRQ1_INTF_OFFSET 0x000108
#define RP23XX_RV_PWM_IRQ1_INTS_OFFSET 0x00010c
/* Register definitions *****************************************************/
#define RP23XX_RV_PWM_CSR(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CSR_OFFSET(n))
#define RP23XX_RV_PWM_DIV(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_DIV_OFFSET(n))
#define RP23XX_RV_PWM_CTR(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CTR_OFFSET(n))
#define RP23XX_RV_PWM_CC(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CC_OFFSET(n))
#define RP23XX_RV_PWM_TOP(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_TOP_OFFSET(n))
#define RP23XX_RV_PWM_EN (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_EN_OFFSET)
#define RP23XX_RV_PWM_INTR (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_INTR_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTE (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTE_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTF (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTF_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTS (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTS_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTE (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTE_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTF (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTF_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTS (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_PWM_CSR_PH_ADV (1 << 7) /* advance phase of counter by one */
#define RP23XX_RV_PWM_CSR_PH_RET (1 << 6) /* retard phase of counter by one */
#define RP23XX_RV_PWM_CSR_DIVMODE_SHIFT (4) /* divisor mode */
#define RP23XX_RV_PWM_CSR_DIVMODE_MASK (0x03 << RP23XX_RV_PWM_CSR_DIVMODE_SHIFT)
#define RP23XX_RV_PWM_CSR_B_INV (1 << 3) /* invert output B */
#define RP23XX_RV_PWM_CSR_A_INV (1 << 2) /* invert output A */
#define RP23XX_RV_PWM_CSR_PH_CORRECT (1 << 1) /* enable phase correct modulation */
#define RP23XX_RV_PWM_CSR_EN (1 << 0) /* enable the PWM channel */
#define RP23XX_PWN_CSR_DIVMODE_DIV 0x00
#define RP23XX_PWN_CSR_DIVMODE_LEVEL 0x01
#define RP23XX_PWN_CSR_DIVMODE_RISE 0x02
#define RP23XX_PWN_CSR_DIVMODE_FALL 0x03
#define RP23XX_RV_PWM_DIV_INT_SHIFT (4) /* divisor integer part */
#define RP23XX_RV_PWM_DIV_INT_MASK (0xff << RP23XX_RV_PWM_DIV_INT_SHIFT)
#define RP23XX_RV_PWM_DIV_FRAC_SHIFT (0) /* divisor fraction part */
#define RP23XX_RV_PWM_DIV_FRAC_MASK (0x0f << RP23XX_RV_PWM_DIV_FRAC_SHIFT)
#define RP23XX_RV_PWM_CC_B_SHIFT (16) /* channel B compare register */
#define RP23XX_RV_PWM_CC_B_MASK (0xffff << RP23XX_RV_PWM_CC_B_SHIFT)
#define RP23XX_RV_PWM_CC_A_SHIFT (0) /* channel A compare register */
#define RP23XX_RV_PWM_CC_A_MASK (0xffff << RP23XX_RV_PWM_CC_A_SHIFT)
#define RP23XX_RV_PWM_TOP_SHIFT (0) /* channel A compare register */
#define RP23XX_RV_PWM_TOP_MASK (0xffff << RP23XX_RV_PWM_TOP_SHIFT)
/* Bit mask for ENA, INTR, INTE, INTF, and INTS registers */
#define RP23XX_RV_PWM_CH11 (1 << 11) /* PWM channel 11 */
#define RP23XX_RV_PWM_CH10 (1 << 10) /* PWM channel 10 */
#define RP23XX_RV_PWM_CH9 (1 << 9) /* PWM channel 9 */
#define RP23XX_RV_PWM_CH8 (1 << 8) /* PWM channel 8 */
#define RP23XX_RV_PWM_CH7 (1 << 7) /* PWM channel 7 */
#define RP23XX_RV_PWM_CH6 (1 << 6) /* PWM channel 6 */
#define RP23XX_RV_PWM_CH5 (1 << 5) /* PWM channel 5 */
#define RP23XX_RV_PWM_CH4 (1 << 4) /* PWM channel 4 */
#define RP23XX_RV_PWM_CH3 (1 << 3) /* PWM channel 3 */
#define RP23XX_RV_PWM_CH2 (1 << 2) /* PWM channel 2 */
#define RP23XX_RV_PWM_CH1 (1 << 1) /* PWM channel 1 */
#define RP23XX_RV_PWM_CH0 (1 << 0) /* PWM channel 0 */
/****************************************************************************
* The following IOCTL values set additional flags in the RP23XX PWM
* device.
****************************************************************************/
/****************************************************************************
* PWMIOC_RP23XX_SETINVERTPULSE sets the pulse invert flag.
*
* The argument is an integer where:
* bit zero is set to invert channel A
* bit one is set to invert channel B
****************************************************************************/
#define PWMIOC_RP23XX_SETINVERTPULSE _PWMIOC(0x80)
#define PWMIOC_RP23XX_GETINVERTPULSE _PWMIOC(0x81)
/****************************************************************************
* PWMIOC_RP23XX_SETPHASECORRECT sets phase correct flags.
*
* The argument is an integer which if non-zero sets the phase correct flag.
****************************************************************************/
#define PWMIOC_RP23XX_SETPHASECORRECT _PWMIOC(0x82)
#define PWMIOC_RP23XX_GETPHASECORRECT _PWMIOC(0x83)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_qmi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_QMI_DIRECT_CSR_OFFSET 0x00000000
#define RP23XX_QMI_DIRECT_TX_OFFSET 0x00000004
#define RP23XX_QMI_DIRECT_RX_OFFSET 0x00000008
#define RP23XX_QMI_M0_TIMING_OFFSET 0x0000000c
#define RP23XX_QMI_M0_RFMT_OFFSET 0x00000010
#define RP23XX_QMI_M0_RCMD_OFFSET 0x00000014
#define RP23XX_QMI_M0_WFMT_OFFSET 0x00000018
#define RP23XX_QMI_M0_WCMD_OFFSET 0x0000001c
#define RP23XX_QMI_M1_TIMING_OFFSET 0x00000020
#define RP23XX_QMI_M1_RFMT_OFFSET 0x00000024
#define RP23XX_QMI_M1_RCMD_OFFSET 0x00000028
#define RP23XX_QMI_M1_WFMT_OFFSET 0x0000002c
#define RP23XX_QMI_M1_WCMD_OFFSET 0x00000030
#define RP23XX_QMI_ATRANS_OFFSET(n) (0x00000034 + (n) * 4)
/* Register definitions *****************************************************/
#define RP23XX_QMI_DIRECT_CSR (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_CSR_OFFSET)
#define RP23XX_QMI_DIRECT_TX (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_TX_OFFSET)
#define RP23XX_QMI_DIRECT_RX (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_RX_OFFSET)
#define RP23XX_QMI_M0_TIMING (RP23XX_QMI_BASE + RP23XX_QMI_M0_TIMING_OFFSET)
#define RP23XX_QMI_M0_RFMT (RP23XX_QMI_BASE + RP23XX_QMI_M0_RFMT_OFFSET)
#define RP23XX_QMI_M0_RCMD (RP23XX_QMI_BASE + RP23XX_QMI_M0_RCMD_OFFSET)
#define RP23XX_QMI_M0_WFMT (RP23XX_QMI_BASE + RP23XX_QMI_M0_WFMT_OFFSET)
#define RP23XX_QMI_M0_WCMD (RP23XX_QMI_BASE + RP23XX_QMI_M0_WCMD_OFFSET)
#define RP23XX_QMI_M1_TIMING (RP23XX_QMI_BASE + RP23XX_QMI_M1_TIMING_OFFSET)
#define RP23XX_QMI_M1_RFMT (RP23XX_QMI_BASE + RP23XX_QMI_M1_RFMT_OFFSET)
#define RP23XX_QMI_M1_RCMD (RP23XX_QMI_BASE + RP23XX_QMI_M1_RCMD_OFFSET)
#define RP23XX_QMI_M1_WFMT (RP23XX_QMI_BASE + RP23XX_QMI_M1_WFMT_OFFSET)
#define RP23XX_QMI_M1_WCMD (RP23XX_QMI_BASE + RP23XX_QMI_M1_WCMD_OFFSET)
#define RP23XX_QMI_ATRANS(n) (RP23XX_QMI_BASE + RP23XX_QMI_ATRANS_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_QMI_DIRECT_CSR_RXDELAY_SHIFT (30) /* Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) */
#define RP23XX_QMI_DIRECT_CSR_RXDELAY_MASK (0x3 << RP23XX_QMI_DIRECT_CSR_RXDELAY_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT (22) /* Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0 */
#define RP23XX_QMI_DIRECT_CSR_CLKDIV_MASK (0xff << RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_RXLEVEL_SHIFT (18) /* Current level of DIRECT_RX FIFO */
#define RP23XX_QMI_DIRECT_CSR_RXLEVEL_MASK (0x7 << RP23XX_QMI_DIRECT_CSR_RXLEVEL_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_RXFULL (1 << 17) /* When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full */
#define RP23XX_QMI_DIRECT_CSR_RXEMPTY (1 << 16) /* When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined */
#define RP23XX_QMI_DIRECT_CSR_TXLEVEL_SHIFT (12) /* Current level of DIRECT_TX FIFO */
#define RP23XX_QMI_DIRECT_CSR_TXLEVEL_MASK (0x7 << RP23XX_QMI_DIRECT_CSR_TXLEVEL_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_TXEMPTY (1 << 11) /* When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes */
#define RP23XX_QMI_DIRECT_CSR_TXFULL (1 << 10) /* When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored */
#define RP23XX_QMI_DIRECT_CSR_AUTO_CS1N (1 << 7) /* When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set */
#define RP23XX_QMI_DIRECT_CSR_AUTO_CS0N (1 << 6) /* When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set */
#define RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N (1 << 3) /* When 1, assert (i.e. drive low) the CS1n chip select line */
#define RP23XX_QMI_DIRECT_CSR_ASSERT_CS0N (1 << 2) /* When 1, assert (i.e. drive low) the CS0n chip select line */
#define RP23XX_QMI_DIRECT_CSR_BUSY (1 << 1) /* Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted */
#define RP23XX_QMI_DIRECT_CSR_EN (1 << 0) /* Enable direct mode */
#define RP23XX_QMI_DIRECT_TX_NOPUSH (1 << 20) /* Inhibit the RX FIFO push that would correspond to this TX FIFO entry */
#define RP23XX_QMI_DIRECT_TX_OE (1 << 19) /* Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input */
#define RP23XX_QMI_DIRECT_TX_DWIDTH (1 << 18) /* Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely */
#define RP23XX_QMI_DIRECT_TX_IWIDTH_SHIFT (16) /* Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely */
#define RP23XX_QMI_DIRECT_TX_IWIDTH_MASK (0x3 << RP23XX_QMI_DIRECT_TX_IWIDTH_SHIFT)
#define RP23XX_QMI_DIRECT_TX_DATA_MASK (0xffff) /* Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first. */
#define RP23XX_QMI_DIRECT_RX_MASK (0xffff) /* With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. */
#define RP23XX_QMI_TIMING_COOLDOWN_SHIFT (30) /* Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power */
#define RP23XX_QMI_TIMING_COOLDOWN_MASK (0x3 << RP23XX_QMI_M0_TIMING_COOLDOWN_SHIFT)
#define RP23XX_QMI_TIMING_PAGEBREAK_SHIFT (28) /* When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary */
#define RP23XX_QMI_TIMING_PAGEBREAK_MASK (0x3 << RP23XX_QMI_M0_TIMING_PAGEBREAK_SHIFT)
#define RP23XX_QMI_TIMING_SELECT_SETUP (1 << 25) /* Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK */
#define RP23XX_QMI_TIMING_SELECT_HOLD_SHIFT (23) /* Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window’s chip select */
#define RP23XX_QMI_TIMING_SELECT_HOLD_MASK (0x3 << RP23XX_QMI_M0_TIMING_SELECT_HOLD_SHIFT)
#define RP23XX_QMI_TIMING_MAX_SELECT_SHIFT (17) /* Enforce a maximum assertion duration for this window’s chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN) */
#define RP23XX_QMI_TIMING_MAX_SELECT_MASK (0x3f << RP23XX_QMI_M0_TIMING_MAX_SELECT_SHIFT)
#define RP23XX_QMI_TIMING_MIN_DESELECT_SHIFT (12) /* After this window’s chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin */
#define RP23XX_QMI_TIMING_MIN_DESELECT_MASK (0x1f << RP23XX_QMI_M0_TIMING_MIN_DESELECT_SHIFT)
#define RP23XX_QMI_TIMING_RXDELAY_SHIFT (8) /* Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register */
#define RP23XX_QMI_TIMING_RXDELAY_MASK (0x7 << RP23XX_QMI_M0_TIMING_RXDELAY_SHIFT)
#define RP23XX_QMI_TIMING_CLKDIV_MASK (0x000000ff) /* Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0 */
#define RP23XX_QMI_FMT_DTR (1 << 28) /* Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch */
#define RP23XX_QMI_FMT_DUMMY_LEN_SHIFT (16) /* Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) */
#define RP23XX_QMI_FMT_DUMMY_LEN_MASK (0x7 << RP23XX_QMI_M0_RFMT_DUMMY_LEN_SHIFT)
#define RP23XX_QMI_FMT_SUFFIX_LEN_SHIFT (14) /* Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) */
#define RP23XX_QMI_FMT_SUFFIX_LEN_MASK (0x3 << RP23XX_QMI_M0_RFMT_SUFFIX_LEN_SHIFT)
#define RP23XX_QMI_FMT_PREFIX_LEN (1 << 12) /* Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) */
#define RP23XX_QMI_FMT_DATA_WIDTH_SHIFT (8) /* The width used for the data transfer */
#define RP23XX_QMI_FMT_DATA_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_DATA_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_DUMMY_WIDTH_SHIFT (6) /* The width used for the dummy phase, if any */
#define RP23XX_QMI_FMT_DUMMY_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_DUMMY_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_SUFFIX_WIDTH_SHIFT (4) /* The width used for the post-address command suffix, if any */
#define RP23XX_QMI_FMT_SUFFIX_WIDTH_MASK (0x4 << RP23XX_QMI_M0_RFMT_SUFFIX_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_ADDR_WIDTH_SHIFT (2) /* The transfer width used for the address. The address phase always transfers 24 bits in total */
#define RP23XX_QMI_FMT_ADDR_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_ADDR_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_PREFIX_WIDTH_MASK (0x00000003) /* The transfer width used for the command prefix, if any */
#define RP23XX_QMI_CMD_SUFFIX_SHIFT (8) /* The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero */
#define RP23XX_QMI_CMD_SUFFIX_MASK (0xff << RP23XX_QMI_CMD_SUFFIX_SHIFT)
#define RP23XX_QMI_CMD_PREFIX_MASK (0x000000ff) /* The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero */
#define RP23XX_QMI_ATRANS_SIZE_SHIFT (16) /* Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). */
#define RP23XX_QMI_ATRANS_SIZE_MASK (0x7ff << RP23XX_QMI_ATRANS_SIZE_SHIFT)
#define RP23XX_QMI_ATRANS_BASE_MASK (0xfff) /* Physical address base for this virtual address range, in units of 4 kiB (one flash sector) */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RESETS_RESET_OFFSET 0x000000 /* Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. */
#define RP23XX_RESETS_WDSEL_OFFSET 0x000004 /* Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. */
#define RP23XX_RESETS_RESET_DONE_OFFSET 0x000008 /* Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. */
/* Register definitions *****************************************************/
#define RP23XX_RESETS_RESET (RP23XX_RESETS_BASE + RP23XX_RESETS_RESET_OFFSET)
#define RP23XX_RESETS_WDSEL (RP23XX_RESETS_BASE + RP23XX_RESETS_WDSEL_OFFSET)
#define RP23XX_RESETS_RESET_DONE (RP23XX_RESETS_BASE + RP23XX_RESETS_RESET_DONE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RESETS_RESET_MASK (0x1fffffff)
#define RP23XX_RESETS_RESET_USBCTRL (1 << 28)
#define RP23XX_RESETS_RESET_UART1 (1 << 27)
#define RP23XX_RESETS_RESET_UART0 (1 << 26)
#define RP23XX_RESETS_RESET_TRNG (1 << 25)
#define RP23XX_RESETS_RESET_TIMER1 (1 << 24)
#define RP23XX_RESETS_RESET_TIMER0 (1 << 23)
#define RP23XX_RESETS_RESET_TBMAN (1 << 22)
#define RP23XX_RESETS_RESET_SYSINFO (1 << 21)
#define RP23XX_RESETS_RESET_SYSCFG (1 << 20)
#define RP23XX_RESETS_RESET_SPI1 (1 << 19)
#define RP23XX_RESETS_RESET_SPI0 (1 << 18)
#define RP23XX_RESETS_RESET_SHA256 (1 << 17)
#define RP23XX_RESETS_RESET_PWM (1 << 16)
#define RP23XX_RESETS_RESET_PLL_USB (1 << 15)
#define RP23XX_RESETS_RESET_PLL_SYS (1 << 14)
#define RP23XX_RESETS_RESET_PIO2 (1 << 13)
#define RP23XX_RESETS_RESET_PIO1 (1 << 12)
#define RP23XX_RESETS_RESET_PIO0 (1 << 11)
#define RP23XX_RESETS_RESET_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_RESET_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_RESET_JTAG (1 << 8)
#define RP23XX_RESETS_RESET_IO_QSPI (1 << 7)
#define RP23XX_RESETS_RESET_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_RESET_I2C1 (1 << 5)
#define RP23XX_RESETS_RESET_I2C0 (1 << 4)
#define RP23XX_RESETS_RESET_HSTX (1 << 3)
#define RP23XX_RESETS_RESET_DMA (1 << 2)
#define RP23XX_RESETS_RESET_BUSCTRL (1 << 1)
#define RP23XX_RESETS_RESET_ADC (1 << 0)
#define RP23XX_RESETS_WDSEL_USBCTRL (1 << 28)
#define RP23XX_RESETS_WDSEL_UART1 (1 << 27)
#define RP23XX_RESETS_WDSEL_UART0 (1 << 26)
#define RP23XX_RESETS_WDSEL_TRNG (1 << 25)
#define RP23XX_RESETS_WDSEL_TIMER1 (1 << 24)
#define RP23XX_RESETS_WDSEL_TIMER0 (1 << 23)
#define RP23XX_RESETS_WDSEL_TBMAN (1 << 22)
#define RP23XX_RESETS_WDSEL_SYSINFO (1 << 21)
#define RP23XX_RESETS_WDSEL_SYSCFG (1 << 20)
#define RP23XX_RESETS_WDSEL_SPI1 (1 << 19)
#define RP23XX_RESETS_WDSEL_SPI0 (1 << 18)
#define RP23XX_RESETS_WDSEL_SHA256 (1 << 17)
#define RP23XX_RESETS_WDSEL_PWM (1 << 16)
#define RP23XX_RESETS_WDSEL_PLL_USB (1 << 15)
#define RP23XX_RESETS_WDSEL_PLL_SYS (1 << 14)
#define RP23XX_RESETS_WDSEL_PIO2 (1 << 13)
#define RP23XX_RESETS_WDSEL_PIO1 (1 << 12)
#define RP23XX_RESETS_WDSEL_PIO0 (1 << 11)
#define RP23XX_RESETS_WDSEL_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_WDSEL_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_WDSEL_JTAG (1 << 8)
#define RP23XX_RESETS_WDSEL_IO_QSPI (1 << 7)
#define RP23XX_RESETS_WDSEL_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_WDSEL_I2C1 (1 << 5)
#define RP23XX_RESETS_WDSEL_I2C0 (1 << 4)
#define RP23XX_RESETS_WDSEL_HSTX (1 << 3)
#define RP23XX_RESETS_WDSEL_DMA (1 << 2)
#define RP23XX_RESETS_WDSEL_BUSCTRL (1 << 1)
#define RP23XX_RESETS_WDSEL_ADC (1 << 0)
#define RP23XX_RESETS_RESET_DONE_USBCTRL (1 << 28)
#define RP23XX_RESETS_RESET_DONE_UART1 (1 << 27)
#define RP23XX_RESETS_RESET_DONE_UART0 (1 << 26)
#define RP23XX_RESETS_RESET_DONE_TRNG (1 << 25)
#define RP23XX_RESETS_RESET_DONE_TIMER1 (1 << 24)
#define RP23XX_RESETS_RESET_DONE_TIMER0 (1 << 23)
#define RP23XX_RESETS_RESET_DONE_TBMAN (1 << 22)
#define RP23XX_RESETS_RESET_DONE_SYSINFO (1 << 21)
#define RP23XX_RESETS_RESET_DONE_SYSCFG (1 << 20)
#define RP23XX_RESETS_RESET_DONE_SPI1 (1 << 19)
#define RP23XX_RESETS_RESET_DONE_SPI0 (1 << 18)
#define RP23XX_RESETS_RESET_DONE_SHA256 (1 << 17)
#define RP23XX_RESETS_RESET_DONE_PWM (1 << 16)
#define RP23XX_RESETS_RESET_DONE_PLL_USB (1 << 15)
#define RP23XX_RESETS_RESET_DONE_PLL_SYS (1 << 14)
#define RP23XX_RESETS_RESET_DONE_PIO2 (1 << 13)
#define RP23XX_RESETS_RESET_DONE_PIO1 (1 << 12)
#define RP23XX_RESETS_RESET_DONE_PIO0 (1 << 11)
#define RP23XX_RESETS_RESET_DONE_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_RESET_DONE_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_RESET_DONE_JTAG (1 << 8)
#define RP23XX_RESETS_RESET_DONE_IO_QSPI (1 << 7)
#define RP23XX_RESETS_RESET_DONE_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_RESET_DONE_I2C1 (1 << 5)
#define RP23XX_RESETS_RESET_DONE_I2C0 (1 << 4)
#define RP23XX_RESETS_RESET_DONE_HSTX (1 << 3)
#define RP23XX_RESETS_RESET_DONE_DMA (1 << 2)
#define RP23XX_RESETS_RESET_DONE_BUSCTRL (1 << 1)
#define RP23XX_RESETS_RESET_DONE_ADC (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_rosc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_ROSC_CTRL_OFFSET 0x00000000
#define RP23XX_ROSC_FREQA_OFFSET 0x00000004
#define RP23XX_ROSC_FREQB_OFFSET 0x00000008
#define RP23XX_ROSC_RANDOM_OFFSET 0x0000000c
#define RP23XX_ROSC_DORMANT_OFFSET 0x00000010
#define RP23XX_ROSC_DIV_OFFSET 0x00000014
#define RP23XX_ROSC_PHASE_OFFSET 0x00000018
#define RP23XX_ROSC_STATUS_OFFSET 0x0000001c
#define RP23XX_ROSC_RANDOMBIT_OFFSET 0x00000020
#define RP23XX_ROSC_COUNT_OFFSET 0x00000024
/* Register definitions *****************************************************/
#define RP23XX_ROSC_CTRL (RP23XX_ROSC_BASE + RP23XX_ROSC_CTRL_OFFSET)
#define RP23XX_ROSC_FREQA (RP23XX_ROSC_BASE + RP23XX_ROSC_FREQA_OFFSET)
#define RP23XX_ROSC_FREQB (RP23XX_ROSC_BASE + RP23XX_ROSC_FREQB_OFFSET)
#define RP23XX_ROSC_RANDOM (RP23XX_ROSC_BASE + RP23XX_ROSC_RANDOM_OFFSET)
#define RP23XX_ROSC_DORMANT (RP23XX_ROSC_BASE + RP23XX_ROSC_DORMANT_OFFSET)
#define RP23XX_ROSC_DIV (RP23XX_ROSC_BASE + RP23XX_ROSC_DIV_OFFSET)
#define RP23XX_ROSC_PHASE (RP23XX_ROSC_BASE + RP23XX_ROSC_PHASE_OFFSET)
#define RP23XX_ROSC_STATUS (RP23XX_ROSC_BASE + RP23XX_ROSC_STATUS_OFFSET)
#define RP23XX_ROSC_RANDOMBIT (RP23XX_ROSC_BASE + RP23XX_ROSC_RANDOMBIT_OFFSET)
#define RP23XX_ROSC_COUNT (RP23XX_ROSC_BASE + RP23XX_ROSC_COUNT_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_ROSC_CTRL_ENABLE_SHIFT (12) /* On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */
#define RP23XX_ROSC_CTRL_ENABLE_MASK (0xfff << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_ENABLE_DISABLE (0xd1e << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_ENABLE_ENABLE (0xfab << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_MASK (0xfff)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_LOW (0xfa4)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_MEDIUM (0xfa5)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_HIGH (0xfa7)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_TOOHIGH (0xfa6)
#define RP23XX_ROSC_FREQA_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
#define RP23XX_ROSC_FREQA_PASSWD_MASK (0xffff << RP23XX_ROSC_FREQA_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQA_PASSWD_PASS (0x9696 << RP23XX_ROSC_FREQA_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQA_DS3_SHIFT (12) /* Stage 3 drive strength */
#define RP23XX_ROSC_FREQA_DS3_MASK (0x07 << RP23XX_ROSC_FREQA_DS3_SHIFT)
#define RP23XX_ROSC_FREQA_DS2_SHIFT (8) /* Stage 2 drive strength */
#define RP23XX_ROSC_FREQA_DS2_MASK (0x07 << RP23XX_ROSC_FREQA_DS2_SHIFT)
#define RP23XX_ROSC_FREQA_DS1_SHIFT (4) /* Stage 1 drive strength */
#define RP23XX_ROSC_FREQA_DS1_MASK (0x07 << RP23XX_ROSC_FREQA_DS1_SHIFT)
#define RP23XX_ROSC_FREQA_DS0_MASK (0x07) /* Stage 0 drive strength */
#define RP23XX_ROSC_FREQB_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
#define RP23XX_ROSC_FREQB_PASSWD_MASK (0xffff << RP23XX_ROSC_FREQB_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQB_PASSWD_PASS (0x9696 << RP23XX_ROSC_FREQB_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQB_DS7_SHIFT (12) /* Stage 7 drive strength */
#define RP23XX_ROSC_FREQB_DS7_MASK (0x07 << RP23XX_ROSC_FREQB_DS7_SHIFT)
#define RP23XX_ROSC_FREQB_DS6_SHIFT (8) /* Stage 6 drive strength */
#define RP23XX_ROSC_FREQB_DS6_MASK (0x07 << RP23XX_ROSC_FREQB_DS6_SHIFT)
#define RP23XX_ROSC_FREQB_DS5_SHIFT (4) /* Stage 5 drive strength */
#define RP23XX_ROSC_FREQB_DS5_MASK (0x07 << RP23XX_ROSC_FREQB_DS5_SHIFT)
#define RP23XX_ROSC_FREQB_DS4_MASK (0x07) /* Stage 4 drive strength */
#define RP23XX_ROSC_DORMANT_DORMANT (0x636f6d61)
#define RP23XX_ROSC_DORMANT_WAKE (0x77616b65)
#define RP23XX_ROSC_DIV_MASK (0xffff)
#define RP23XX_ROSC_DIV_PASS (0xaa00)
#define RP23XX_ROSC_PHASE_PASSWD_SHIFT (4) /* set to 0xaa0 any other value enables the output with shift=0 */
#define RP23XX_ROSC_PHASE_PASSWD_MASK (0xff << RP23XX_ROSC_PHASE_PASSWD_SHIFT)
#define RP23XX_ROSC_PHASE_ENABLE (1 << 3) /* enable the phase-shifted output this can be changed on-the-fly */
#define RP23XX_ROSC_PHASE_FLIP (1 << 2) /* invert the phase-shifted output this is ignored when div=1 */
#define RP23XX_ROSC_PHASE_SHIFT_MASK (0x03) /* phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1 */
#define RP23XX_ROSC_STATUS_STABLE (1 << 31) /* Oscillator is running and stable */
#define RP23XX_ROSC_STATUS_BADWRITE (1 << 24) /* An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT */
#define RP23XX_ROSC_STATUS_DIV_RUNNING (1 << 16) /* post-divider is running this resets to 0 but transitions to 1 during chip startup */
#define RP23XX_ROSC_STATUS_ENABLED (1 << 12) /* Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup */
#define RP23XX_ROSC_RANDOMBIT_MASK (1 << 0)
#define RP23XX_ROSC_COUNT_MASK (0xffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_rp_ap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_RP_AP_CTRL_OFFSET 0x00000000
#define RP23XX_RP_AP_CTRL_BITS 0xc000007f
#define RP23XX_RP_AP_CTRL_RESET 0x00000000
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_RESET 0x0
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_BITS 0x80000000
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_MSB 31
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_LSB 31
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_SPARE_RESET 0x0
#define RP23XX_RP_AP_CTRL_SPARE_BITS 0x40000000
#define RP23XX_RP_AP_CTRL_SPARE_MSB 30
#define RP23XX_RP_AP_CTRL_SPARE_LSB 30
#define RP23XX_RP_AP_CTRL_SPARE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET 0x0
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS 0x00000040
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB 6
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB 6
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET 0x0
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS 0x00000020
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB 5
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB 5
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS 0x00000010
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB 4
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB 4
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_BITS 0x00000008
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_MSB 3
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_LSB 3
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_BITS 0x00000004
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_MSB 2
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_LSB 2
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_RESET 0x0
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_BITS 0x00000002
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_MSB 1
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_LSB 1
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_RESET 0x0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_BITS 0x00000001
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_MSB 0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_LSB 0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_OFFSET 0x00000004
#define RP23XX_RP_AP_DBGKEY_BITS 0x00000007
#define RP23XX_RP_AP_DBGKEY_RESET 0x00000000
#define RP23XX_RP_AP_DBGKEY_RESET_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_RESET_BITS 0x00000004
#define RP23XX_RP_AP_DBGKEY_RESET_MSB 2
#define RP23XX_RP_AP_DBGKEY_RESET_LSB 2
#define RP23XX_RP_AP_DBGKEY_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_PUSH_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_PUSH_BITS 0x00000002
#define RP23XX_RP_AP_DBGKEY_PUSH_MSB 1
#define RP23XX_RP_AP_DBGKEY_PUSH_LSB 1
#define RP23XX_RP_AP_DBGKEY_PUSH_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_DATA_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_DATA_BITS 0x00000001
#define RP23XX_RP_AP_DBGKEY_DATA_MSB 0
#define RP23XX_RP_AP_DBGKEY_DATA_LSB 0
#define RP23XX_RP_AP_DBGKEY_DATA_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_OFFSET 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS 0x00000800
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB 11
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB 11
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS 0x00000400
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB 10
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB 10
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS 0x00000200
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB 9
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB 9
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_OFFSET 0x0000000c
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_OFFSET 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_OFFSET 0x00000014
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_OVRD_OFFSET 0x00000018
#define RP23XX_RP_AP_DBG_POW_OVRD_BITS 0x0000007f
#define RP23XX_RP_AP_DBG_POW_OVRD_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB 6
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB 6
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB 5
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB 5
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB 4
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB 4
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB 3
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB 3
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB 2
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB 2
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB 1
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB 1
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB 0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB 0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET 0x0000001c
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET 0x000
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB 11
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB 0
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW"
#define RP23XX_RP_AP_IDR_OFFSET 0x00000dfc
#define RP23XX_RP_AP_IDR_BITS 0xffffffff
#define RP23XX_RP_AP_IDR_RESET "-"
#define RP23XX_RP_AP_IDR_MSB 31
#define RP23XX_RP_AP_IDR_LSB 0
#define RP23XX_RP_AP_IDR_ACCESS "RO"
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sha256.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_SHA256_CSR_OFFSET 0x00000000
#define RP23XX_SHA256_WDATA_OFFSET 0x00000004
#define RP23XX_SHA256_SUM_OFFSET(n) ((n) * 4 + 0x000008)
/* Register definitions *****************************************************/
#define RP23XX_SHA256_CSR (RP23XX_SHA256_BASE + RP23XX_SHA256_CSR_OFFSET)
#define RP23XX_SHA256_WDATA (RP23XX_SHA256_BASE + RP23XX_SHA256_WDATA_OFFSET)
#define RP23XX_SHA256_SUM(n) (RP23XX_SHA256_BASE + RP23XX_SHA256_SUM_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_SHA256_CSR_MASK (0x00001317)
#define RP23XX_SHA256_CSR_BSWAP (1 << 18)
#define RP23XX_SHA256_CSR_DMA_SIZE_MASK (0x00000300)
#define RP23XX_SHA256_CSR_ERR_WDATA_NOT_RDY (1 << 4)
#define RP23XX_SHA256_CSR_SUM_VLD (1 << 2)
#define RP23XX_SHA256_CSR_WDATA_RDY (1 << 1)
#define RP23XX_SHA256_CSR_START (1 << 0)
#define RP23XX_SHA256_WDATA_MASK (0xffffffff)
#define RP23XX_SHA256_SUM_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_SIO_CPUID_OFFSET 0x00000000
#define RP23XX_SIO_GPIO_IN_OFFSET 0x00000004
#define RP23XX_SIO_GPIO_HI_IN_OFFSET 0x00000008
#define RP23XX_SIO_GPIO_OUT_OFFSET 0x00000010
#define RP23XX_SIO_GPIO_HI_OUT_OFFSET 0x00000014
#define RP23XX_SIO_GPIO_OUT_SET_OFFSET 0x00000018
#define RP23XX_SIO_GPIO_HI_OUT_SET_OFFSET 0x0000001c
#define RP23XX_SIO_GPIO_OUT_CLR_OFFSET 0x00000020
#define RP23XX_SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000024
#define RP23XX_SIO_GPIO_OUT_XOR_OFFSET 0x00000028
#define RP23XX_SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000002c
#define RP23XX_SIO_GPIO_OE_OFFSET 0x00000030
#define RP23XX_SIO_GPIO_HI_OE_OFFSET 0x00000034
#define RP23XX_SIO_GPIO_OE_SET_OFFSET 0x00000038
#define RP23XX_SIO_GPIO_HI_OE_SET_OFFSET 0x0000003c
#define RP23XX_SIO_GPIO_OE_CLR_OFFSET 0x00000040
#define RP23XX_SIO_GPIO_HI_OE_CLR_OFFSET 0x00000044
#define RP23XX_SIO_GPIO_OE_XOR_OFFSET 0x00000048
#define RP23XX_SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c
#define RP23XX_SIO_FIFO_ST_OFFSET 0x00000050
#define RP23XX_SIO_FIFO_WR_OFFSET 0x00000054
#define RP23XX_SIO_FIFO_RD_OFFSET 0x00000058
#define RP23XX_SIO_SPINLOCK_ST_OFFSET 0x0000005c
#define RP23XX_SIO_INTERP0_ACCUM0_OFFSET 0x00000080
#define RP23XX_SIO_INTERP0_ACCUM1_OFFSET 0x00000084
#define RP23XX_SIO_INTERP0_BASE0_OFFSET 0x00000088
#define RP23XX_SIO_INTERP0_BASE1_OFFSET 0x0000008c
#define RP23XX_SIO_INTERP0_BASE2_OFFSET 0x00000090
#define RP23XX_SIO_INTERP0_POP_LANE0_OFFSET 0x00000094
#define RP23XX_SIO_INTERP0_POP_LANE1_OFFSET 0x00000098
#define RP23XX_SIO_INTERP0_POP_FULL_OFFSET 0x0000009c
#define RP23XX_SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0
#define RP23XX_SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4
#define RP23XX_SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac
#define RP23XX_SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0
#define RP23XX_SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4
#define RP23XX_SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8
#define RP23XX_SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc
#define RP23XX_SIO_INTERP1_ACCUM0_OFFSET 0x000000c0
#define RP23XX_SIO_INTERP1_ACCUM1_OFFSET 0x000000c4
#define RP23XX_SIO_INTERP1_BASE0_OFFSET 0x000000c8
#define RP23XX_SIO_INTERP1_BASE1_OFFSET 0x000000cc
#define RP23XX_SIO_INTERP1_BASE2_OFFSET 0x000000d0
#define RP23XX_SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4
#define RP23XX_SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8
#define RP23XX_SIO_INTERP1_POP_FULL_OFFSET 0x000000dc
#define RP23XX_SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0
#define RP23XX_SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4
#define RP23XX_SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec
#define RP23XX_SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0
#define RP23XX_SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4
#define RP23XX_SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8
#define RP23XX_SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc
#define RP23XX_SIO_SPINLOCK_OFFSET(n) ((n) * 4 + 0x000100)
#define RP23XX_SIO_DOORBELL_OUT_SET_OFFSET 0x00000180
#define RP23XX_SIO_DOORBELL_OUT_CLR_OFFSET 0x00000184
#define RP23XX_SIO_DOORBELL_IN_SET_OFFSET 0x00000188
#define RP23XX_SIO_DOORBELL_IN_CLR_OFFSET 0x0000018c
#define RP23XX_SIO_PERI_NONSEC_OFFSET 0x00000190
#define RP23XX_SIO_RISCV_SOFTIRQ_OFFSET 0x000001a0
#define RP23XX_SIO_MTIME_CTRL_OFFSET 0x000001a4
#define RP23XX_SIO_MTIME_OFFSET 0x000001b0
#define RP23XX_SIO_MTIMEH_OFFSET 0x000001b4
#define RP23XX_SIO_MTIMECMP_OFFSET 0x000001b8
#define RP23XX_SIO_MTIMECMPH_OFFSET 0x000001bc
#define RP23XX_SIO_TMDS_CTRL_OFFSET 0x000001c0
#define RP23XX_SIO_TMDS_WDATA_OFFSET 0x000001c4
#define RP23XX_SIO_TMDS_PEEK_SINGLE_OFFSET 0x000001c8
#define RP23XX_SIO_TMDS_POP_SINGLE_OFFSET 0x000001cc
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L0_OFFSET 0x000001d0
#define RP23XX_SIO_TMDS_POP_DOUBLE_L0_OFFSET 0x000001d4
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L1_OFFSET 0x000001d8
#define RP23XX_SIO_TMDS_POP_DOUBLE_L1_OFFSET 0x000001dc
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L2_OFFSET 0x000001e0
#define RP23XX_SIO_TMDS_POP_DOUBLE_L2_OFFSET 0x000001e4
/* Register definitions *****************************************************/
#define RP23XX_SIO_CPUID (RP23XX_SIO_BASE + RP23XX_SIO_CPUID_OFFSET)
#define RP23XX_SIO_GPIO_IN (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_IN_OFFSET)
#define RP23XX_SIO_GPIO_HI_IN (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_IN_OFFSET)
#define RP23XX_SIO_GPIO_OUT (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_OFFSET)
#define RP23XX_SIO_GPIO_OUT_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_SET_OFFSET)
#define RP23XX_SIO_GPIO_OUT_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_CLR_OFFSET)
#define RP23XX_SIO_GPIO_OUT_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_XOR_OFFSET)
#define RP23XX_SIO_GPIO_OE (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_OFFSET)
#define RP23XX_SIO_GPIO_OE_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_SET_OFFSET)
#define RP23XX_SIO_GPIO_OE_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_CLR_OFFSET)
#define RP23XX_SIO_GPIO_OE_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_XOR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_SET_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_CLR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_XOR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_SET_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_CLR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_XOR_OFFSET)
#define RP23XX_SIO_FIFO_ST (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_ST_OFFSET)
#define RP23XX_SIO_FIFO_WR (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_WR_OFFSET)
#define RP23XX_SIO_FIFO_RD (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_RD_OFFSET)
#define RP23XX_SIO_SPINLOCK_ST (RP23XX_SIO_BASE + RP23XX_SIO_SPINLOCK_ST_OFFSET)
#define RP23XX_SIO_DIV_UDIVIDEND (RP23XX_SIO_BASE + RP23XX_SIO_DIV_UDIVIDEND_OFFSET)
#define RP23XX_SIO_DIV_UDIVISOR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_UDIVISOR_OFFSET)
#define RP23XX_SIO_DIV_SDIVIDEND (RP23XX_SIO_BASE + RP23XX_SIO_DIV_SDIVIDEND_OFFSET)
#define RP23XX_SIO_DIV_SDIVISOR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_SDIVISOR_OFFSET)
#define RP23XX_SIO_DIV_QUOTIENT (RP23XX_SIO_BASE + RP23XX_SIO_DIV_QUOTIENT_OFFSET)
#define RP23XX_SIO_DIV_REMAINDER (RP23XX_SIO_BASE + RP23XX_SIO_DIV_REMAINDER_OFFSET)
#define RP23XX_SIO_DIV_CSR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_CSR_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM0_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM1_OFFSET)
#define RP23XX_SIO_INTERP0_BASE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE0_OFFSET)
#define RP23XX_SIO_INTERP0_BASE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE1_OFFSET)
#define RP23XX_SIO_INTERP0_BASE2 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE2_OFFSET)
#define RP23XX_SIO_INTERP0_POP_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_POP_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_POP_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_FULL_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_FULL_OFFSET)
#define RP23XX_SIO_INTERP0_CTRL_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_CTRL_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_CTRL_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_CTRL_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM0_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM0_ADD_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM1_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM1_ADD_OFFSET)
#define RP23XX_SIO_INTERP0_BASE_1AND0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE_1AND0_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM0_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM1_OFFSET)
#define RP23XX_SIO_INTERP1_BASE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE0_OFFSET)
#define RP23XX_SIO_INTERP1_BASE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE1_OFFSET)
#define RP23XX_SIO_INTERP1_BASE2 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE2_OFFSET)
#define RP23XX_SIO_INTERP1_POP_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_POP_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_POP_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_FULL_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_FULL_OFFSET)
#define RP23XX_SIO_INTERP1_CTRL_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_CTRL_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_CTRL_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_CTRL_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM0_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM0_ADD_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM1_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM1_ADD_OFFSET)
#define RP23XX_SIO_INTERP1_BASE_1AND0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE_1AND0_OFFSET)
#define RP23XX_SIO_SPINLOCK(n) (RP23XX_SIO_BASE + RP23XX_SIO_SPINLOCK_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_SIO_GPIO_IN_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_IN_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_IN_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_IN_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_IN_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_SET_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_SET_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_SET_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_SET_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_SET_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_CLR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_XOR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_SET_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_SET_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_SET_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_SET_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_SET_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_CLR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_CLR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_CLR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_CLR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_CLR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_XOR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_XOR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_XOR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_XOR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_XOR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_FIFO_ST_MASK (0x0000000f)
#define RP23XX_SIO_FIFO_ST_ROE (1 << 3)
#define RP23XX_SIO_FIFO_ST_WOF (1 << 2)
#define RP23XX_SIO_FIFO_ST_RDY (1 << 1)
#define RP23XX_SIO_FIFO_ST_VLD (1 << 0)
#define RP23XX_SIO_FIFO_WR_MASK (0xffffffff)
#define RP23XX_SIO_FIFO_RD_MASK (0xffffffff)
#define RP23XX_SIO_SPINLOCK_ST_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_ACCUM0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_ACCUM1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE2_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK (0x03bfffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF (1 << 25)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF1 (1 << 24)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF0 (1 << 23)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_BLEND (1 << 21)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK (0x001fffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP0_ACCUM0_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP0_ACCUM1_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP0_BASE_1AND0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_ACCUM0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_ACCUM1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE2_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK (0x03dfffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF (1 << 25)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF1 (1 << 24)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF0 (1 << 23)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CLAMP (1 << 22)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK (0x001fffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP1_ACCUM0_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP1_ACCUM1_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP1_BASE_1AND0_MASK (0xffffffff)
#define RP23XX_SIO_DOORBELL_OUT_SET_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_OUT_CLR_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_IN_SET_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_IN_CLR_MASK (0x000000ff)
#define RP23XX_SIO_PERI_NONSEC_MASK (0x00000023)
#define RP23XX_SIO_PERI_NONSEC_TMDS_MASK (0x00000020)
#define RP23XX_SIO_PERI_NONSEC_INTERP1 (1 << 1)
#define RP23XX_SIO_PERI_NONSEC_INTERP0 (1 << 0)
#define RP23XX_SIO_RISCV_SOFTIRQ_MASK (0x00000303)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE1_CLR (1 << 9)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE0_CLR (1 << 8)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE1_SET (1 << 1)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE0_SET (1 << 0)
#define RP23XX_SIO_MTIME_CTRL_MASK (0x0000000f)
#define RP23XX_SIO_MTIME_CTRL_DBGPAUSE_CORE1 (1 << 3)
#define RP23XX_SIO_MTIME_CTRL_DBGPAUSE_CORE0 (1 << 2)
#define RP23XX_SIO_MTIME_CTRL_FULLSPEED (1 << 1)
#define RP23XX_SIO_MTIME_CTRL_EN (1 << 0)
#define RP23XX_SIO_MTIME_MASK (0xffffffff)
#define RP23XX_SIO_MTIMEH_MASK (0xffffffff)
#define RP23XX_SIO_MTIMECMP_MASK (0xffffffff)
#define RP23XX_SIO_MTIMECMPH_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_CTRL_MASK (0x1f9fffff)
#define RP23XX_SIO_TMDS_CTRL_CLEAR_BALANCE (1 << 28)
#define RP23XX_SIO_TMDS_CTRL_PIX2_NOSHIFT (1 << 27)
#define RP23XX_SIO_TMDS_CTRL_PIX_SHIFT_MASK (0x07000000)
#define RP23XX_SIO_TMDS_CTRL_INTERLEAVE (1 << 23)
#define RP23XX_SIO_TMDS_CTRL_L2_NMASK_MASK (0x001c0000)
#define RP23XX_SIO_TMDS_CTRL_L1_NMASK_MASK (0x00038000)
#define RP23XX_SIO_TMDS_CTRL_L0_NMASK_MASK (0x00007000)
#define RP23XX_SIO_TMDS_CTRL_L2_ROT_MASK (0x00000f00)
#define RP23XX_SIO_TMDS_CTRL_L1_ROT_MASK (0x000000f0)
#define RP23XX_SIO_TMDS_CTRL_L0_ROT_MASK (0x0000000f)
#define RP23XX_SIO_TMDS_WDATA_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_SINGLE_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_SINGLE_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L0_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L0_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L1_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L1_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L2_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L2_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_spi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_SPI_SSPCR0_OFFSET 0x000000 /* Control register 0 */
#define RP23XX_RV_SPI_SSPCR1_OFFSET 0x000004 /* Control register 1 */
#define RP23XX_RV_SPI_SSPDR_OFFSET 0x000008 /* Data register */
#define RP23XX_RV_SPI_SSPSR_OFFSET 0x00000c /* Status register */
#define RP23XX_RV_SPI_SSPCPSR_OFFSET 0x000010 /* Clock prescale register */
#define RP23XX_RV_SPI_SSPIMSC_OFFSET 0x000014 /* Interrupt mask set or clear register */
#define RP23XX_RV_SPI_SSPRIS_OFFSET 0x000018 /* Raw interrupt status register */
#define RP23XX_RV_SPI_SSPMIS_OFFSET 0x00001c /* Masked interrupt status register */
#define RP23XX_RV_SPI_SSPICR_OFFSET 0x000020 /* Interrupt clear register */
#define RP23XX_RV_SPI_SSPDMACR_OFFSET 0x000024 /* DMA control register */
#define RP23XX_RV_SPI_SSPPERIPHID0_OFFSET 0x000fe0 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID1_OFFSET 0x000fe4 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID2_OFFSET 0x000fe8 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID3_OFFSET 0x000fec /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPCELLID0_OFFSET 0x000ff0 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID1_OFFSET 0x000ff4 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID2_OFFSET 0x000ff8 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID3_OFFSET 0x000ffc /* PrimeCell identification registers */
/* Register definitions *****************************************************/
#define RP23XX_RV_SPI_SSPCR0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCR0_OFFSET)
#define RP23XX_RV_SPI_SSPCR1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCR1_OFFSET)
#define RP23XX_RV_SPI_SSPDR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPDR_OFFSET)
#define RP23XX_RV_SPI_SSPSR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPSR_OFFSET)
#define RP23XX_RV_SPI_SSPCPSR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCPSR_OFFSET)
#define RP23XX_RV_SPI_SSPIMSC(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPIMSC_OFFSET)
#define RP23XX_RV_SPI_SSPRIS(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPRIS_OFFSET)
#define RP23XX_RV_SPI_SSPMIS(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPMIS_OFFSET)
#define RP23XX_RV_SPI_SSPICR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPICR_OFFSET)
#define RP23XX_RV_SPI_SSPDMACR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPDMACR_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID0_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID1_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID2(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID2_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID3(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID3_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID0_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID1_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID2(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID2_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID3(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID3_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_SPI_SSPCR0_SCR_SHIFT (8) /* Serial clock rate */
#define RP23XX_RV_SPI_SSPCR0_SCR_MASK (0xff << RP23XX_RV_SPI_SSPCR0_SCR_SHIFT)
#define RP23XX_RV_SPI_SSPCR0_SPH (1 << 7) /* SSPCLKOUT phase */
#define RP23XX_RV_SPI_SSPCR0_SPO (1 << 6) /* SSPCLKOUT polarity */
#define RP23XX_RV_SPI_SSPCR0_FRF_SHIFT (4) /* Frame format */
#define RP23XX_RV_SPI_SSPCR0_FRF_MASK (0x03 << RP23XX_RV_SPI_SSPCR0_FRF_SHIFT)
#define RP23XX_RV_SPI_SSPCR0_DSS_MASK (0x0f) /* Data Size Select */
#define RP23XX_RV_SPI_SSPCR0_DSS_SHIFT (0)
#define RP23XX_RV_SPI_SSPCR1_SOD (1 << 3) /* Slave-mode output disable */
#define RP23XX_RV_SPI_SSPCR1_MS (1 << 2) /* Master or slave mode select */
#define RP23XX_RV_SPI_SSPCR1_SSE (1 << 1) /* Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. */
#define RP23XX_RV_SPI_SSPCR1_LBM (1 << 0) /* Loop back mode */
#define RP23XX_RV_SPI_SSPDR_DATA_MASK (0xffff) /* Transmit/Receive FIFO */
#define RP23XX_RV_SPI_SSPSR_BSY (1 << 4) /* PrimeCell SSP busy flag */
#define RP23XX_RV_SPI_SSPSR_RFF (1 << 3) /* Receive FIFO full */
#define RP23XX_RV_SPI_SSPSR_RNE (1 << 2) /* Receive FIFO not empty */
#define RP23XX_RV_SPI_SSPSR_TNF (1 << 1) /* Transmit FIFO not full */
#define RP23XX_RV_SPI_SSPSR_TFE (1 << 0) /* Transmit FIFO empty */
#define RP23XX_RV_SPI_SSPCPSR_CPSDVSR_MASK (0xff) /* Clock prescale divisor. Must be an even number from 2-254 */
#define RP23XX_RV_SPI_SSPIMSC_TXIM (1 << 3) /* Transmit FIFO interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RXIM (1 << 2) /* Receive FIFO interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RTIM (1 << 1) /* Receive timeout interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RORIM (1 << 0) /* Receive overrun interrupt mask */
#define RP23XX_RV_SPI_SSPRIS_TXRIS (1 << 3) /* Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RXRIS (1 << 2) /* Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RTRIS (1 << 1) /* Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RORRIS (1 << 0) /* Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_TXMIS (1 << 3) /* Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RXMIS (1 << 2) /* Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RTMIS (1 << 1) /* Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RORMIS (1 << 0) /* Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPICR_RTIC (1 << 1) /* Clears the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPICR_RORIC (1 << 0) /* Clears the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPDMACR_TXDMAE (1 << 1) /* Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */
#define RP23XX_RV_SPI_SSPDMACR_RXDMAE (1 << 0) /* Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. */
#define RP23XX_RV_SPI_SSPPERIPHID0_PARTNUMBER0_MASK (0xff) /* These bits read back as 0x22 */
#define RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_SHIFT (4) /* These bits read back as 0x1 */
#define RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_MASK (0x0f << RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_SHIFT)
#define RP23XX_RV_SPI_SSPPERIPHID1_PARTNUMBER1_MASK (0x0f) /* These bits read back as 0x0 */
#define RP23XX_RV_SPI_SSPPERIPHID2_REVISION_SHIFT (4) /* These bits return the peripheral revision */
#define RP23XX_RV_SPI_SSPPERIPHID2_REVISION_MASK (0x0f << RP23XX_RV_SPI_SSPPERIPHID2_REVISION_SHIFT)
#define RP23XX_RV_SPI_SSPPERIPHID2_DESIGNER1_MASK (0x0f) /* These bits read back as 0x4 */
#define RP23XX_RV_SPI_SSPPERIPHID3_CONFIGURATION_MASK (0xff) /* These bits read back as 0x00 */
#define RP23XX_RV_SPI_SSPPCELLID0_MASK (0xff) /* These bits read back as 0x0D */
#define RP23XX_RV_SPI_SSPPCELLID1_MASK (0xff) /* These bits read back as 0xF0 */
#define RP23XX_RV_SPI_SSPPCELLID2_MASK (0xff) /* These bits read back as 0x05 */
#define RP23XX_RV_SPI_SSPPCELLID3_MASK (0xff) /* These bits read back as 0xB1 */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_tbman.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_TBMAN_PLATFORM_OFFSET 0x00000000
/* Register definitions *****************************************************/
#define RP23XX_TBMAN_PLATFORM (RP23XX_TBMAN_BASE + RP23XX_TBMAN_PLATFORM_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_TBMAN_PLATFORM_MASK 0x00000007
#define RP23XX_TBMAN_PLATFORM_HDLSIM (1 << 2)
#define RP23XX_TBMAN_PLATFORM_FPGA (1 << 1)
#define RP23XX_TBMAN_PLATFORM_ASIC (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_ticks.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TICKS_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TICKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_TICKS_PROC0_CTRL_OFFSET 0x00000000
#define RP23XX_TICKS_PROC0_CYCLES_OFFSET 0x00000004
#define RP23XX_TICKS_PROC0_COUNT_OFFSET 0x00000008
#define RP23XX_TICKS_PROC1_CTRL_OFFSET 0x0000000c
#define RP23XX_TICKS_PROC1_CYCLES_OFFSET 0x00000010
#define RP23XX_TICKS_PROC1_COUNT_OFFSET 0x00000014
#define RP23XX_TICKS_TIMER0_CTRL_OFFSET 0x00000018
#define RP23XX_TICKS_TIMER0_CYCLES_OFFSET 0x0000001c
#define RP23XX_TICKS_TIMER0_COUNT_OFFSET 0x00000020
#define RP23XX_TICKS_TIMER1_CTRL_OFFSET 0x00000024
#define RP23XX_TICKS_TIMER1_CYCLES_OFFSET 0x00000028
#define RP23XX_TICKS_TIMER1_COUNT_OFFSET 0x0000002c
#define RP23XX_TICKS_WATCHDOG_CTRL_OFFSET 0x00000030
#define RP23XX_TICKS_WATCHDOG_CYCLES_OFFSET 0x00000034
#define RP23XX_TICKS_WATCHDOG_COUNT_OFFSET 0x00000038
#define RP23XX_TICKS_CTRL_OFFSET(n) ((n) * 12 + RP23XX_TICKS_PROC0_CTRL_OFFSET)
#define RP23XX_TICKS_CYCLES_OFFSET(n) ((n) * 12 + RP23XX_TICKS_PROC0_CYCLES_OFFSET)
#define RP23XX_TICKS_COUNT_OFFSET(n) ((n) * 12 + RP23XX_TICKS_PROC0_COUNT_OFFSET)
/* Register definitions *****************************************************/
#define RP23XX_TICKS_CTRL(n) (RP23XX_TICKS_BASE + RP23XX_TICKS_CTRL_OFFSET(n))
#define RP23XX_TICKS_CYCLES(n) (RP23XX_TICKS_BASE + RP23XX_TICKS_CYCLES_OFFSET(n))
#define RP23XX_TICKS_COUNT(n) (RP23XX_TICKS_BASE + RP23XX_TICKS_COUNT_OFFSET(n))
#define RP23XX_TICKS_PROC0_CTRL (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC0_CTRL_OFFSET)
#define RP23XX_TICKS_PROC0_CYCLES (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC0_CYCLES_OFFSET)
#define RP23XX_TICKS_PROC0_COUNT (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC0_COUNT_OFFSET)
#define RP23XX_TICKS_PROC1_CTRL (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC1_CTRL_OFFSET)
#define RP23XX_TICKS_PROC1_CYCLES (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC1_CYCLES_OFFSET)
#define RP23XX_TICKS_PROC1_COUNT (RP23XX_TICKS_BASE + RP23XX_TICKS_PROC1_COUNT_OFFSET)
#define RP23XX_TICKS_TIMER0_CTRL (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER0_CTRL_OFFSET)
#define RP23XX_TICKS_TIMER0_CYCLES (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER0_CYCLES_OFFSET)
#define RP23XX_TICKS_TIMER0_COUNT (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER0_COUNT_OFFSET)
#define RP23XX_TICKS_TIMER1_CTRL (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER1_CTRL_OFFSET)
#define RP23XX_TICKS_TIMER1_CYCLES (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER1_CYCLES_OFFSET)
#define RP23XX_TICKS_TIMER1_COUNT (RP23XX_TICKS_BASE + RP23XX_TICKS_TIMER1_COUNT_OFFSET)
#define RP23XX_TICKS_WATCHDOG_CTRL (RP23XX_TICKS_BASE + RP23XX_TICKS_WATCHDOG_CTRL_OFFSET)
#define RP23XX_TICKS_WATCHDOG_CYCLES (RP23XX_TICKS_BASE + RP23XX_TICKS_WATCHDOG_CYCLES_OFFSET)
#define RP23XX_TICKS_WATCHDOG_COUNT (RP23XX_TICKS_BASE + RP23XX_TICKS_WATCHDOG_COUNT_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_TICKS_WATCHDOG_CTRL_EN (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TICKS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_timer.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TIMER_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_TIMER_TIMEHW_OFFSET 0x00000000
#define RP23XX_TIMER_TIMELW_OFFSET 0x00000004
#define RP23XX_TIMER_TIMEHR_OFFSET 0x00000008
#define RP23XX_TIMER_TIMELR_OFFSET 0x0000000c
#define RP23XX_TIMER_ALARM0_OFFSET 0x00000010
#define RP23XX_TIMER_ALARM1_OFFSET 0x00000014
#define RP23XX_TIMER_ALARM2_OFFSET 0x00000018
#define RP23XX_TIMER_ALARM3_OFFSET 0x0000001c
#define RP23XX_TIMER_ARMED_OFFSET 0x00000020
#define RP23XX_TIMER_TIMERAWH_OFFSET 0x00000024
#define RP23XX_TIMER_TIMERAWL_OFFSET 0x00000028
#define RP23XX_TIMER_DBGPAUSE_OFFSET 0x0000002c
#define RP23XX_TIMER_PAUSE_OFFSET 0x00000030
#define RP23XX_TIMER_LOCKED_OFFSET 0x00000034
#define RP23XX_TIMER_SOURCE_OFFSET 0x00000038
#define RP23XX_TIMER_INTR_OFFSET 0x0000003c
#define RP23XX_TIMER_INTE_OFFSET 0x00000040
#define RP23XX_TIMER_INTF_OFFSET 0x00000044
#define RP23XX_TIMER_INTS_OFFSET 0x00000048
/* Register definitions *****************************************************/
#define RP23XX_TIMER_TIMEHW (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMEHW_OFFSET)
#define RP23XX_TIMER_TIMELW (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMELW_OFFSET)
#define RP23XX_TIMER_TIMEHR (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMEHR_OFFSET)
#define RP23XX_TIMER_TIMELR (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMELR_OFFSET)
#define RP23XX_TIMER_ALARM0 (RP23XX_TIMER_BASE + RP23XX_TIMER_ALARM0_OFFSET)
#define RP23XX_TIMER_ALARM1 (RP23XX_TIMER_BASE + RP23XX_TIMER_ALARM1_OFFSET)
#define RP23XX_TIMER_ALARM2 (RP23XX_TIMER_BASE + RP23XX_TIMER_ALARM2_OFFSET)
#define RP23XX_TIMER_ALARM3 (RP23XX_TIMER_BASE + RP23XX_TIMER_ALARM3_OFFSET)
#define RP23XX_TIMER_ARMED (RP23XX_TIMER_BASE + RP23XX_TIMER_ARMED_OFFSET)
#define RP23XX_TIMER_TIMERAWH (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMERAWH_OFFSET)
#define RP23XX_TIMER_TIMERAWL (RP23XX_TIMER_BASE + RP23XX_TIMER_TIMERAWL_OFFSET)
#define RP23XX_TIMER_DBGPAUSE (RP23XX_TIMER_BASE + RP23XX_TIMER_DBGPAUSE_OFFSET)
#define RP23XX_TIMER_PAUSE (RP23XX_TIMER_BASE + RP23XX_TIMER_PAUSE_OFFSET)
#define RP23XX_TIMER_LOCKED (RP23XX_TIMER_BASE + RP23XX_TIMER_LOCKED_OFFSET)
#define RP23XX_TIMER_SOURCE (RP23XX_TIMER_BASE + RP23XX_TIMER_SOURCE_OFFSET)
#define RP23XX_TIMER_INTR (RP23XX_TIMER_BASE + RP23XX_TIMER_INTR_OFFSET)
#define RP23XX_TIMER_INTE (RP23XX_TIMER_BASE + RP23XX_TIMER_INTE_OFFSET)
#define RP23XX_TIMER_INTF (RP23XX_TIMER_BASE + RP23XX_TIMER_INTF_OFFSET)
#define RP23XX_TIMER_INTS (RP23XX_TIMER_BASE + RP23XX_TIMER_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_TIMER_DBGPAUSE_DBG1_MASK (1 << 2)
#define RP23XX_TIMER_DBGPAUSE_DBG0_MASK (1 << 1)
#define RP23XX_TIMER_PAUSE_MASK (1 << 0)
#define RP23XX_TIMER_LOCKED_MASK (1 << 0)
#define RP23XX_TIMER_SOURCE_MASK (1 << 0)
#define RP23XX_TIMER_SOURCE_CLK_SYS_MASK (1 << 0)
#define RP23XX_TIMER_INTR_ALARM_3_MASK (1 << 3)
#define RP23XX_TIMER_INTR_ALARM_2_MASK (1 << 2)
#define RP23XX_TIMER_INTR_ALARM_1_MASK (1 << 1)
#define RP23XX_TIMER_INTR_ALARM_0_MASK (1 << 0)
#define RP23XX_TIMER_INTE_ALARM_3_MASK (1 << 3)
#define RP23XX_TIMER_INTE_ALARM_2_MASK (1 << 2)
#define RP23XX_TIMER_INTE_ALARM_1_MASK (1 << 1)
#define RP23XX_TIMER_INTE_ALARM_0_MASK (1 << 0)
#define RP23XX_TIMER_INTF_ALARM_3_MASK (1 << 3)
#define RP23XX_TIMER_INTF_ALARM_2_MASK (1 << 2)
#define RP23XX_TIMER_INTF_ALARM_1_MASK (1 << 1)
#define RP23XX_TIMER_INTF_ALARM_0_MASK (1 << 0)
#define RP23XX_TIMER_INTS_ALARM_3_MASK (1 << 3)
#define RP23XX_TIMER_INTS_ALARM_2_MASK (1 << 2)
#define RP23XX_TIMER_INTS_ALARM_1_MASK (1 << 1)
#define RP23XX_TIMER_INTS_ALARM_0_MASK (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TIMER_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_trng.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TRNG_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TRNG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_TRNG_RNG_IMR_OFFSET 0x00000100
#define RP23XX_TRNG_RNG_ISR_OFFSET 0x00000104
#define RP23XX_TRNG_RNG_ICR_OFFSET 0x00000108
#define RP23XX_TRNG_TRNG_CONFIG_OFFSET 0x0000010c
#define RP23XX_TRNG_TRNG_VALID_OFFSET 0x00000110
#define RP23XX_TRNG_EHR_DATA_OFFSET(n) (0x000114 + (n) * 4)
#define RP23XX_TRNG_RND_SOURCE_ENABLE_OFFSET 0x0000012c
#define RP23XX_TRNG_SAMPLE_CNT1_OFFSET 0x00000130
#define RP23XX_TRNG_AUTOCORR_STATISTIC_OFFSET 0x00000134
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL_OFFSET 0x00000138
#define RP23XX_TRNG_TRNG_SW_RESET_OFFSET 0x00000140
#define RP23XX_TRNG_RNG_DEBUG_EN_INPUT_OFFSET 0x000001b4
#define RP23XX_TRNG_TRNG_BUSY_OFFSET 0x000001b8
#define RP23XX_TRNG_RST_BITS_COUNTER_OFFSET 0x000001bc
#define RP23XX_TRNG_RNG_VERSION_OFFSET 0x000001c0
#define RP23XX_TRNG_RNG_BIST_CNTR_0_OFFSET 0x000001e0
#define RP23XX_TRNG_RNG_BIST_CNTR_1_OFFSET 0x000001e4
#define RP23XX_TRNG_RNG_BIST_CNTR_2_OFFSET 0x000001e8
/* Register definitions *****************************************************/
#define RP23XX_TRNG_RNG_IMR (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_IMR_OFFSET)
#define RP23XX_TRNG_RNG_ISR (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_ISR_OFFSET)
#define RP23XX_TRNG_RNG_ICR (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_ICR_OFFSET)
#define RP23XX_TRNG_TRNG_CONFIG (RP23XX_TRNG_BASE + RP23XX_TRNG_TRNG_CONFIG_OFFSET)
#define RP23XX_TRNG_TRNG_VALID (RP23XX_TRNG_BASE + RP23XX_TRNG_TRNG_VALID_OFFSET)
#define RP23XX_TRNG_EHR_DATA(n) (RP23XX_TRNG_BASE + RP23XX_TRNG_EHR_DATA_OFFSET(n))
#define RP23XX_TRNG_RND_SOURCE_ENABLE (RP23XX_TRNG_BASE + RP23XX_TRNG_RND_SOURCE_ENABLE_OFFSET)
#define RP23XX_TRNG_SAMPLE_CNT1 (RP23XX_TRNG_BASE + RP23XX_TRNG_SAMPLE_CNT1_OFFSET)
#define RP23XX_TRNG_AUTOCORR_STATISTIC (RP23XX_TRNG_BASE + RP23XX_TRNG_AUTOCORR_STATISTIC_OFFSET)
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL (RP23XX_TRNG_BASE + RP23XX_TRNG_TRNG_DEBUG_CONTROL_OFFSET)
#define RP23XX_TRNG_TRNG_SW_RESET (RP23XX_TRNG_BASE + RP23XX_TRNG_TRNG_SW_RESET_OFFSET)
#define RP23XX_TRNG_RNG_DEBUG_EN_INPUT (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_DEBUG_EN_INPUT_OFFSET)
#define RP23XX_TRNG_TRNG_BUSY (RP23XX_TRNG_BASE + RP23XX_TRNG_TRNG_BUSY_OFFSET)
#define RP23XX_TRNG_RST_BITS_COUNTER (RP23XX_TRNG_BASE + RP23XX_TRNG_RST_BITS_COUNTER_OFFSET)
#define RP23XX_TRNG_RNG_VERSION (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_VERSION_OFFSET)
#define RP23XX_TRNG_RNG_BIST_CNTR_0 (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_BIST_CNTR_0_OFFSET)
#define RP23XX_TRNG_RNG_BIST_CNTR_1 (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_BIST_CNTR_1_OFFSET)
#define RP23XX_TRNG_RNG_BIST_CNTR_2 (RP23XX_TRNG_BASE + RP23XX_TRNG_RNG_BIST_CNTR_2_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_TRNG_RNG_IMR_VN_ERR_INT_MASK (1 << 3)
#define RP23XX_TRNG_RNG_IMR_CRNGT_ERR_INT_MASK (1 << 2)
#define RP23XX_TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK (1 << 1)
#define RP23XX_TRNG_RNG_IMR_EHR_VALID_INT_MASK (1 << 0)
#define RP23XX_TRNG_RNG_ISR_VN_ERR (1 << 3)
#define RP23XX_TRNG_RNG_ISR_CRNGT_ERR (1 << 2)
#define RP23XX_TRNG_RNG_ISR_AUTOCORR_ERR (1 << 1)
#define RP23XX_TRNG_RNG_ISR_EHR_VALID (1 << 0)
#define RP23XX_TRNG_RNG_ICR_VN_ERR (1 << 3)
#define RP23XX_TRNG_RNG_ICR_CRNGT_ERR (1 << 2)
#define RP23XX_TRNG_RNG_ICR_AUTOCORR_ERR (1 << 1)
#define RP23XX_TRNG_RNG_ICR_EHR_VALID (1 << 0)
#define RP23XX_TRNG_TRNG_CONFIG_RND_SRC_SEL_MASK (0x00000003)
#define RP23XX_TRNG_TRNG_VALID_EHR_VALID (1 << 0)
#define RP23XX_TRNG_RND_SOURCE_ENABLE_RND_SRC_EN (1 << 0)
#define RP23XX_TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_SHIFT (14)
#define RP23XX_TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MASK (0xff << RP23XX_TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_SHIFT)
#define RP23XX_TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MASK (0x00003fff)
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS (1 << 3)
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS (1 << 2)
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS (1 << 1)
#define RP23XX_TRNG_TRNG_DEBUG_CONTROL_RESERVED (1 << 0)
#define RP23XX_TRNG_TRNG_SW_RESET_TRNG_SW_RESET (1 << 0)
#define RP23XX_TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN (1 << 0)
#define RP23XX_TRNG_TRNG_BUSY_TRNG_BUSY (1 << 0)
#define RP23XX_TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER (1 << 0)
#define RP23XX_TRNG_RNG_VERSION_RNG_USE_5_SBOXES (1 << 7)
#define RP23XX_TRNG_RNG_VERSION_RESEEDING_EXISTS (1 << 6)
#define RP23XX_TRNG_RNG_VERSION_KAT_EXISTS (1 << 5)
#define RP23XX_TRNG_RNG_VERSION_PRNG_EXISTS (1 << 4)
#define RP23XX_TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN (1 << 3)
#define RP23XX_TRNG_RNG_VERSION_AUTOCORR_EXISTS (1 << 2)
#define RP23XX_TRNG_RNG_VERSION_CRNGT_EXISTS (1 << 1)
#define RP23XX_TRNG_RNG_VERSION_EHR_WIDTH_192 (1 << 0)
#define RP23XX_TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MASK (0x003fffff)
#define RP23XX_TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MASK (0x003fffff)
#define RP23XX_TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MASK (0x003fffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TRNG_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_UART_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_UART_UARTDR_OFFSET 0x000000 /* Data Register, UARTDR */
#define RP23XX_RV_UART_UARTRSR_OFFSET 0x000004 /* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */
#define RP23XX_RV_UART_UARTFR_OFFSET 0x000018 /* Flag Register, UARTFR */
#define RP23XX_RV_UART_UARTILPR_OFFSET 0x000020 /* IrDA Low-Power Counter Register, UARTILPR */
#define RP23XX_RV_UART_UARTIBRD_OFFSET 0x000024 /* Integer Baud Rate Register, UARTIBRD */
#define RP23XX_RV_UART_UARTFBRD_OFFSET 0x000028 /* Fractional Baud Rate Register, UARTFBRD */
#define RP23XX_RV_UART_UARTLCR_H_OFFSET 0x00002c /* Line Control Register, UARTLCR_H */
#define RP23XX_RV_UART_UARTCR_OFFSET 0x000030 /* Control Register, UARTCR */
#define RP23XX_RV_UART_UARTIFLS_OFFSET 0x000034 /* Interrupt FIFO Level Select Register, UARTIFLS */
#define RP23XX_RV_UART_UARTIMSC_OFFSET 0x000038 /* Interrupt Mask Set/Clear Register, UARTIMSC */
#define RP23XX_RV_UART_UARTRIS_OFFSET 0x00003c /* Raw Interrupt Status Register, UARTRIS */
#define RP23XX_RV_UART_UARTMIS_OFFSET 0x000040 /* Masked Interrupt Status Register, UARTMIS */
#define RP23XX_RV_UART_UARTICR_OFFSET 0x000044 /* Interrupt Clear Register, UARTICR */
#define RP23XX_RV_UART_UARTDMACR_OFFSET 0x000048 /* DMA Control Register, UARTDMACR */
#define RP23XX_RV_UART_UARTPERIPHID0_OFFSET 0x000fe0 /* UARTPeriphID0 Register */
#define RP23XX_RV_UART_UARTPERIPHID1_OFFSET 0x000fe4 /* UARTPeriphID1 Register */
#define RP23XX_RV_UART_UARTPERIPHID2_OFFSET 0x000fe8 /* UARTPeriphID2 Register */
#define RP23XX_RV_UART_UARTPERIPHID3_OFFSET 0x000fec /* UARTPeriphID3 Register */
#define RP23XX_RV_UART_UARTPCELLID0_OFFSET 0x000ff0 /* UARTPCellID0 Register */
#define RP23XX_RV_UART_UARTPCELLID1_OFFSET 0x000ff4 /* UARTPCellID1 Register */
#define RP23XX_RV_UART_UARTPCELLID2_OFFSET 0x000ff8 /* UARTPCellID2 Register */
#define RP23XX_RV_UART_UARTPCELLID3_OFFSET 0x000ffc /* UARTPCellID3 Register */
/* Register definitions (UART) **********************************************/
#define RP23XX_RV_UART0_UARTDR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTDR_OFFSET)
#define RP23XX_RV_UART0_UARTRSR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTRSR_OFFSET)
#define RP23XX_RV_UART0_UARTFR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTFR_OFFSET)
#define RP23XX_RV_UART0_UARTILPR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTILPR_OFFSET)
#define RP23XX_RV_UART0_UARTIBRD (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTIBRD_OFFSET)
#define RP23XX_RV_UART0_UARTFBRD (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTFBRD_OFFSET)
#define RP23XX_RV_UART0_UARTLCR_H (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTLCR_H_OFFSET)
#define RP23XX_RV_UART0_UARTCR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTCR_OFFSET)
#define RP23XX_RV_UART0_UARTIFLS (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTIFLS_OFFSET)
#define RP23XX_RV_UART0_UARTIMSC (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTIMSC_OFFSET)
#define RP23XX_RV_UART0_UARTRIS (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTRIS_OFFSET)
#define RP23XX_RV_UART0_UARTMIS (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTMIS_OFFSET)
#define RP23XX_RV_UART0_UARTICR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTICR_OFFSET)
#define RP23XX_RV_UART0_UARTDMACR (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTDMACR_OFFSET)
#define RP23XX_RV_UART0_UARTPERIPHID0 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPERIPHID0_OFFSET)
#define RP23XX_RV_UART0_UARTPERIPHID1 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPERIPHID1_OFFSET)
#define RP23XX_RV_UART0_UARTPERIPHID2 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPERIPHID2_OFFSET)
#define RP23XX_RV_UART0_UARTPERIPHID3 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPERIPHID3_OFFSET)
#define RP23XX_RV_UART0_UARTPCELLID0 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPCELLID0_OFFSET)
#define RP23XX_RV_UART0_UARTPCELLID1 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPCELLID1_OFFSET)
#define RP23XX_RV_UART0_UARTPCELLID2 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPCELLID2_OFFSET)
#define RP23XX_RV_UART0_UARTPCELLID3 (RP23XX_RV_UART0_BASE + RP23XX_RV_UART_UARTPCELLID3_OFFSET)
/* Register definitions (UART1) *********************************************/
#define RP23XX_RV_UART1_UARTDR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTDR_OFFSET)
#define RP23XX_RV_UART1_UARTRSR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTRSR_OFFSET)
#define RP23XX_RV_UART1_UARTFR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTFR_OFFSET)
#define RP23XX_RV_UART1_UARTILPR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTILPR_OFFSET)
#define RP23XX_RV_UART1_UARTIBRD (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTIBRD_OFFSET)
#define RP23XX_RV_UART1_UARTFBRD (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTFBRD_OFFSET)
#define RP23XX_RV_UART1_UARTLCR_H (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTLCR_H_OFFSET)
#define RP23XX_RV_UART1_UARTCR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTCR_OFFSET)
#define RP23XX_RV_UART1_UARTIFLS (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTIFLS_OFFSET)
#define RP23XX_RV_UART1_UARTIMSC (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTIMSC_OFFSET)
#define RP23XX_RV_UART1_UARTRIS (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTRIS_OFFSET)
#define RP23XX_RV_UART1_UARTMIS (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTMIS_OFFSET)
#define RP23XX_RV_UART1_UARTICR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTICR_OFFSET)
#define RP23XX_RV_UART1_UARTDMACR (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTDMACR_OFFSET)
#define RP23XX_RV_UART1_UARTPERIPHID0 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPERIPHID0_OFFSET)
#define RP23XX_RV_UART1_UARTPERIPHID1 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPERIPHID1_OFFSET)
#define RP23XX_RV_UART1_UARTPERIPHID2 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPERIPHID2_OFFSET)
#define RP23XX_RV_UART1_UARTPERIPHID3 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPERIPHID3_OFFSET)
#define RP23XX_RV_UART1_UARTPCELLID0 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPCELLID0_OFFSET)
#define RP23XX_RV_UART1_UARTPCELLID1 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPCELLID1_OFFSET)
#define RP23XX_RV_UART1_UARTPCELLID2 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPCELLID2_OFFSET)
#define RP23XX_RV_UART1_UARTPCELLID3 (RP23XX_RV_UART1_BASE + RP23XX_RV_UART_UARTPCELLID3_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_UART_UARTDR_OE (1 << 11)
#define RP23XX_RV_UART_UARTDR_BE (1 << 10)
#define RP23XX_RV_UART_UARTDR_PE (1 << 9)
#define RP23XX_RV_UART_UARTDR_FE (1 << 8)
#define RP23XX_RV_UART_UARTDR_DATA_MASK (0xff)
#define RP23XX_RV_UART_UARTRSR_OE (1 << 3)
#define RP23XX_RV_UART_UARTRSR_BE (1 << 2)
#define RP23XX_RV_UART_UARTRSR_PE (1 << 1)
#define RP23XX_RV_UART_UARTRSR_FE (1 << 0)
#define RP23XX_RV_UART_UARTFR_RI (1 << 8)
#define RP23XX_RV_UART_UARTFR_TXFE (1 << 7)
#define RP23XX_RV_UART_UARTFR_RXFF (1 << 6)
#define RP23XX_RV_UART_UARTFR_TXFF (1 << 5)
#define RP23XX_RV_UART_UARTFR_RXFE (1 << 4)
#define RP23XX_RV_UART_UARTFR_BUSY (1 << 3)
#define RP23XX_RV_UART_UARTFR_DCD (1 << 2)
#define RP23XX_RV_UART_UARTFR_DSR (1 << 1)
#define RP23XX_RV_UART_UARTFR_CTS (1 << 0)
#define RP23XX_RV_UART_UARTILPR_ILPDVSR_MASK (0xff)
#define RP23XX_RV_UART_UARTIBRD_BAUD_DIVINT_MASK (0xffff)
#define RP23XX_RV_UART_UARTFBRD_BAUD_DIVFRAC_MASK (0x3f)
#define RP23XX_RV_UART_UARTLCR_H_SPS (1 << 7)
#define RP23XX_RV_UART_UARTLCR_H_WLEN_SHIFT (5)
#define RP23XX_RV_UART_UARTLCR_H_WLEN_MASK (0x03 << RP23XX_RV_UART_UARTLCR_H_WLEN_SHIFT)
#define RP23XX_RV_UART_UARTLCR_H_FEN (1 << 4)
#define RP23XX_RV_UART_UARTLCR_H_STP2 (1 << 3)
#define RP23XX_RV_UART_UARTLCR_H_EPS (1 << 2)
#define RP23XX_RV_UART_UARTLCR_H_PEN (1 << 1)
#define RP23XX_RV_UART_UARTLCR_H_BRK (1 << 0)
#define RP23XX_RV_UART_LCR_H_WLEN(x) ((((x) - 5) << RP23XX_RV_UART_UARTLCR_H_WLEN_SHIFT) & RP23XX_RV_UART_UARTLCR_H_WLEN_MASK)
#define RP23XX_RV_UART_UARTCR_CTSEN (1 << 15)
#define RP23XX_RV_UART_UARTCR_RTSEN (1 << 14)
#define RP23XX_RV_UART_UARTCR_OUT2 (1 << 13)
#define RP23XX_RV_UART_UARTCR_OUT1 (1 << 12)
#define RP23XX_RV_UART_UARTCR_RTS (1 << 11)
#define RP23XX_RV_UART_UARTCR_DTR (1 << 10)
#define RP23XX_RV_UART_UARTCR_RXE (1 << 9)
#define RP23XX_RV_UART_UARTCR_TXE (1 << 8)
#define RP23XX_RV_UART_UARTCR_LBE (1 << 7)
#define RP23XX_RV_UART_UARTCR_SIRLP (1 << 2)
#define RP23XX_RV_UART_UARTCR_SIREN (1 << 1)
#define RP23XX_RV_UART_UARTCR_UARTEN (1 << 0)
#define RP23XX_RV_UART_UARTIFLS_RXIFLSEL_SHIFT (3)
#define RP23XX_RV_UART_UARTIFLS_RXIFLSEL_MASK (0x07 << RP23XX_RV_UART_UARTIFLS_RXIFLSEL_SHIFT)
#define RP23XX_RV_UART_UARTIFLS_TXIFLSEL_MASK (0x07)
#define RP23XX_RV_UART_INTR_ALL (0x7ff) /* All of interrupts */
#define RP23XX_RV_UART_UARTIMSC_OEIM (1 << 10) /* Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_BEIM (1 << 9) /* Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_PEIM (1 << 8) /* Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_FEIM (1 << 7) /* Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_RTIM (1 << 6) /* Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_TXIM (1 << 5) /* Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_RXIM (1 << 4) /* Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_DSRMIM (1 << 3) /* nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_DCDMIM (1 << 2) /* nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_CTSMIM (1 << 1) /* nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTIMSC_RIMIM (1 << 0) /* nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. */
#define RP23XX_RV_UART_UARTRIS_OERIS (1 << 10) /* Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_BERIS (1 << 9) /* Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_PERIS (1 << 8) /* Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_FERIS (1 << 7) /* Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_RTRIS (1 << 6) /* Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a */
#define RP23XX_RV_UART_UARTRIS_TXRIS (1 << 5) /* Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_RXRIS (1 << 4) /* Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_DSRRMIS (1 << 3) /* nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_DCDRMIS (1 << 2) /* nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_CTSRMIS (1 << 1) /* nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. */
#define RP23XX_RV_UART_UARTRIS_RIRMIS (1 << 0) /* nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_OEMIS (1 << 10) /* Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_BEMIS (1 << 9) /* Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_PEMIS (1 << 8) /* Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_FEMIS (1 << 7) /* Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_RTMIS (1 << 6) /* Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_TXMIS (1 << 5) /* Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_RXMIS (1 << 4) /* Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_DSRMMIS (1 << 3) /* nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_DCDMMIS (1 << 2) /* nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_CTSMMIS (1 << 1) /* nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. */
#define RP23XX_RV_UART_UARTMIS_RIMMIS (1 << 0) /* nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_OEIC (1 << 10) /* Overrun error interrupt clear. Clears the UARTOEINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_BEIC (1 << 9) /* Break error interrupt clear. Clears the UARTBEINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_PEIC (1 << 8) /* Parity error interrupt clear. Clears the UARTPEINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_FEIC (1 << 7) /* Framing error interrupt clear. Clears the UARTFEINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_RTIC (1 << 6) /* Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_TXIC (1 << 5) /* Transmit interrupt clear. Clears the UARTTXINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_RXIC (1 << 4) /* Receive interrupt clear. Clears the UARTRXINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_DSRMIC (1 << 3) /* nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_DCDMIC (1 << 2) /* nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_CTSMIC (1 << 1) /* nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. */
#define RP23XX_RV_UART_UARTICR_RIMIC (1 << 0) /* nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. */
#define RP23XX_RV_UART_UARTDMACR_DMAONERR (1 << 2)
#define RP23XX_RV_UART_UARTDMACR_TXDMAE (1 << 1) /* Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */
#define RP23XX_RV_UART_UARTDMACR_RXDMAE (1 << 0) /* Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. */
#define RP23XX_RV_UART_UARTPERIPHID0_PARTNUMBER0_MASK (0xff) /* These bits read back as 0x11 */
#define RP23XX_RV_UART_UARTPERIPHID1_DESIGNER0_SHIFT (4) /* These bits read back as 0x1 */
#define RP23XX_RV_UART_UARTPERIPHID1_DESIGNER0_MASK (0x0f << RP23XX_RV_UART_UARTPERIPHID1_DESIGNER0_SHIFT)
#define RP23XX_RV_UART_UARTPERIPHID1_PARTNUMBER1_MASK (0x0f) /* These bits read back as 0x0 */
#define RP23XX_RV_UART_UARTPERIPHID2_REVISION_SHIFT (4)
#define RP23XX_RV_UART_UARTPERIPHID2_REVISION_MASK (0x0f << RP23XX_RV_UART_UARTPERIPHID2_REVISION_SHIFT)
#define RP23XX_RV_UART_UARTPERIPHID2_DESIGNER1_MASK (0x0f)
#define RP23XX_RV_UART_UARTPERIPHID3_CONFIGURATION_MASK (0xff)
#define RP23XX_RV_UART_UARTPCELLID0_MASK (0xff)
#define RP23XX_RV_UART_UARTPCELLID1_MASK (0xff)
#define RP23XX_RV_UART_UARTPCELLID2_MASK (0xff)
#define RP23XX_RV_UART_UARTPCELLID3_MASK (0xff)
#endif

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_DPSRAM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_DPSRAM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_USBCTRL_DPSRAM_SETUP_PACKET_OFFSET 0x000000
#define RP23XX_USBCTRL_DPSRAM_EP_IN_CTRL_OFFSET(n) (0x000008 + ((n) - 1) * 8)
#define RP23XX_USBCTRL_DPSRAM_EP_OUT_CTRL_OFFSET(n) (0x00000c + ((n) - 1) * 8)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_OFFSET(n) (0x000008 + ((n) - 2) * 4)
#define RP23XX_USBCTRL_DPSRAM_EP_IN_BUF_CTRL_OFFSET(n) (0x000080 + (n) * 8)
#define RP23XX_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL_OFFSET(n) (0x000084 + (n) * 8)
#define RP23XX_USBCTRL_DPSRAM_EP_BUF_CTRL_OFFSET(n) (0x000080 + (n) * 4)
#define RP23XX_USBCTRL_DPSRAM_EP0_BUF_0_OFFSET 0x000100
#define RP23XX_USBCTRL_DPSRAM_EP0_BUF_1_OFFSET 0x000140
#define RP23XX_USBCTRL_DPSRAM_DATA_BUF_OFFSET 0x000180
/* Register definitions *****************************************************/
#define RP23XX_USBCTRL_DPSRAM_SETUP_PACKET (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_SETUP_PACKET_OFFSET)
#define RP23XX_USBCTRL_DPSRAM_EP_IN_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_IN_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP_OUT_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_OUT_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP_IN_BUF_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_IN_BUF_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_OUT_BUF_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP_BUF_CTRL(n) (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP_BUF_CTRL_OFFSET(n))
#define RP23XX_USBCTRL_DPSRAM_EP0_BUF_0 (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP0_BUF_0_OFFSET)
#define RP23XX_USBCTRL_DPSRAM_EP0_BUF_1 (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_EP0_BUF_1_OFFSET)
#define RP23XX_USBCTRL_DPSRAM_DATA_BUF (RP23XX_USBCTRL_DPSRAM_BASE + RP23XX_USBCTRL_DPSRAM_DATA_BUF_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_ENABLE (1 << 31)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_DOUBLE_BUF (1 << 30)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_INT_1BUF (1 << 29)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_INT_2BUF (1 << 28)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT (26)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_MASK (0x3 << RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_CTRL (0 << RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_ISO (1 << RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_BULK (2 << RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_INTR (3 << RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_TYPE_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_INT_STALL (1 << 17)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_INT_NAK (1 << 16)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_ADDR_SHIFT (6)
#define RP23XX_USBCTRL_DPSRAM_EP_CTRL_EP_ADDR_MASK (0xffc0)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_FULL1 (1 << 31)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LAST1 (1 << 30)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT (29)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_MASK (1 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA0_PID1 (0 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID1 (1 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID1_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_128 (0 << 27)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_256 (1 << 27)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_512 (2 << 27)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DBUF_OFF_1024 (3 << 27)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL1 (1 << 26)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_SHIFT (16)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_MASK (0x3ff << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN1_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_FULL (1 << 15)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LAST (1 << 14)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT (13)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_MASK (1 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA0_PID (0 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID (1 << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA_PID_SHIFT)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_SEL (1 << 12)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_STALL (1 << 11)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL (1 << 10)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_SHIFT (0)
#define RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK (0x3ff << RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_SHIFT)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_DPSRAM_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_REGS_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_REGS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_USBCTRL_REGS_ADDR_ENDP_OFFSET 0x000000 /* Device address and endpoint control */
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_OFFSET(n) (0x000004 + ((n) - 1) * 4)
/* Interrupt endpoint 1. Only valid for HOST mode. */
#define RP23XX_USBCTRL_REGS_MAIN_CTRL_OFFSET 0x000040 /* Main control register */
#define RP23XX_USBCTRL_REGS_SOF_WR_OFFSET 0x000044 /* Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. */
#define RP23XX_USBCTRL_REGS_SOF_RD_OFFSET 0x000048 /* Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_OFFSET 0x00004c /* SIE control register */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_OFFSET 0x000050 /* SIE status register */
#define RP23XX_USBCTRL_REGS_INT_EP_CTRL_OFFSET 0x000054 /* interrupt endpoint control register */
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_OFFSET 0x000058 /* Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. */
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x00005c /* Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. */
#define RP23XX_USBCTRL_REGS_EP_ABORT_OFFSET 0x000060 /* Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. */
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_OFFSET 0x000064 /* Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. */
#define RP23XX_USBCTRL_REGS_EP_STALL_ARM_OFFSET 0x000068 /* Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. */
#define RP23XX_USBCTRL_REGS_NAK_POLL_OFFSET 0x00006c /* Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. */
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_OFFSET 0x000070 /* Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. */
#define RP23XX_USBCTRL_REGS_USB_MUXING_OFFSET 0x000074 /* Where to connect the USB controller. Should be to_phy by default. */
#define RP23XX_USBCTRL_REGS_USB_PWR_OFFSET 0x000078 /* Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OFFSET 0x00007c /* This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_OFFSET 0x000080 /* Override enable for each control in usbphy_direct */
#define RP23XX_USBCTRL_REGS_USBPHY_TRIM_OFFSET 0x000084 /* Used to adjust trim values of USB phy pull down resistors. */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_OFFSET 0x000088 /* Used for debug only */
#define RP23XX_USBCTRL_REGS_INTR_OFFSET 0x00008c /* Raw Interrupts */
#define RP23XX_USBCTRL_REGS_INTE_OFFSET 0x000090 /* Interrupt Enable */
#define RP23XX_USBCTRL_REGS_INTF_OFFSET 0x000094 /* Interrupt Force */
#define RP23XX_USBCTRL_REGS_INTS_OFFSET 0x000098 /* Interrupt status after masking & forcing */
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW_OFFSET 0x000100 /* Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events */
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_OFFSET 0x000104 /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred */
#define RP23XX_USBCTRL_REGS_SM_STATE_OFFSET 0x000108
#define RP23XX_USBCTRL_REGS_EP_TX_ERROR_OFFSET 0x00010c /* TX error count for each endpoint. Write to each field to reset the counter to 0 */
#define RP23XX_USBCTRL_REGS_EP_RX_ERROR_OFFSET 0x000110 /* RX error count for each endpoint. Write to each field to reset the counter to 0 */
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_OFFSET 0x000114 /* Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn’t idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable */
/* Register definitions *****************************************************/
#define RP23XX_USBCTRL_REGS_ADDR_ENDP (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_ADDR_ENDP_OFFSET)
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN(n) (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_ADDR_ENDPN_OFFSET(n))
#define RP23XX_USBCTRL_REGS_MAIN_CTRL (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_MAIN_CTRL_OFFSET)
#define RP23XX_USBCTRL_REGS_SOF_WR (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SOF_WR_OFFSET)
#define RP23XX_USBCTRL_REGS_SOF_RD (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SOF_RD_OFFSET)
#define RP23XX_USBCTRL_REGS_SIE_CTRL (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SIE_CTRL_OFFSET)
#define RP23XX_USBCTRL_REGS_SIE_STATUS (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SIE_STATUS_OFFSET)
#define RP23XX_USBCTRL_REGS_INT_EP_CTRL (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_INT_EP_CTRL_OFFSET)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_BUFF_STATUS_OFFSET)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_ABORT (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_ABORT_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_ABORT_DONE_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_STALL_ARM (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_STALL_ARM_OFFSET)
#define RP23XX_USBCTRL_REGS_NAK_POLL (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_NAK_POLL_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_OFFSET)
#define RP23XX_USBCTRL_REGS_USB_MUXING (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_USB_MUXING_OFFSET)
#define RP23XX_USBCTRL_REGS_USB_PWR (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_USB_PWR_OFFSET)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OFFSET)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_OFFSET)
#define RP23XX_USBCTRL_REGS_USBPHY_TRIM (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_USBPHY_TRIM_OFFSET)
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_LINESTATE_TUNING_OFFSET)
#define RP23XX_USBCTRL_REGS_INTR (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_INTR_OFFSET)
#define RP23XX_USBCTRL_REGS_INTE (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_INTE_OFFSET)
#define RP23XX_USBCTRL_REGS_INTF (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_INTF_OFFSET)
#define RP23XX_USBCTRL_REGS_INTS (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_INTS_OFFSET)
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW_OFFSET)
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_OFFSET)
#define RP23XX_USBCTRL_REGS_SM_STATE (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_SM_STATE_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_TX_ERROR (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_TX_ERROR_OFFSET)
#define RP23XX_USBCTRL_REGS_EP_RX_ERROR (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_EP_RX_ERROR_OFFSET)
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG (RP23XX_USBCTRL_REGS_BASE + RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_SHIFT (16) /* Device endpoint to send data to. Only valid for HOST mode. */
#define RP23XX_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_MASK (0x0f << RP23XX_USBCTRL_REGS_ADDR_ENDP_ENDPOINT_SHIFT)
#define RP23XX_USBCTRL_REGS_ADDR_ENDP_ADDRESS_MASK (0x7f) /* In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. */
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_INTEP_PREAMBLE (1 << 26) /* Interrupt EP requires preamble (is a low speed device on a full speed hub) */
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_INTEP_DIR (1 << 25) /* Direction of the interrupt endpoint. In=0, Out=1 */
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_ENDPOINT_SHIFT (16) /* Endpoint number of the interrupt endpoint */
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_ENDPOINT_MASK (0x0f << RP23XX_USBCTRL_REGS_ADDR_ENDP1_ENDPOINT_SHIFT)
#define RP23XX_USBCTRL_REGS_ADDR_ENDPN_ADDRESS_MASK (0x7f) /* Device address */
#define RP23XX_USBCTRL_REGS_MAIN_CTRL_SIM_TIMING (1 << 31) /* Reduced timings for simulation */
#define RP23XX_USBCTRL_REGS_MAIN_CTRL_PHY_ISO (1 << 2) /* Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1 */
#define RP23XX_USBCTRL_REGS_MAIN_CTRL_HOST_NDEVICE (1 << 1) /* Device mode = 0, Host mode = 1 */
#define RP23XX_USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN (1 << 0) /* Enable controller */
#define RP23XX_USBCTRL_REGS_SOF_WR_COUNT_MASK (0x7ff)
#define RP23XX_USBCTRL_REGS_SOF_RD_COUNT_MASK (0x7ff)
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_STALL (1 << 31) /* Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_DOUBLE_BUF (1 << 30) /* Device: EP0 single buffered = 0, double buffered = 1 */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF (1 << 29) /* Device: Set bit in BUFF_STATUS for every buffer completed on EP0 */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_2BUF (1 << 28) /* Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_NAK (1 << 27) /* Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_DIRECT_EN (1 << 26) /* Direct bus drive enable */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_DIRECT_DP (1 << 25) /* Direct control of DP */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_DIRECT_DM (1 << 24) /* Direct control of DM */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET (1 << 19) /* Device: Stop EP0 on a short packet */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_TRANSCEIVER_PD (1 << 18) /* Power down bus transceiver */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_RPU_OPT (1 << 17) /* Device: Pull-up strength (0=1K2, 1=2k3) */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_PULLUP_EN (1 << 16) /* Device: Enable pull up resistor */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_PULLDOWN_EN (1 << 15) /* Host: Enable pull down resistors */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_RESET_BUS (1 << 13) /* Host: Reset bus */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_RESUME (1 << 12) /* Device: Remote wakeup. Device can initiate its own resume after suspend. */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_VBUS_EN (1 << 11) /* Host: Enable VBUS */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_KEEP_ALIVE_EN (1 << 10) /* Host: Enable keep alive packet (for low speed bus) */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_SOF_EN (1 << 9) /* Host: Enable SOF generation (for full speed bus) */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_SOF_SYNC (1 << 8) /* Host: Delay packet(s) until after SOF */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_PREAMBLE_EN (1 << 6) /* Host: Preable enable for LS device on FS hub */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_STOP_TRANS (1 << 4) /* Host: Stop transaction */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_RECEIVE_DATA (1 << 3) /* Host: Receive transaction (IN to host) */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_SEND_DATA (1 << 2) /* Host: Send transaction (OUT from host) */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_SEND_SETUP (1 << 1) /* Host: Send Setup packet */
#define RP23XX_USBCTRL_REGS_SIE_CTRL_START_TRANS (1 << 0) /* Host: Start transaction */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_DATA_SEQ_ERROR (1 << 31) /* Data Sequence Error. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_ACK_REC (1 << 30) /* ACK received. Raised by both host and device. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_STALL_REC (1 << 29) /* Host: STALL received */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_NAK_REC (1 << 28) /* Host: NAK received */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_TIMEOUT (1 << 27) /* RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_OVERFLOW (1 << 26) /* RX overflow is raised by the Serial RX engine if the incoming data is too fast. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_BIT_STUFF_ERROR (1 << 25) /* Bit Stuff Error. Raised by the Serial RX engine. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_CRC_ERROR (1 << 24) /* CRC Error. Raised by the Serial RX engine. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_ENDPOINT_ERROR (1 << 23) /* An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET (1 << 19) /* Device: bus reset received */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_TRANS_COMPLETE (1 << 18) /* Transaction complete. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_SETUP_REC (1 << 17) /* Device: Setup packet received */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_CONNECTED (1 << 16) /* Device: connected */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_RX_SHORT_PACKET (1 << 12) /* Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_RESUME (1 << 11) /* Host: Device has initiated a remote resume. Device: host has initiated a resume. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_VBUS_OVER_CURR (1 << 10) /* VBUS over current detected */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_SPEED_SHIFT (8) /* Host: device speed. Disconnected = 00, LS = 01, FS = 10 */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_SPEED_MASK (0x03 << RP23XX_USBCTRL_REGS_SIE_STATUS_SPEED_SHIFT)
#define RP23XX_USBCTRL_REGS_SIE_STATUS_SUSPENDED (1 << 4) /* Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_LINE_STATE_SHIFT (2) /* USB bus line state */
#define RP23XX_USBCTRL_REGS_SIE_STATUS_LINE_STATE_MASK (0x03 << RP23XX_USBCTRL_REGS_SIE_STATUS_LINE_STATE_SHIFT)
#define RP23XX_USBCTRL_REGS_SIE_STATUS_VBUS_DETECTED (1 << 0) /* Device: VBUS Detected */
#define RP23XX_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_SHIFT (1) /* Host: Enable interrupt endpoint 1 -> 15 */
#define RP23XX_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_MASK (0x7fff << RP23XX_USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_SHIFT)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP15_OUT (1 << 31)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP15_IN (1 << 30)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP14_OUT (1 << 29)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP14_IN (1 << 28)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP13_OUT (1 << 27)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP13_IN (1 << 26)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP12_OUT (1 << 25)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP12_IN (1 << 24)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP11_OUT (1 << 23)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP11_IN (1 << 22)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP10_OUT (1 << 21)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP10_IN (1 << 20)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP9_OUT (1 << 19)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP9_IN (1 << 18)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP8_OUT (1 << 17)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP8_IN (1 << 16)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP7_OUT (1 << 15)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP7_IN (1 << 14)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP6_OUT (1 << 13)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP6_IN (1 << 12)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP5_OUT (1 << 11)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP5_IN (1 << 10)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP4_OUT (1 << 9)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP4_IN (1 << 8)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP3_OUT (1 << 7)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP3_IN (1 << 6)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP2_OUT (1 << 5)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP2_IN (1 << 4)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP1_OUT (1 << 3)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP1_IN (1 << 2)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_BUFF_STATUS_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_OUT (1 << 31)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_IN (1 << 30)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_OUT (1 << 29)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_IN (1 << 28)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_OUT (1 << 27)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_IN (1 << 26)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_OUT (1 << 25)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_IN (1 << 24)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_OUT (1 << 23)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_IN (1 << 22)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_OUT (1 << 21)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_IN (1 << 20)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_OUT (1 << 19)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_IN (1 << 18)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_OUT (1 << 17)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_IN (1 << 16)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_OUT (1 << 15)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_IN (1 << 14)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_OUT (1 << 13)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_IN (1 << 12)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_OUT (1 << 11)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_IN (1 << 10)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_OUT (1 << 9)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_IN (1 << 8)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_OUT (1 << 7)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_IN (1 << 6)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_OUT (1 << 5)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_IN (1 << 4)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_OUT (1 << 3)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_IN (1 << 2)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP15_OUT (1 << 31)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP15_IN (1 << 30)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP14_OUT (1 << 29)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP14_IN (1 << 28)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP13_OUT (1 << 27)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP13_IN (1 << 26)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP12_OUT (1 << 25)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP12_IN (1 << 24)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP11_OUT (1 << 23)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP11_IN (1 << 22)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP10_OUT (1 << 21)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP10_IN (1 << 20)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP9_OUT (1 << 19)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP9_IN (1 << 18)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP8_OUT (1 << 17)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP8_IN (1 << 16)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP7_OUT (1 << 15)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP7_IN (1 << 14)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP6_OUT (1 << 13)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP6_IN (1 << 12)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP5_OUT (1 << 11)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP5_IN (1 << 10)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP4_OUT (1 << 9)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP4_IN (1 << 8)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP3_OUT (1 << 7)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP3_IN (1 << 6)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP2_OUT (1 << 5)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP2_IN (1 << 4)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP1_OUT (1 << 3)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP1_IN (1 << 2)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_EP_ABORT_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP15_OUT (1 << 31)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP15_IN (1 << 30)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP14_OUT (1 << 29)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP14_IN (1 << 28)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP13_OUT (1 << 27)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP13_IN (1 << 26)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP12_OUT (1 << 25)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP12_IN (1 << 24)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP11_OUT (1 << 23)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP11_IN (1 << 22)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP10_OUT (1 << 21)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP10_IN (1 << 20)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP9_OUT (1 << 19)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP9_IN (1 << 18)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP8_OUT (1 << 17)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP8_IN (1 << 16)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP7_OUT (1 << 15)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP7_IN (1 << 14)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP6_OUT (1 << 13)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP6_IN (1 << 12)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP5_OUT (1 << 11)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP5_IN (1 << 10)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP4_OUT (1 << 9)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP4_IN (1 << 8)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP3_OUT (1 << 7)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP3_IN (1 << 6)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP2_OUT (1 << 5)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP2_IN (1 << 4)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP1_OUT (1 << 3)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP1_IN (1 << 2)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_EP_ABORT_DONE_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_EP_STALL_ARM_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_EP_STALL_ARM_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_HI_SHIFT (28) /* Bits 9:6 of nak_retry count */
#define RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_HI_MASK (0xf << RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_HI_SHIFT)
#define RP23XX_USBCTRL_REGS_NAK_POLL_DELAY_FS_SHIFT (16) /* NAK polling interval for a full speed device */
#define RP23XX_USBCTRL_REGS_NAK_POLL_DELAY_FS_MASK (0x3ff << RP23XX_USBCTRL_REGS_NAK_POLL_DELAY_FS_SHIFT)
#define RP23XX_USBCTRL_REGS_NAK_POLL_EPX_STOPPED_ON_NAK (1 << 27) /* EPX polling has stopped because a nak was received */
#define RP23XX_USBCTRL_REGS_NAK_POLL_STOP_EPX_ON_NAK (1 << 26) /* Stop polling epx when a nak is received */
#define RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_LO_SHIFT (10) /* Bits 5:0 of nak_retry count */
#define RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_LO_MASK (0x3f << RP23XX_USBCTRL_REGS_NAK_POLL_RETRY_COUNT_LO_SHIFT)
#define RP23XX_USBCTRL_REGS_NAK_POLL_DELAY_LS_MASK (0x3ff) /* NAK polling interval for a low speed device */
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_OUT (1 << 31)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_IN (1 << 30)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_OUT (1 << 29)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_IN (1 << 28)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_OUT (1 << 27)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_IN (1 << 26)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_OUT (1 << 25)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_IN (1 << 24)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_OUT (1 << 23)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_IN (1 << 22)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_OUT (1 << 21)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_IN (1 << 20)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_OUT (1 << 19)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_IN (1 << 18)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_OUT (1 << 17)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_IN (1 << 16)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_OUT (1 << 15)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_IN (1 << 14)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_OUT (1 << 13)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_IN (1 << 12)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_OUT (1 << 11)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_IN (1 << 10)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_OUT (1 << 9)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_IN (1 << 8)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_OUT (1 << 7)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_IN (1 << 6)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_OUT (1 << 5)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_IN (1 << 4)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_OUT (1 << 3)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_IN (1 << 2)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_OUT (1 << 1)
#define RP23XX_USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_IN (1 << 0)
#define RP23XX_USBCTRL_REGS_USB_MUXING_SWAP_DPDM (1 << 31) /* Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls */
#define RP23XX_USBCTRL_REGS_USB_MUXING_USBPHY_AS_GPIO (1 << 4) /* Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller */
#define RP23XX_USBCTRL_REGS_USB_MUXING_SOFTCON (1 << 3)
#define RP23XX_USBCTRL_REGS_USB_MUXING_TO_DIGITAL_PAD (1 << 2)
#define RP23XX_USBCTRL_REGS_USB_MUXING_TO_EXTPHY (1 << 1)
#define RP23XX_USBCTRL_REGS_USB_MUXING_TO_PHY (1 << 0)
#define RP23XX_USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_EN (1 << 5)
#define RP23XX_USBCTRL_REGS_USB_PWR_OVERCURR_DETECT (1 << 4)
#define RP23XX_USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN (1 << 3)
#define RP23XX_USBCTRL_REGS_USB_PWR_VBUS_DETECT (1 << 2)
#define RP23XX_USBCTRL_REGS_USB_PWR_VBUS_EN_OVERRIDE_EN (1 << 1)
#define RP23XX_USBCTRL_REGS_USB_PWR_VBUS_EN (1 << 0)
#define RP23XX_USBCTRL_REGS_USBPHY_RX_DM_OVERRIDE (1 << 25) /* Override rx_dm value into controller */
#define RP23XX_USBCTRL_REGS_USBPHY_RX_DP_OVERRIDE (1 << 24) /* Override rx_dp value into controller */
#define RP23XX_USBCTRL_REGS_USBPHY_RX_DD_OVERRIDE (1 << 23) /* Override rx_dd value into controller */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DM_OVV (1 << 22) /* DM over voltage */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DP_OVV (1 << 21) /* DP over voltage */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DM_OVCN (1 << 20) /* DM overcurrent */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DP_OVCN (1 << 19) /* DP overcurrent */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_RX_DM (1 << 18) /* DPM pin state */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_RX_DP (1 << 17) /* DPP pin state */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_RX_DD (1 << 16) /* Differential RX */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_DIFFMODE (1 << 15) /* TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_FSSLEW (1 << 14) /* TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_PD (1 << 13) /* TX power down override (if override enable is set). 1 = powered down. */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_RX_PD (1 << 12) /* RX power down override (if override enable is set). 1 = powered down. */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_DM (1 << 11) /* Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_DP (1 << 10) /* Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_DM_OE (1 << 9) /* Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_TX_DP_OE (1 << 8) /* Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLDN_EN (1 << 6) /* DM pull down enable */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_EN (1 << 5) /* DM pull up enable */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_HISEL (1 << 4) /* Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLDN_EN (1 << 2) /* DP pull down enable */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_EN (1 << 1) /* DP pull up enable */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_HISEL (1 << 0) /* Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 */
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN (1 << 18)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN (1 << 17)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN (1 << 16)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN (1 << 15)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN (1 << 12)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN (1 << 11)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN (1 << 10)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN (1 << 9)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN (1 << 8)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN (1 << 7)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN (1 << 6)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN (1 << 5)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN (1 << 4)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN (1 << 3)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN (1 << 2)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN (1 << 1)
#define RP23XX_USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN (1 << 0)
#define RP23XX_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_SHIFT (8) /* Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required */
#define RP23XX_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_MASK (0x1f << RP23XX_USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_SHIFT)
#define RP23XX_USBCTRL_REGS_USBPHY_TRIM_DP_PULLDN_TRIM_MASK (0x1f) /* Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_SPARE_FIX_SHIFT (8)
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_SPARE_FIX_MASK (0xf << RP23XX_USBCTRL_REGS_LINESTATE_TUNING_SPARE_FIX_SHIFT)
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_DEV_LS_WAKE_FIX (1 << 7) /* Device - exit suspend on any non-idle signalling, not qualified with a 1ms time */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE (1 << 6) /* Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX (1 << 5) /* RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX (1 << 4) /* RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1 << 3) /* Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_MULTI_HUB_FIX (1 << 2) /* Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_LINESTATE_DELAY (1 << 1) /* Device/Host - add an extra 1-bit debounce of linestate sampling */
#define RP23XX_USBCTRL_REGS_LINESTATE_TUNING_RCV_DELAY (1 << 0) /* Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs */
#define RP23XX_USBCTRL_REGS_INTR_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */
#define RP23XX_USBCTRL_REGS_INTR_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */
#define RP23XX_USBCTRL_REGS_INTR_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTR_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */
#define RP23XX_USBCTRL_REGS_INTR_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTR_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */
#define RP23XX_USBCTRL_REGS_INTR_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */
#define RP23XX_USBCTRL_REGS_INTR_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */
#define RP23XX_USBCTRL_REGS_INTR_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */
#define RP23XX_USBCTRL_REGS_INTR_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */
#define RP23XX_USBCTRL_REGS_INTR_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */
#define RP23XX_USBCTRL_REGS_INTR_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */
#define RP23XX_USBCTRL_REGS_INTR_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */
#define RP23XX_USBCTRL_REGS_INTR_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */
#define RP23XX_USBCTRL_REGS_INTR_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */
#define RP23XX_USBCTRL_REGS_INTR_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */
#define RP23XX_USBCTRL_REGS_INTR_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */
#define RP23XX_USBCTRL_REGS_INTR_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTR_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTR_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */
#define RP23XX_USBCTRL_REGS_INTE_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */
#define RP23XX_USBCTRL_REGS_INTE_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */
#define RP23XX_USBCTRL_REGS_INTE_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTE_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */
#define RP23XX_USBCTRL_REGS_INTE_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTE_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */
#define RP23XX_USBCTRL_REGS_INTE_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */
#define RP23XX_USBCTRL_REGS_INTE_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */
#define RP23XX_USBCTRL_REGS_INTE_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */
#define RP23XX_USBCTRL_REGS_INTE_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */
#define RP23XX_USBCTRL_REGS_INTE_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */
#define RP23XX_USBCTRL_REGS_INTE_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */
#define RP23XX_USBCTRL_REGS_INTE_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */
#define RP23XX_USBCTRL_REGS_INTE_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */
#define RP23XX_USBCTRL_REGS_INTE_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */
#define RP23XX_USBCTRL_REGS_INTE_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */
#define RP23XX_USBCTRL_REGS_INTE_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */
#define RP23XX_USBCTRL_REGS_INTE_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTE_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTE_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */
#define RP23XX_USBCTRL_REGS_INTF_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */
#define RP23XX_USBCTRL_REGS_INTF_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */
#define RP23XX_USBCTRL_REGS_INTF_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTF_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */
#define RP23XX_USBCTRL_REGS_INTF_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTF_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */
#define RP23XX_USBCTRL_REGS_INTF_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */
#define RP23XX_USBCTRL_REGS_INTF_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */
#define RP23XX_USBCTRL_REGS_INTF_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */
#define RP23XX_USBCTRL_REGS_INTF_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */
#define RP23XX_USBCTRL_REGS_INTF_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */
#define RP23XX_USBCTRL_REGS_INTF_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */
#define RP23XX_USBCTRL_REGS_INTF_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */
#define RP23XX_USBCTRL_REGS_INTF_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */
#define RP23XX_USBCTRL_REGS_INTF_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */
#define RP23XX_USBCTRL_REGS_INTF_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */
#define RP23XX_USBCTRL_REGS_INTF_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */
#define RP23XX_USBCTRL_REGS_INTF_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTF_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTF_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */
#define RP23XX_USBCTRL_REGS_INTS_EP_STALL_NAK (1 << 19) /* Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. */
#define RP23XX_USBCTRL_REGS_INTS_ABORT_DONE (1 << 18) /* Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. */
#define RP23XX_USBCTRL_REGS_INTS_DEV_SOF (1 << 17) /* Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTS_SETUP_REQ (1 << 16) /* Device. Source: SIE_STATUS.SETUP_REC */
#define RP23XX_USBCTRL_REGS_INTS_DEV_RESUME_FROM_HOST (1 << 15) /* Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTS_DEV_SUSPEND (1 << 14) /* Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED */
#define RP23XX_USBCTRL_REGS_INTS_DEV_CONN_DIS (1 << 13) /* Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED */
#define RP23XX_USBCTRL_REGS_INTS_BUS_RESET (1 << 12) /* Source: SIE_STATUS.BUS_RESET */
#define RP23XX_USBCTRL_REGS_INTS_VBUS_DETECT (1 << 11) /* Source: SIE_STATUS.VBUS_DETECT */
#define RP23XX_USBCTRL_REGS_INTS_STALL (1 << 10) /* Source: SIE_STATUS.STALL_REC */
#define RP23XX_USBCTRL_REGS_INTS_ERROR_CRC (1 << 9) /* Source: SIE_STATUS.CRC_ERROR */
#define RP23XX_USBCTRL_REGS_INTS_ERROR_BIT_STUFF (1 << 8) /* Source: SIE_STATUS.BIT_STUFF_ERROR */
#define RP23XX_USBCTRL_REGS_INTS_ERROR_RX_OVERFLOW (1 << 7) /* Source: SIE_STATUS.RX_OVERFLOW */
#define RP23XX_USBCTRL_REGS_INTS_ERROR_RX_TIMEOUT (1 << 6) /* Source: SIE_STATUS.RX_TIMEOUT */
#define RP23XX_USBCTRL_REGS_INTS_ERROR_DATA_SEQ (1 << 5) /* Source: SIE_STATUS.DATA_SEQ_ERROR */
#define RP23XX_USBCTRL_REGS_INTS_BUFF_STATUS (1 << 4) /* Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. */
#define RP23XX_USBCTRL_REGS_INTS_TRANS_COMPLETE (1 << 3) /* Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. */
#define RP23XX_USBCTRL_REGS_INTS_HOST_SOF (1 << 2) /* Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD */
#define RP23XX_USBCTRL_REGS_INTS_HOST_RESUME (1 << 1) /* Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME */
#define RP23XX_USBCTRL_REGS_INTS_HOST_CONN_DIS (1 << 0) /* Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED */
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_RAW_MASK (0x1fffff) /* Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events */
#define RP23XX_USBCTRL_REGS_SOF_TIMESTAMP_LAST_MASK (0x1fffff) /* Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred */
#define RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_SHIFT (8)
#define RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_MASK (0xf << RP23XX_USBCTRL_REGS_SM_STATE_RX_DASM_SHIFT)
#define RP23XX_USBCTRL_REGS_SM_STATE_BC_STATE_SHIFT (5)
#define RP23XX_USBCTRL_REGS_SM_STATE_BC_STATE_MASK (0x7 << RP23XX_USBCTRL_REGS_SM_STATE_BC_STATE_SHIFT)
#define RP23XX_USBCTRL_REGS_SM_STATE_STATE_MASK (0x00001f)
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_FIRED (1 << 20)
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_RESET (1 << 19) /* Set to 1 to forcibly reset the device state machine on watchdog expiry */
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_ENABLE (1 << 18)
#define RP23XX_USBCTRL_REGS_DEV_SM_WATCHDOG_LIMIT_MASK (0x03ffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_USBCTRL_REGS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_watchdog.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_WATCHDOG_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_WATCHDOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_WATCHDOG_CTRL_OFFSET 0x000000
#define RP23XX_WATCHDOG_LOAD_OFFSET 0x000004
#define RP23XX_WATCHDOG_REASON_OFFSET 0x000008
#define RP23XX_WATCHDOG_SCRATCH_OFFSET(n) (0x00000c + (n) * 4)
/* Register definitions *****************************************************/
#define RP23XX_WATCHDOG_CTRL (RP23XX_WATCHDOG_BASE + RP23XX_WATCHDOG_CTRL_OFFSET)
#define RP23XX_WATCHDOG_LOAD (RP23XX_WATCHDOG_BASE + RP23XX_WATCHDOG_LOAD_OFFSET)
#define RP23XX_WATCHDOG_REASON (RP23XX_WATCHDOG_BASE + RP23XX_WATCHDOG_REASON_OFFSET)
#define RP23XX_WATCHDOG_SCRATCH(n) (RP23XX_WATCHDOG_BASE + RP23XX_WATCHDOG_SCRATCH_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_WATCHDOG_CTRL_TRIGGER (1 << 31)
#define RP23XX_WATCHDOG_CTRL_ENABLE (1 << 30)
#define RP23XX_WATCHDOG_CTRL_PAUSE_DBG1 (1 << 26)
#define RP23XX_WATCHDOG_CTRL_PAUSE_DBG0 (1 << 25)
#define RP23XX_WATCHDOG_CTRL_PAUSE_JTAG (1 << 24)
#define RP23XX_WATCHDOG_CTRL_TIME_MASK (0xffffff)
#define RP23XX_WATCHDOG_LOAD_MASK (0xffffff)
#define RP23XX_WATCHDOG_REASON_FORCE (1 << 1)
#define RP23XX_WATCHDOG_REASON_TIMER (1 << 0)
#define RP23XX_WATCHDOG_ENABLE_BITS (RP23XX_WATCHDOG_CTRL_ENABLE \
| RP23XX_WATCHDOG_CTRL_PAUSE_DBG0 \
| RP23XX_WATCHDOG_CTRL_PAUSE_DBG1 \
| RP23XX_WATCHDOG_CTRL_PAUSE_JTAG)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_WATCHDOG_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_xip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_XIP_CTRL_OFFSET 0x00000000
#define RP23XX_XIP_STAT_OFFSET 0x00000008
#define RP23XX_XIP_CTR_HIT_OFFSET 0x0000000c
#define RP23XX_XIP_CTR_ACC_OFFSET 0x00000010
#define RP23XX_XIP_STREAM_ADDR_OFFSET 0x00000014
#define RP23XX_XIP_STREAM_CTR_OFFSET 0x00000018
#define RP23XX_XIP_STREAM_FIFO_OFFSET 0x0000001c
/* Register definitions *****************************************************/
#define RP23XX_XIP_CTRL (RP23XX_XIP_BASE + RP23XX_XIP_CTRL_OFFSET)
#define RP23XX_XIP_STAT (RP23XX_XIP_BASE + RP23XX_XIP_STAT_OFFSET)
#define RP23XX_XIP_CTR_HIT (RP23XX_XIP_BASE + RP23XX_XIP_CTR_HIT_OFFSET)
#define RP23XX_XIP_CTR_ACC (RP23XX_XIP_BASE + RP23XX_XIP_CTR_ACC_OFFSET)
#define RP23XX_XIP_STREAM_ADDR (RP23XX_XIP_BASE + RP23XX_XIP_STREAM_ADDR_OFFSET)
#define RP23XX_XIP_STREAM_CTR (RP23XX_XIP_BASE + RP23XX_XIP_STREAM_CTR_OFFSET)
#define RP23XX_XIP_STREAM_FIFO (RP23XX_XIP_BASE + RP23XX_XIP_STREAM_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_XIP_CTRL_WRITABLE_M1 (1 << 11)
#define RP23XX_XIP_CTRL_WRITABLE_M0 (1 << 10)
#define RP23XX_XIP_CTRL_SPLIT_WAYS (1 << 9)
#define RP23XX_XIP_CTRL_MAINT_NONSEC (1 << 8)
#define RP23XX_XIP_CTRL_NO_UNTRANSLATED_NONSEC (1 << 7)
#define RP23XX_XIP_CTRL_NO_UNTRANSLATED_SEC (1 << 6)
#define RP23XX_XIP_CTRL_NO_UNCACHED_NONSEC (1 << 5)
#define RP23XX_XIP_CTRL_NO_UNCACHED_SEC (1 << 4)
#define RP23XX_XIP_CTRL_POWER_DOWN (1 << 3)
#define RP23XX_XIP_CTRL_EN_NONSECURE (1 << 1)
#define RP23XX_XIP_CTRL_EN_SECURE (1 << 0)
#define RP23XX_XIP_STAT_FIFO_FULL (1 << 2)
#define RP23XX_XIP_STAT_FIFO_EMPTY (1 << 1)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_xip_aux.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_AUX_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_AUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_XIP_AUX_STREAM_OFFSET 0x00000000
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_OFFSET 0x00000004
#define RP23XX_XIP_AUX_QMI_DIRECT_RX_OFFSET 0x00000008
/* Register definitions *****************************************************/
#define RP23XX_XIP_AUX_STREAM (RP23XX_XIP_AUX_BASE + RP23XX_XIP_AUX_STREAM_OFFSET)
#define RP23XX_XIP_AUX_QMI_DIRECT_TX (RP23XX_XIP_AUX_BASE + RP23XX_XIP_AUX_QMI_DIRECT_TX_OFFSET)
#define RP23XX_XIP_AUX_QMI_DIRECT_RX (RP23XX_XIP_AUX_BASE + RP23XX_XIP_AUX_QMI_DIRECT_RX_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_XIP_AUX_STREAM_MASK 0xffffffff
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_MASK 0x001fffff
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_NOPUSH_MASK 0x00100000
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_OE_MASK 0x00080000
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_DWIDTH_MASK 0x00040000
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_IWIDTH_MASK 0x00030000
#define RP23XX_XIP_AUX_QMI_DIRECT_TX_DATA_MASK 0x0000ffff
#define RP23XX_XIP_AUX_QMI_DIRECT_RX_MASK 0x0000ffff
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XIP_AUX_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_xosc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XOSC_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XOSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_XOSC_CTRL_OFFSET 0x00000000 /* Crystal Oscillator Control */
#define RP23XX_XOSC_STATUS_OFFSET 0x00000004 /* Crystal Oscillator Status */
#define RP23XX_XOSC_DORMANT_OFFSET 0x00000008 /* Crystal Oscillator pause control This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE WARNING: stop the PLLs before selecting dormant mode WARNING: setup the irq before selecting dormant mode */
#define RP23XX_XOSC_STARTUP_OFFSET 0x0000000c /* Controls the startup delay */
#define RP23XX_XOSC_COUNT_OFFSET 0x00000010 /* A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. */
/* Register definitions *****************************************************/
#define RP23XX_XOSC_CTRL (RP23XX_XOSC_BASE + RP23XX_XOSC_CTRL_OFFSET)
#define RP23XX_XOSC_STATUS (RP23XX_XOSC_BASE + RP23XX_XOSC_STATUS_OFFSET)
#define RP23XX_XOSC_DORMANT (RP23XX_XOSC_BASE + RP23XX_XOSC_DORMANT_OFFSET)
#define RP23XX_XOSC_STARTUP (RP23XX_XOSC_BASE + RP23XX_XOSC_STARTUP_OFFSET)
#define RP23XX_XOSC_COUNT (RP23XX_XOSC_BASE + RP23XX_XOSC_COUNT_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_XOSC_CTRL_ENABLE_SHIFT (12) /* On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */
#define RP23XX_XOSC_CTRL_ENABLE_MASK (0xfff << RP23XX_XOSC_CTRL_ENABLE_SHIFT)
#define RP23XX_XOSC_CTRL_ENABLE_DISABLE (0xd1e << RP23XX_XOSC_CTRL_ENABLE_SHIFT)
#define RP23XX_XOSC_CTRL_ENABLE_ENABLE (0xfab << RP23XX_XOSC_CTRL_ENABLE_SHIFT)
#define RP23XX_XOSC_CTRL_FREQ_RANGE_MASK (0xfff)
#define RP23XX_XOSC_CTRL_FREQ_RANGE_1_15MHZ (0xaa0)
#define RP23XX_XOSC_CTRL_FREQ_RANGE_10_30MHZ (0xaa1)
#define RP23XX_XOSC_CTRL_FREQ_RANGE_25_60MHZ (0xaa2)
#define RP23XX_XOSC_CTRL_FREQ_RANGE_40_100MHZ (0xaa3)
#define RP23XX_XOSC_STATUS_STABLE (1 << 31) /* Oscillator is running and stable */
#define RP23XX_XOSC_STATUS_BADWRITE (1 << 24) /* An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT */
#define RP23XX_XOSC_STATUS_ENABLED (1 << 12) /* Oscillator is enabled but not necessarily running and stable, resets to 0 */
#define RP23XX_XOSC_STATUS_FREQ_RANGE_MASK (0x03)
#define RP23XX_XOSC_STATUS_FREQ_RANGE_1_15MHZ (0x0)
#define RP23XX_XOSC_STATUS_FREQ_RANGE_10_30MHZ (0x1)
#define RP23XX_XOSC_STATUS_FREQ_RANGE_25_60MHZ (0x2)
#define RP23XX_XOSC_STATUS_FREQ_RANGE_40_100MHZ (0x3)
#define RP23XX_XOSC_DORMANT_DORMANT (0x636f6d61)
#define RP23XX_XOSC_DORMANT_WAKE (0x77616b65)
#define RP23XX_XOSC_STARTUP_X4 (1 << 20) /* Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly */
#define RP23XX_XOSC_STARTUP_DELAY_MASK (0x3fff) /* in multiples of 256*xtal_period */
#define RP23XX_XOSC_COUNT_MASK (0xffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_XOSC_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_adc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Notes:
* The ADC driver upper-half returns signed values of up to 32-bits to
* the user and expects the high-order bits in any result to be
* significant. So, while the RP23XX hardware returns an unsigned value
* in the low-order 12 bits of the result register, we shift this
* value to the high-order bits.
*
* The result is that to convert a 32-bit value returned from the ADC
* driver, you should use V = ADC_AVDD * value / (2^31) where ADC_AVDD
* is the analogue reference voltage supplied to the RP23XX chip. If
* 8 or 16 bit values are returned the divisor would be (2^15) or (2^7)
* respectively.
*
* Also, if the conversion error bit was set for a particular sample,
* the return value will be negated. Any negative return value should
* be treated as erroneous.
*
* -------------
*
* This lower-half supports multiple drivers (/dev/adc0, /dav/dca1, etc.)
* that each may read data from any of the ADC ports. The driver reads
* whichever ADC ports are needed by ANY of the drivers in strict
* round-robin fashion, passing the converted values to the drivers that
* needed it. Data is only passed if the driver is open.
*
* --------------
*
* This code reads the ADC ports at full speed. At the time this comment
* was written, the upper-half will throw away any converted values it
* receives when the buffer is full; therefore, if the data is not read
* for a while, the returned values may be stale when finally read. You
* can use the ANIOC_RESET_FIFO ioctl call to flush this stale data.
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <rp23xx_adc.h>
#include <stdlib.h>
#include <fcntl.h>
#include <string.h>
#include <errno.h>
#include <nuttx/analog/adc.h>
#include <nuttx/kmalloc.h>
#include <rp23xx_gpio.h>
#include "riscv_internal.h"
#include "hardware/rp23xx_adc.h"
#ifdef CONFIG_RP23XX_RV_ADC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_RP2350B
#define ADC_CHANNEL_COUNT 9
#define ADC_TEMP_CHANNEL 8
#else
#define ADC_CHANNEL_COUNT 5
#define ADC_TEMP_CHANNEL 4
#endif
/* Get the private data pointer from a device pointer */
#define PRIV(x) ((struct private_s *)(x)->ad_priv)
/****************************************************************************
* Private Types
****************************************************************************/
struct private_s
{
const struct adc_callback_s *callback; /* ADC Callback Structure */
struct adc_dev_s *next_device;
struct adc_dev_s *prior_device;
bool has_channel[ADC_CHANNEL_COUNT];
};
/****************************************************************************
* Private Functions
****************************************************************************/
static int interrupt_handler(int irq,
void *context,
void *arg);
static void get_next_channel(void);
static void add_device(struct adc_dev_s *dev);
static void remove_device(struct adc_dev_s *dev);
/* ADC methods */
static int my_bind(struct adc_dev_s *dev,
const struct adc_callback_s *callback);
static void my_reset(struct adc_dev_s *dev);
static int my_setup(struct adc_dev_s *dev);
static void my_shutdown(struct adc_dev_s *dev);
static void my_rxint(struct adc_dev_s *dev, bool enable);
static int my_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct adc_ops_s g_adcops =
{
.ao_bind = my_bind, /* Called first during initialization. */
.ao_reset = my_reset, /* Called second during initialization. */
.ao_setup = my_setup, /* Called during first open. */
.ao_shutdown = my_shutdown, /* Called during last close. */
.ao_rxint = my_rxint, /* Called to enable/disable interrupts. */
.ao_ioctl = my_ioctl, /* Called for custom ioctls. */
};
static const int8_t g_gpio_map[ADC_CHANNEL_COUNT] =
{
26, 27, 28, 29, -1
};
static struct adc_dev_s *g_first_device = NULL;
static uint8_t g_current_channel = 0xf0; /* too big */
static uint8_t g_active_count = 0;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: interrupt_handler
*
* Description:
* ADC interrupt handler. Note that this one handler is shared between
* all ADC devices.
*
* Note: This is called from inside an interrupt service routine.
****************************************************************************/
static int interrupt_handler(int irq, void *context, void *arg)
{
struct adc_dev_s *a_device;
const struct adc_callback_s *a_callback;
int32_t value;
bool error_bit_set;
if (g_active_count == 0)
{
/* Last device has been removed -- turn off ADC */
putreg32(0, RP23XX_RV_ADC_CS);
putreg32(0, RP23XX_RV_ADC_INTE);
up_disable_irq(RP23XX_RV_ADC_IRQ_FIFO);
irq_detach(RP23XX_RV_ADC_IRQ_FIFO);
/* Flush the FIFO */
while (getreg32(RP23XX_RV_ADC_FCS) & RP23XX_RV_ADC_FCS_LEVEL_MASK)
{
getreg32(RP23XX_RV_ADC_FIFO);
}
return OK;
}
/* Fetch the data from the FIFO register */
value = getreg32(RP23XX_RV_ADC_FIFO);
error_bit_set = (value & RP23XX_RV_ADC_FIFO_ERR) != 0;
/* Shift value to top of signed 32-bit word for upper-halfs benefit. */
value <<= 19;
if (error_bit_set)
{
value = -value;
}
for (a_device = g_first_device;
a_device != NULL;
a_device = PRIV(a_device)->next_device)
{
a_callback = PRIV(a_device)->callback;
if (a_callback != NULL && a_callback->au_receive != NULL)
{
if (PRIV(a_device)->has_channel[g_current_channel])
{
if (a_callback->au_receive(a_device,
g_current_channel,
value) != OK)
{
/* ### TODO ### Upper half buffer overflow */
}
}
}
}
/* Start next channel read */
get_next_channel();
return OK;
}
/****************************************************************************
* Name: get_next_channel
*
* Description:
* Update g_current_channel to point to next channel in use and start
* the conversion.
*
* Note: This is called from inside a critical section.
****************************************************************************/
static void get_next_channel(void)
{
struct adc_dev_s *a_device;
uint8_t next = g_current_channel + 1;
uint32_t value;
while (true)
{
if (next >= ADC_CHANNEL_COUNT)
{
next = 0;
}
for (a_device = g_first_device;
a_device != NULL;
a_device = PRIV(a_device)->next_device)
{
if (PRIV(a_device)->has_channel[next])
{
g_current_channel = next;
while (getreg32(RP23XX_RV_ADC_FCS)
& RP23XX_RV_ADC_FCS_LEVEL_MASK)
{
getreg32(RP23XX_RV_ADC_FIFO);
}
/* Enable Interrupt on ADC Completion */
putreg32(RP23XX_RV_ADC_INTE_FIFO, RP23XX_RV_ADC_INTE);
/* Configure CS to read one value from current channel */
value = (g_current_channel << RP23XX_RV_ADC_CS_AINSEL_SHIFT)
| RP23XX_RV_ADC_CS_EN;
if (g_current_channel == ADC_TEMP_CHANNEL)
{
value |= RP23XX_RV_ADC_CS_TS_EN;
}
putreg32(value, RP23XX_RV_ADC_CS);
while ((getreg32(RP23XX_RV_ADC_CS)
& RP23XX_RV_ADC_CS_READY) == 0)
{
/* Wait for ready to go high. The rp23xx docs
* say this is only a few clock cycles so we'll
* just busy wait.
*/
}
/* Start the conversion */
value += RP23XX_RV_ADC_CS_START_ONCE;
putreg32(value, RP23XX_RV_ADC_CS);
return;
}
}
/* if we've looped all the way we're in trouble */
ASSERT(next != g_current_channel);
/* try another */
next += 1;
}
}
/****************************************************************************
* Name: add_device
*
* Description:
* This function is called to link the device int the device list.
* It also makes sure ADC reads are taking place
*
* Note: This is called from inside a critical section.
****************************************************************************/
static void add_device(struct adc_dev_s *dev)
{
uint32_t value;
g_active_count += 1;
if (g_first_device != NULL)
{
PRIV(g_first_device)->prior_device = dev;
}
PRIV(dev)->next_device = g_first_device;
PRIV(dev)->prior_device = NULL;
g_first_device = dev;
if (PRIV(g_first_device)->next_device == NULL)
{
/* We just added first device */
/* Make sure ADC interrupts are disabled */
putreg32(0, RP23XX_RV_ADC_INTE);
/* Configure FCS to use FIFO and interrupt on first value */
value = (1 << RP23XX_RV_ADC_FCS_THRESH_SHIFT)
| RP23XX_RV_ADC_FCS_OVER
| RP23XX_RV_ADC_FCS_UNDER
| RP23XX_RV_ADC_FCS_ERR
| RP23XX_RV_ADC_FCS_EN;
putreg32(value, RP23XX_RV_ADC_FCS);
/* Set up for interrupts */
irq_attach(RP23XX_RV_ADC_IRQ_FIFO, interrupt_handler, NULL);
up_enable_irq(RP23XX_RV_ADC_IRQ_FIFO);
/* Start conversions on first required channel. */
get_next_channel();
ainfo("new cur %d\n", g_current_channel);
}
}
/****************************************************************************
* Name: remove_device
*
* Description:
* This function is called to unlink the device from the device list.
*
* Note: This is called from inside a critical section.
****************************************************************************/
void remove_device(struct adc_dev_s *dev)
{
struct adc_dev_s *a_device;
if (dev == g_first_device)
{
/* Special handling for first device */
g_first_device = PRIV(g_first_device)->next_device;
if (g_first_device != NULL)
{
PRIV(g_first_device)->prior_device = NULL;
}
g_active_count -= 1;
}
else
{
/* Make sure dev is on the change, and unlink if it is. */
for (a_device = g_first_device;
a_device != NULL;
a_device = PRIV(a_device)->next_device)
{
if (a_device == dev)
{
PRIV(PRIV(dev)->prior_device)->next_device =
PRIV(dev)->next_device;
PRIV(PRIV(dev)->next_device)->prior_device =
PRIV(dev)->prior_device;
g_active_count -= 1;
break;
}
}
}
}
/****************************************************************************
* Name: my_bind
*
* Description:
* This function is called when a driver is registered. It give us a
* chance to bind the upper-half callbacks to our private data structure so
* they can be accessed later.
*
****************************************************************************/
static int my_bind(struct adc_dev_s *dev,
const struct adc_callback_s *callback)
{
DEBUGASSERT(PRIV(dev) != NULL);
ainfo("entered\n");
PRIV(dev)->callback = callback;
return OK;
}
/****************************************************************************
* Name: my_reset
*
* Description:
* This is called by the upper-half as part of the driver registration
* process. The upper half documentation also claims that it may
* be called as part of an error condition.
*
* Set the pin for the ADC's to standard GPIO input with no pulls.
*
****************************************************************************/
static void my_reset(struct adc_dev_s *dev)
{
int a_gpio;
ainfo("entered\n");
for (int i = 0; i < ADC_CHANNEL_COUNT; ++i)
{
a_gpio = g_gpio_map[i];
if (a_gpio >= 0)
{
rp23xx_gpio_setdir(a_gpio, false);
rp23xx_gpio_set_function(a_gpio, GPIO_FUNC_NULL);
rp23xx_gpio_set_pulls(a_gpio, false, false);
}
}
}
/****************************************************************************
* Name: my_setup
*
* Description:
* This is called when a particular ADC driver is first opened.
*
* We don't do anything here.
*
* Note: This is called from inside a critical section.
****************************************************************************/
static int my_setup(struct adc_dev_s *dev)
{
int ret;
ainfo("entered: %p\n", dev);
/* Note: We check g_active_count here so we can return an error
* in the, probably impossible, case we have too many.
*/
if (g_active_count >= 200)
{
aerr("Too many active devices.");
ret = -EBUSY;
}
else
{
ret = OK;
}
return ret;
}
/****************************************************************************
* Name: my_shutdown
*
* Description:
* This is called to shutdown an ADC device. It unlinks the
* device from out local chain and turns off ADC interrupts if no
* more devices are active.
*
* Note: This is called from inside a critical section.
****************************************************************************/
static void my_shutdown(struct adc_dev_s *dev)
{
ainfo("entered: %p\n", dev);
/* Remove adc_dev_s structure from the list */
remove_device(dev);
}
/****************************************************************************
* Name: my_rxint
*
* Description:
* Call to enable or disable ADC RX interrupts
*
* Note: This is called from inside a critical section.
****************************************************************************/
static void my_rxint(struct adc_dev_s *dev, bool enable)
{
if (enable)
{
ainfo("entered: enable: %p\n", dev);
add_device(dev);
}
else
{
ainfo("entered: disable: %p\n", dev);
remove_device(dev);
}
}
/****************************************************************************
* Name: my_ioctl
*
* Description:
* All ioctl calls will be routed through this method
*
****************************************************************************/
static int my_ioctl(struct adc_dev_s *dev,
int cmd,
unsigned long arg)
{
/* No ioctl commands supported */
ainfo("entered\n");
return -ENOTTY;
}
/****************************************************************************
* Public Function
****************************************************************************/
#ifdef CONFIG_ADC
/****************************************************************************
* Name: my_setup
*
* Description:
* Initialize and register the ADC driver.
*
* Input Parameters:
* path - Path to the adc device (e.g. "/dev/adc0")
* read_adc0 - This device reads ADC0
* read_adc1 - This device reads ADC1
* read_adc2 - This device reads ADC3
* read_adc3 - This device reads ADC4
* read_temp - This device reads the chip temperature.
*
* Returned Value:
* An opaque pointer that can be passed to rp23xx_adc_release on
* success or NULL (with errno set) on failure
****************************************************************************/
int rp23xx_adc_setup(const char *path,
bool read_adc0,
bool read_adc1,
bool read_adc2,
bool read_adc3,
bool read_temp)
{
struct adc_dev_s *dev;
struct private_s *priv;
int ret;
ainfo("entered\n");
if (!read_adc0 && !read_adc1 && !read_adc2 && !read_adc3 && !read_temp)
{
aerr("No ADC inputs selected.\n");
return -EINVAL;
}
dev = kmm_zalloc(sizeof(struct adc_dev_s));
if (dev == NULL)
{
aerr("Failed to allocate adc_dev_s.\n");
return -ENOMEM;
}
priv = kmm_zalloc(sizeof(struct private_s));
if (priv == NULL)
{
aerr("Failed to allocate private_s.\n");
kmm_free(dev);
return -ENOMEM;
}
priv->has_channel[0] = read_adc0;
priv->has_channel[1] = read_adc1;
priv->has_channel[2] = read_adc2;
priv->has_channel[3] = read_adc3;
priv->has_channel[4] = read_temp;
dev->ad_ops = &g_adcops;
dev->ad_priv = priv;
ret = adc_register(path, dev);
return ret;
}
#endif /* if CONFIG_ADC */
#endif /* if CONFIG_RP23XX_RV_ADC */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_adc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Note:
* The ADC driver upper-half returns signed values of up to 32-bits to
* the user and expects the high-order bits in any result to be
* significant. So, while the RP23XX hardware returns an unsigned value
* in the low-order 12 bits of the result register, we shift this
* value to the high-order bits.
*
* The result is that to convert a 32-bit value returned from the ADC
* driver, you should use V = ADC_AVDD * value / (2^31) where ADC_AVDD
* is the analogue reference voltage supplied to the RP23XX chip. If
* 8 or 16 bit values are returned the divisor would be (2^15) or (2^7)
* respectively.
*
* Also, if the conversion error bit was set for a particular sample,
* the return value will be negated. Any negative return value should
* be treated as erroneous.
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_ADC_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <stdbool.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_RP23XX_RV_ADC
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_ADC
/****************************************************************************
* Name: rp23xx_adc_setup
*
* Description:
* Initialize and register the ADC driver.
*
* Input Parameters:
* path - Path to the adc device (e.g. "/dev/adc0")
* read_adc0 - This device reads ADC0
* read_adc1 - This device reads ADC1
* read_adc2 - This device reads ADC3
* read_adc3 - This device reads ADC4
* read_temp - This device reads the chip temperature.
*
* Returned Value:
* OK on success or an ERROR on failure
****************************************************************************/
int rp23xx_adc_setup(const char *path,
bool read_adc0,
bool read_adc1,
bool read_adc2,
bool read_adc3,
bool read_temp);
#else /* CONFIG_ADC */
/* ### TODO ### Add programmatic access function. */
#endif /* CONFIG_ADC */
#endif /* CONFIG_RP23XX_RV_ADC */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_ADC_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_clock.c
*
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-FileCopyrightText: 2020 Raspberry Pi (Trading) Ltd.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "riscv_internal.h"
#include "chip.h"
#include "rp23xx_clock.h"
#include "rp23xx_xosc.h"
#include "rp23xx_pll.h"
#include "hardware/rp23xx_clocks.h"
#include "hardware/rp23xx_resets.h"
#include "hardware/rp23xx_ticks.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static uint32_t rp23xx_clock_freq[RP23XX_CLOCKS_NDX_MAX];
/****************************************************************************
* Private Functions
****************************************************************************/
static void tick_start(int tick, int cycles)
{
putreg32(cycles, RP23XX_TICKS_CYCLES(tick));
putreg32(RP23XX_TICKS_WATCHDOG_CTRL_EN, RP23XX_TICKS_CTRL(tick));
}
static inline bool has_glitchless_mux(int clk_index)
{
return clk_index == RP23XX_CLOCKS_NDX_SYS ||
clk_index == RP23XX_CLOCKS_NDX_REF;
}
#if defined(CONFIG_RP23XX_CLK_GPOUT_ENABLE)
static bool rp23xx_clock_configure_gpout(int clk_index,
uint32_t src,
uint32_t div_int,
uint32_t div_frac)
{
if (clk_index > RP23XX_CLOCKS_NDX_GPOUT3 ||
clk_index < RP23XX_CLOCKS_NDX_GPOUT0 ||
(src >> RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) > 0xa)
{
return false;
}
putreg32((div_int << RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT) |
(div_frac & RP23XX_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK),
(RP23XX_CLOCKS_CLK_NDX_DIV(clk_index)));
putreg32((src << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) |
RP23XX_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
(RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index)));
return true;
}
#endif
bool rp23xx_clock_configure(int clk_index,
uint32_t src, uint32_t auxsrc,
uint32_t src_freq, uint32_t freq)
{
uint32_t div;
ASSERT(src_freq >= freq);
if (freq > src_freq)
{
return false;
}
/* Div register is 16.16 int.frac divider so multiply by 2^16
* (left shift by 16)
*/
div = (uint32_t) (((uint64_t) src_freq << 16) / freq);
/* If increasing divisor, set divisor before source. Otherwise set source
* before divisor. This avoids a momentary overspeed when e.g. switching
* to a faster source and increasing divisor to compensate.
*/
if (div > getreg32(RP23XX_CLOCKS_CLK_NDX_DIV(clk_index)))
{
putreg32(div, RP23XX_CLOCKS_CLK_NDX_DIV(clk_index));
}
if (has_glitchless_mux(clk_index) &&
src == RP23XX_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX)
{
/* If switching a glitchless slice (ref or sys) to an aux source,
* switch away from aux *first* to avoid passing glitches when
* changing aux mux.
* Assume (!!!) glitchless source 0 is no faster than the aux source.
*/
clrbits_reg32(RP23XX_CLOCKS_CLK_REF_CTRL_SRC_MASK,
RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index));
while (!(getreg32(RP23XX_CLOCKS_CLK_NDX_SELECTED(clk_index)) & 1u))
;
}
else
{
/* If no glitchless mux, cleanly stop the clock to avoid glitches
* propagating when changing aux mux. Note it would be a really bad
* idea to do this on one of the glitchless clocks (clk_sys, clk_ref).
*/
clrbits_reg32(RP23XX_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index));
if (rp23xx_clock_freq[clk_index] > 0)
{
/* Delay for 3 cycles of the target clock, for ENABLE propagation.
* Note XOSC_COUNT is not helpful here because XOSC is not
* necessarily running, nor is timer... so, 3 cycles per loop:
*/
volatile unsigned int delay_cyc;
delay_cyc = rp23xx_clock_freq[RP23XX_CLOCKS_NDX_SYS] /
rp23xx_clock_freq[clk_index] + 1;
while (--delay_cyc > 0);
}
}
/* Set aux mux first, and then glitchless mux if this clock has one */
modbits_reg32(auxsrc, RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_MASK,
RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index));
if (has_glitchless_mux(clk_index))
{
modbits_reg32(src, RP23XX_CLOCKS_CLK_REF_CTRL_SRC_MASK,
RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index));
while (!(getreg32(RP23XX_CLOCKS_CLK_NDX_SELECTED(clk_index))
& (1u << src)))
;
}
setbits_reg32(RP23XX_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
RP23XX_CLOCKS_CLK_NDX_CTRL(clk_index));
/* Now that the source is configured, we can trust that the user-supplied
* divisor is a safe value.
*/
putreg32(div, RP23XX_CLOCKS_CLK_NDX_DIV(clk_index));
/* Store the configured frequency */
rp23xx_clock_freq[clk_index] = freq;
return true;
}
void clocks_init(void)
{
/* Disable resus that may be enabled from previous software */
putreg32(0, RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL);
/* Enable the xosc */
rp23xx_xosc_init();
/* Before we touch PLLs, switch sys and ref cleanly away from their
* aux sources.
*/
clrbits_reg32(RP23XX_CLOCKS_CLK_SYS_CTRL_SRC,
RP23XX_CLOCKS_CLK_SYS_CTRL);
while (getreg32(RP23XX_CLOCKS_CLK_SYS_SELECTED) != 1)
;
clrbits_reg32(RP23XX_CLOCKS_CLK_REF_CTRL_SRC_MASK,
RP23XX_CLOCKS_CLK_REF_CTRL);
while (getreg32(RP23XX_CLOCKS_CLK_REF_SELECTED) != 1)
;
/* Configure PLLs
* REF FBDIV VCO POSTDIV
* PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 5 / 2 = 150MHz
* PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
*/
setbits_reg32(RP23XX_RESETS_RESET_PLL_SYS | RP23XX_RESETS_RESET_PLL_USB,
RP23XX_RESETS_RESET);
clrbits_reg32(RP23XX_RESETS_RESET_PLL_SYS | RP23XX_RESETS_RESET_PLL_USB,
RP23XX_RESETS_RESET);
while (~getreg32(RP23XX_RESETS_RESET_DONE) &
(RP23XX_RESETS_RESET_PLL_SYS | RP23XX_RESETS_RESET_PLL_USB))
;
rp23xx_pll_init(RP23XX_PLL_SYS_BASE, 1, 1500 * MHZ, 5, 2);
rp23xx_pll_init(RP23XX_PLL_USB_BASE, 1, 1200 * MHZ, 5, 5);
/* Configure clocks */
/* CLK_REF = XOSC (12MHz) / 1 = 12MHz */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_REF,
RP23XX_CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC,
0,
BOARD_XOSC_FREQ,
BOARD_REF_FREQ);
/* CLK SYS = PLL SYS (150MHz) / 1 = 150MHz */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_SYS,
RP23XX_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,
RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS,
BOARD_PLL_SYS_FREQ,
BOARD_SYS_FREQ);
/* CLK USB = PLL USB (48MHz) / 1 = 48MHz */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_USB,
0,
RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB,
BOARD_PLL_USB_FREQ,
BOARD_USB_FREQ);
/* CLK ADC = PLL USB (48MHZ) / 1 = 48MHz */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_ADC,
0,
RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB,
BOARD_PLL_USB_FREQ,
BOARD_ADC_FREQ);
/* CLK PERI = clk_sys. */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_PERI,
0,
RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS,
BOARD_SYS_FREQ,
BOARD_PERI_FREQ);
/* CLK HSTX = clk_sys */
rp23xx_clock_configure(RP23XX_CLOCKS_NDX_HSTX,
0,
RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLK_SYS,
BOARD_SYS_FREQ,
BOARD_HSTX_FREQ);
#if defined(CONFIG_RP23XX_CLK_GPOUT_ENABLE)
uint32_t src;
#if defined(CONFIG_RP23XX_CLK_GPOUT0)
#if defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_REF)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF;
#elif defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_SYS)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS;
#elif defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_USB)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB;
#elif defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_ADC)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC;
#elif defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_PERI)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_PERI;
#elif defined(CONFIG_RP23XX_CLK_GPOUT0_SRC_HSTX)
src = RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_HSTX;
#else
src = 0;
#endif
rp23xx_clock_configure_gpout(RP23XX_CLOCKS_NDX_GPOUT0,
src,
CONFIG_RP23XX_CLK_GPOUT0_DIVINT,
CONFIG_RP23XX_CLK_GPOUT0_DIVFRAC);
#endif
#if defined(CONFIG_RP23XX_CLK_GPOUT1)
#if defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_REF)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF;
#elif defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_SYS)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS;
#elif defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_USB)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB;
#elif defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_ADC)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC;
#elif defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_PERI)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_PERI;
#elif defined(CONFIG_RP23XX_CLK_GPOUT1_SRC_HSTX)
src = RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_HSTX;
#else
src = 0;
#endif
rp23xx_clock_configure_gpout(RP23XX_CLOCKS_NDX_GPOUT1,
src,
CONFIG_RP23XX_CLK_GPOUT1_DIVINT,
CONFIG_RP23XX_CLK_GPOUT1_DIVFRAC);
#endif
#if defined(CONFIG_RP23XX_CLK_GPOUT2)
#if defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_REF)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF;
#elif defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_SYS)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS;
#elif defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_USB)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB;
#elif defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_ADC)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC;
#elif defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_PERI)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_PERI;
#elif defined(CONFIG_RP23XX_CLK_GPOUT2_SRC_HSTX)
src = RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_HSTX;
#else
src = 0;
#endif
rp23xx_clock_configure_gpout(RP23XX_CLOCKS_NDX_GPOUT2,
src,
CONFIG_RP23XX_CLK_GPOUT2_DIVINT,
CONFIG_RP23XX_CLK_GPOUT2_DIVFRAC);
#endif
#if defined(CONFIG_RP23XX_CLK_GPOUT3)
#if defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_REF)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF;
#elif defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_SYS)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS;
#elif defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_USB)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB;
#elif defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_ADC)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC;
#elif defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_RTC)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_RTC;
#elif defined(CONFIG_RP23XX_CLK_GPOUT3_SRC_PERI)
src = RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_PERI;
#else
src = 0;
#endif
rp23xx_clock_configure_gpout(RP23XX_CLOCKS_NDX_GPOUT3,
src,
CONFIG_RP23XX_CLK_GPOUT3_DIVINT,
CONFIG_RP23XX_CLK_GPOUT3_DIVFRAC);
#endif
#endif
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void rp23xx_clockconfig(void)
{
/* Reset all peripherals to put system into a known state,
* - except for QSPI pads and the XIP IO bank, as this is fatal if running
* from flash
* - and the PLLs, as this is fatal if clock muxing has not been reset on
* this boot
* - and USB, syscfg, as this disturbs USB-to-SWD on core 1
*/
setbits_reg32(RP23XX_RESETS_RESET_MASK & ~(RP23XX_RESETS_RESET_IO_QSPI |
RP23XX_RESETS_RESET_PADS_QSPI |
RP23XX_RESETS_RESET_PLL_USB |
RP23XX_RESETS_RESET_USBCTRL |
RP23XX_RESETS_RESET_SYSCFG |
RP23XX_RESETS_RESET_JTAG |
RP23XX_RESETS_RESET_PLL_SYS),
RP23XX_RESETS_RESET);
/* Remove reset from peripherals which are clocked only by clk_sys and
* clk_ref. Other peripherals stay in reset until we've configured clocks.
*/
clrbits_reg32(RP23XX_RESETS_RESET_MASK & ~(RP23XX_RESETS_RESET_ADC |
RP23XX_RESETS_RESET_HSTX |
RP23XX_RESETS_RESET_SPI0 |
RP23XX_RESETS_RESET_SPI1 |
RP23XX_RESETS_RESET_UART0 |
RP23XX_RESETS_RESET_UART1 |
RP23XX_RESETS_RESET_USBCTRL),
RP23XX_RESETS_RESET);
while (~getreg32(RP23XX_RESETS_RESET_DONE) &
(RP23XX_RESETS_RESET_MASK & ~(RP23XX_RESETS_RESET_ADC |
RP23XX_RESETS_RESET_HSTX |
RP23XX_RESETS_RESET_SPI0 |
RP23XX_RESETS_RESET_SPI1 |
RP23XX_RESETS_RESET_UART0 |
RP23XX_RESETS_RESET_UART1 |
RP23XX_RESETS_RESET_USBCTRL)))
;
/* After calling preinit we have enough runtime to do the exciting maths
* in clocks_init
*/
clocks_init();
/* Configure all TICK blocks */
for (int i = 0; i < (int)RP23XX_TICK_NUM; ++i)
{
tick_start(i, (BOARD_REF_FREQ / MHZ));
}
/* Peripheral clocks should now all be running */
clrbits_reg32(RP23XX_RESETS_RESET_MASK, RP23XX_RESETS_RESET);
while (~getreg32(RP23XX_RESETS_RESET_DONE) & RP23XX_RESETS_RESET_MASK)
;
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_clock.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_CLOCK_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_CLOCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_TICK_NUM 6 /* Number of TICK blocks */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void rp23xx_clockconfig(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_CLOCK_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_config.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_CONFIG_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Required configuration settings */
/* Are any UARTs enabled? */
#undef HAVE_UART
#if defined(CONFIG_RP23XX_RV_UART0) || defined(CONFIG_RP23XX_RV_UART1)
# define HAVE_UART 1
#endif
/* Make sure all features are disabled for disabled U[S]ARTs.
* This simplifies checking later.
*/
#ifndef CONFIG_RP23XX_RV_UART0
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART0_RS485MODE
# undef CONFIG_UART0_RS485_DTRDIR
#endif
#ifndef CONFIG_RP23XX_RV_UART1
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART1_RS485MODE
# undef CONFIG_UART1_RS485_DTRDIR
#endif
/* Is there a serial console? There should be at most one defined. It could
* be on any UARTn, n=0,1,2,3 - OR - there might not be any serial console at
* all.
*/
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
# define HAVE_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
# undef HAVE_CONSOLE
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_CONFIG_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include "riscv_internal.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_cpu_idlestack
*
* Description:
* Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
* setup up stack-related information in the IDLE task's TCB. This
* function is always called before up_cpu_start(). This function is
* only called for the CPU's initial IDLE task; up_create_task is used for
* all normal tasks, pthreads, and kernel threads for all CPUs.
*
* The initial IDLE task is a special case because the CPUs can be started
* in different wans in different environments:
*
* 1. The CPU may already have been started and waiting in a low power
* state for up_cpu_start(). In this case, the IDLE thread's stack
* has already been allocated and is already in use. Here
* up_cpu_idlestack() only has to provide information about the
* already allocated stack.
*
* 2. The CPU may be disabled but started when up_cpu_start() is called.
* In this case, a new stack will need to be created for the IDLE
* thread and this function is then equivalent to:
*
* return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
*
* The following TCB fields must be initialized by this function:
*
* - adj_stack_size: Stack size after adjustment for hardware, processor,
* etc. This value is retained only for debug purposes.
* - stack_alloc_ptr: Pointer to allocated stack
* - stack_base_ptr: Adjusted stack base pointer after the TLS Data and
* Arguments has been removed from the stack allocation.
*
* Input Parameters:
* - cpu: CPU index that indicates which CPU the IDLE task is
* being created for.
* - tcb: The TCB of new CPU IDLE task
* - stack_size: The requested stack size for the IDLE task. At least
* this much must be allocated. This should be
* CONFIG_SMP_STACK_SIZE.
*
****************************************************************************/
int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
#endif
return OK;
}
#endif /* CONFIG_SMP */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <string.h>
#include <stdio.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/sched_note.h>
#include "nvic.h"
#include "sched/sched.h"
#include "init/init.h"
#include "riscv_internal.h"
#include "hardware/rp23xx_memorymap.h"
#include "hardware/rp23xx_sio.h"
#include "hardware/rp23xx_psm.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if 0
# define DPRINTF(fmt, args...) _err(fmt, ##args)
#else
# define DPRINTF(fmt, args...) do {} while (0)
#endif
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) riscv_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
static volatile bool g_core1_boot;
extern int rp23xx_smp_call_handler(int irq, void *c, void *arg);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: fifo_drain
*
* Description:
* Drain all data in the inter-processor FIFO
****************************************************************************/
static void fifo_drain(void)
{
putreg32(0, RP23XX_SIO_FIFO_ST);
while (getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_VLD)
{
getreg32(RP23XX_SIO_FIFO_RD);
}
__asm__ volatile ("sev");
}
/****************************************************************************
* Name: fifo_comm
*
* Description:
* Communicate with CPU Core 1 using inter-processor FIFO for boot
*
* Input Parameters:
* msg - Data to be sent to Core 1
*
* Returned Value:
* true on success; false on failure.
*
****************************************************************************/
static int fifo_comm(uint32_t msg)
{
uint32_t rcv;
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
;
putreg32(msg, RP23XX_SIO_FIFO_WR);
__asm__ volatile ("sev");
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_VLD))
__asm__ volatile ("wfe");
rcv = getreg32(RP23XX_SIO_FIFO_RD);
return msg == rcv;
}
/****************************************************************************
* Name: core1_boot
*
* Description:
* This is the boot vector for Core #1
*
* Input Parameters:
*
* Returned Value:
*
****************************************************************************/
static void core1_boot(void)
{
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Initializes the stack pointer */
riscv_initialize_stack();
#endif
fifo_drain();
/* Setup NVIC */
up_irqinitialize();
/* Enable inter-processor FIFO interrupt */
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
g_core1_boot = true;
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify that this CPU has started */
sched_note_cpu_started(this_task());
#endif
/* Then transfer control to the IDLE task */
nx_idle_trampoline();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_cpu_start
*
* Description:
* In an SMP configuration, only one CPU is initially active (CPU 0).
* System initialization occurs on that single thread. At the completion of
* the initialization of the OS, just before beginning normal multitasking,
* the additional CPUs would be started by calling this function.
*
* Each CPU is provided the entry point to its IDLE task when started. A
* TCB for each CPU's IDLE task has been initialized and placed in the
* CPU's g_assignedtasks[cpu] list. No stack has been allocated or
* initialized.
*
* The OS initialization logic calls this function repeatedly until each
* CPU has been started, 1 through (CONFIG_SMP_NCPUS-1).
*
* Input Parameters:
* cpu - The index of the CPU being started. This will be a numeric
* value in the range of one to (CONFIG_SMP_NCPUS-1).
* (CPU 0 is already active)
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
int up_cpu_start(int cpu)
{
int i;
struct tcb_s *tcb = current_task(cpu);
uint32_t core1_boot_msg[5];
DPRINTF("cpu=%d\n", cpu);
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the start event */
sched_note_cpu_start(this_task(), cpu);
#endif
/* Reset Core 1 */
setbits_reg32(RP23XX_PSM_PROC1, RP23XX_PSM_FRCE_OFF);
while (!(getreg32(RP23XX_PSM_FRCE_OFF) & RP23XX_PSM_PROC1))
;
clrbits_reg32(RP23XX_PSM_PROC1, RP23XX_PSM_FRCE_OFF);
/* Send initial VTOR, MSP, PC for Core 1 boot */
core1_boot_msg[0] = 0;
core1_boot_msg[1] = 1;
core1_boot_msg[2] = getreg32(NVIC_VECTAB);
core1_boot_msg[3] = (uint32_t)tcb->stack_base_ptr +
tcb->adj_stack_size;
core1_boot_msg[4] = (uint32_t)core1_boot;
do
{
fifo_drain();
for (i = 0; i < 5; i++)
{
if (!fifo_comm(core1_boot_msg[i]))
{
break;
}
}
}
while (i < 5);
fifo_drain();
/* Enable inter-processor FIFO interrupt */
irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL);
up_enable_irq(RP23XX_SIO_IRQ_FIFO);
while (!g_core1_boot);
/* CPU Core 1 boot done */
return 0;
}
#endif /* CONFIG_SMP */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_dmac.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include "riscv_internal.h"
#include "hardware/rp23xx_dma.h"
#include "rp23xx_dmac.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes one DMA channel */
struct dma_channel_s
{
uint8_t chan; /* DMA channel number (0-RP23XX_DMA_NCHANNELS) */
bool inuse; /* TRUE: The DMA channel is in use */
dma_callback_t callback; /* Callback invoked when the DMA completes */
void *arg; /* Argument passed to callback function */
};
/* This structure describes the state of the DMA controller */
struct dma_controller_s
{
mutex_t lock; /* Protects channel table */
sem_t chansem; /* Count of free channels */
};
/****************************************************************************
* Private Data
****************************************************************************/
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(RP23XX_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
static struct dma_channel_s g_dmach[RP23XX_DMA_NCHANNELS];
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_dmac_interrupt
*
* Description:
* DMA interrupt handler
*
****************************************************************************/
static int rp23xx_dmac_interrupt(int irq, void *context, void *arg)
{
struct dma_channel_s *dmach;
int result = OK;
unsigned int ch;
uint32_t stat;
uint32_t ctrl;
/* Get and clear pending DMA interrupt status */
stat = getreg32(RP23XX_DMA_INTS0) & RP23XX_DMA_INTS0_MASK;
putreg32(stat, RP23XX_DMA_INTS0);
while (stat != 0)
{
ch = ffs(stat) - 1;
stat &= ~(1 << ch);
ctrl = getreg32(RP23XX_DMA_CTRL_TRIG(ch));
if (ctrl & RP23XX_DMA_CTRL_TRIG_AHB_ERROR)
{
setbits_reg32(RP23XX_DMA_CTRL_TRIG_READ_ERROR |
RP23XX_DMA_CTRL_TRIG_WRITE_ERROR,
RP23XX_DMA_CTRL_TRIG(ch));
result = EIO;
}
dmach = &g_dmach[ch];
/* Call the DMA completion callback */
if (dmach->callback)
{
dmach->callback((DMA_HANDLE)dmach, result, dmach->arg);
dmach->callback = NULL;
}
dmach->arg = NULL;
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: riscv_dma_initialize
*
* Description:
* Initialize the DMA subsystem
*
* Returned Value:
* None
*
****************************************************************************/
void weak_function riscv_dma_initialize(void)
{
int i;
dmainfo("Initialize DMAC\n");
/* Initialize the channel list */
for (i = 0; i < RP23XX_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;
putreg32(0, RP23XX_DMA_CTRL_TRIG(i));
}
putreg32(0, RP23XX_DMA_INTE0);
putreg32(RP23XX_DMA_INTS0_MASK, RP23XX_DMA_INTS0);
/* Attach DMA completion interrupt handler */
irq_attach(RP23XX_DMA_IRQ_0, rp23xx_dmac_interrupt, NULL);
up_enable_irq(RP23XX_DMA_IRQ_0);
}
/****************************************************************************
* Name: rp23xx_dmachannel
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually
* exclusive access to a DMA channel.
*
* If no DMA channel is available, then rp23xx_dmachannel() will wait
* until the holder of a channel relinquishes the channel by calling
* rp23xx_dmafree().
*
* Input parameters:
* None
*
* Returned Value:
* This function ALWAYS returns a non-NULL, void* DMA channel handle.
*
* Assumptions:
* - The caller can wait for a DMA channel to be freed if it is not
* available.
*
****************************************************************************/
DMA_HANDLE rp23xx_dmachannel(void)
{
struct dma_channel_s *dmach;
unsigned int ch;
uint32_t bit = 0;
int ret;
/* Take a count from the channel counting semaphore. We may block
* if there are no free channels. When we get the count, then we can
* be assured that a channel is available in the channel list and is
* reserved for us.
*/
ret = nxsem_wait_uninterruptible(&g_dmac.chansem);
if (ret < 0)
{
return NULL;
}
/* Get exclusive access to the DMA channel list */
ret = nxmutex_lock(&g_dmac.lock);
if (ret < 0)
{
nxsem_post(&g_dmac.chansem);
return NULL;
}
/* Search for an available DMA channel */
for (ch = 0, dmach = NULL; ch < RP23XX_DMA_NCHANNELS; ch++)
{
struct dma_channel_s *candidate = &g_dmach[ch];
if (!candidate->inuse)
{
dmach = candidate;
dmach->inuse = true;
bit = 1 << ch;
break;
}
}
nxmutex_unlock(&g_dmac.lock);
setbits_reg32(bit, RP23XX_DMA_INTS0);
setbits_reg32(bit, RP23XX_DMA_INTE0);
/* Since we have reserved a DMA descriptor by taking a count from chansem,
* it would be a serious logic failure if we could not find a free channel
* for our use.
*/
DEBUGASSERT(dmach);
return (DMA_HANDLE)dmach;
}
/****************************************************************************
* Name: rp23xx_dmafree
*
* Description:
* Release a DMA channel. If another thread is waiting for this DMA
* channel in a call to rp23xx_dmachannel, then this function will
* re-assign the DMA channel to that thread and wake it up. NOTE: The
* 'handle' used in this argument must NEVER be used again until
* rp23xx_dmachannel() is called again to re-gain access to the channel.
*
* Returned Value:
* None
*
* Assumptions:
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
****************************************************************************/
void rp23xx_dmafree(DMA_HANDLE handle)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
unsigned int ch;
DEBUGASSERT(dmach != NULL && dmach->inuse);
ch = dmach->chan;
dmainfo("DMA channel %d\n", ch);
/* Disable the channel */
setbits_reg32(1 << dmach->chan, RP23XX_DMA_CHAN_ABORT);
putreg32(0, RP23XX_DMA_CTRL_TRIG(ch));
clrbits_reg32(1 << dmach->chan, RP23XX_DMA_INTE0);
clrbits_reg32(1 << dmach->chan, RP23XX_DMA_INTS0);
/* Mark the channel no longer in use. Clearing the in-use flag is an
* atomic operation and so should be safe.
*/
dmach->inuse = false;
/* And increment the count of free channels... possibly waking up a
* thread that may be waiting for a channel.
*/
nxsem_post(&g_dmac.chansem);
}
/****************************************************************************
* Name: rp23xx_rxdmasetup
*
* Description:
* Configure an RX (peripheral-to-memory) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (source)
* maddr - Memory address (destination)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void rp23xx_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
unsigned int ch;
uint32_t count;
uint32_t mask;
uint32_t ctrl;
DEBUGASSERT(dmach != NULL && dmach->inuse);
ch = dmach->chan;
DEBUGASSERT(config.size >= RP23XX_DMA_SIZE_BYTE &&
config.size <= RP23XX_DMA_SIZE_WORD);
mask = (1 << config.size) - 1;
count = nbytes >> config.size;
DEBUGASSERT(count > 0);
/* Set DMA registers */
putreg32(paddr & ~mask, RP23XX_DMA_READ_ADDR(ch));
putreg32(maddr & ~mask, RP23XX_DMA_WRITE_ADDR(ch));
putreg32(count, RP23XX_DMA_TRANS_COUNT(ch));
ctrl = RP23XX_DMA_CTRL_TRIG_READ_ERROR |
RP23XX_DMA_CTRL_TRIG_WRITE_ERROR |
((config.dreq << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) &
RP23XX_DMA_CTRL_TRIG_TREQ_SEL_MASK) |
((ch << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT) &
RP23XX_DMA_CTRL_TRIG_CHAIN_TO_MASK) |
(config.size << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT);
if (!config.noincr)
{
ctrl |= RP23XX_DMA_CTRL_TRIG_INCR_WRITE;
}
putreg32(ctrl, RP23XX_DMA_CTRL_TRIG(ch));
}
/****************************************************************************
* Name: rp23xx_txdmasetup
*
* Description:
* Configure an TX (memory-to-peripheral) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (destination)
* maddr - Memory address (source)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void rp23xx_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
unsigned int ch;
uint32_t count;
uint32_t mask;
uint32_t ctrl;
DEBUGASSERT(dmach != NULL && dmach->inuse);
ch = dmach->chan;
DEBUGASSERT(config.size >= RP23XX_DMA_SIZE_BYTE &&
config.size <= RP23XX_DMA_SIZE_WORD);
mask = (1 << config.size) - 1;
count = nbytes >> config.size;
DEBUGASSERT(count > 0);
/* Set DMA registers */
putreg32(maddr & ~mask, RP23XX_DMA_READ_ADDR(ch));
putreg32(paddr & ~mask, RP23XX_DMA_WRITE_ADDR(ch));
putreg32(count, RP23XX_DMA_TRANS_COUNT(ch));
ctrl = RP23XX_DMA_CTRL_TRIG_READ_ERROR |
RP23XX_DMA_CTRL_TRIG_WRITE_ERROR |
((config.dreq << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) &
RP23XX_DMA_CTRL_TRIG_TREQ_SEL_MASK) |
((ch << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT) &
RP23XX_DMA_CTRL_TRIG_CHAIN_TO_MASK) |
(config.size << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT);
if (!config.noincr)
{
ctrl |= RP23XX_DMA_CTRL_TRIG_INCR_READ;
}
putreg32(ctrl, RP23XX_DMA_CTRL_TRIG(ch));
}
/****************************************************************************
* Name: rp23xx_ctrl_dmasetup
*
* Description:
* Configure a dma channel to send a list of channel control blocks to
* a second dma channel..
*
* Input Parameters:
* control - the DMA handle that reads the control blocks. This is
* the one that should be started.
* transfer - the DMA handle the transfers data to the peripheral.
* ctrl_blks - the array of control blocks to used. Terminate this
* list with an all zero control block.
* callback - callback when last transfer completes
* arg - arg to pass to callback
*
****************************************************************************/
void rp23xx_ctrl_dmasetup(DMA_HANDLE control,
DMA_HANDLE transfer,
dma_control_block_t *ctrl_blks,
dma_callback_t callback,
void *arg)
{
struct dma_channel_s *ctrl_dmach = (struct dma_channel_s *)control;
struct dma_channel_s *xfer_dmach = (struct dma_channel_s *)transfer;
uint32_t ctrl_ch;
uint32_t xfer_ch;
uint32_t xfer_reg_addr;
uint32_t ctrl;
DEBUGASSERT(ctrl_dmach && ctrl_dmach->inuse);
DEBUGASSERT(xfer_dmach && xfer_dmach->inuse);
ctrl_ch = ctrl_dmach->chan;
xfer_ch = xfer_dmach->chan;
xfer_dmach->callback = callback;
xfer_dmach->arg = arg;
xfer_reg_addr = RP23XX_DMA_AL1_CTRL(xfer_ch);
/* Set DMA registers */
putreg32((uint32_t)ctrl_blks, RP23XX_DMA_READ_ADDR(ctrl_ch));
putreg32(xfer_reg_addr, RP23XX_DMA_WRITE_ADDR(ctrl_ch));
putreg32(4, RP23XX_DMA_TRANS_COUNT(ctrl_ch));
/* Configure the xfer dma channel as follows:
* clear read and write error flags
* set increment on both read and write
* set 32-bit (word) transfer size
* run the ctrl at high priority
* RING_SIZE applies to write
* set RING_SIZE to wrap every 16 bytes
* don't chain to another dma (chain set to ourself)
* use un-paced transfer mode TREQ_SEL = 0x3f
*/
ctrl = RP23XX_DMA_CTRL_TRIG_READ_ERROR
| RP23XX_DMA_CTRL_TRIG_WRITE_ERROR
| RP23XX_DMA_CTRL_TRIG_INCR_READ
| RP23XX_DMA_CTRL_TRIG_INCR_WRITE
| RP23XX_DMA_CTRL_TRIG_HIGH_PRIORITY
| RP23XX_DMA_CTRL_TRIG_RING_SEL
| (4 << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
| (RP23XX_DMA_SIZE_WORD << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
| (ctrl_ch << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT)
| (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT);
putreg32(ctrl, RP23XX_DMA_CTRL_TRIG(ctrl_ch));
}
/****************************************************************************
* Name: rp23xx_ctrl_dmasetup
*
* Description:
* Configure a dma channel to send a list of channel control blocks to
* a second dma channel..
*
* Input Parameters:
* control - the DMA handle that reads the control blocks. This is
* the one that should be started.
* size - transfer size for this block
* pacing - dma pacing register for this block
* ctrl - Additional bits to set in CTRL_TRIG for this block.
*
****************************************************************************/
uint32_t rp23xx_dma_ctrl_blk_ctrl(DMA_HANDLE control,
int size,
uint32_t pacing,
uint32_t ctrl)
{
struct dma_channel_s *ctrl_dmach = (struct dma_channel_s *)control;
uint32_t ctrl_ch;
DEBUGASSERT(ctrl_dmach && ctrl_dmach->inuse);
ctrl_ch = ctrl_dmach->chan;
return RP23XX_DMA_CTRL_TRIG_EN
| RP23XX_DMA_CTRL_TRIG_IRQ_QUIET
| (ctrl_ch << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT)
| (size << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
| (pacing << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT)
| ctrl;
}
/****************************************************************************
* Name: rp23xx_dmastart
*
* Description:
* Start the DMA transfer
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
* - No DMA in progress
*
****************************************************************************/
void rp23xx_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
uint32_t ch;
DEBUGASSERT(dmach && dmach->inuse);
ch = dmach->chan;
/* Save the DMA complete callback info */
dmach->callback = callback;
dmach->arg = arg;
/* Enable the channel */
setbits_reg32(RP23XX_DMA_CTRL_TRIG_EN, RP23XX_DMA_CTRL_TRIG(ch));
}
/****************************************************************************
* Name: rp23xx_dmastop
*
* Description:
* Cancel the DMA. After rp23xx_dmastop() is called, the DMA channel is
* reset and rp23xx_dmasetup() must be called before rp23xx_dmastart()
* can be called again
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
*
****************************************************************************/
void rp23xx_dmastop(DMA_HANDLE handle)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
uint32_t bit;
uint32_t stat;
DEBUGASSERT(dmach);
bit = 1 << dmach->chan;
/* Disable the channel */
setbits_reg32(bit, RP23XX_DMA_CHAN_ABORT);
do
{
stat = getreg32(RP23XX_DMA_CHAN_ABORT);
}
while (stat & bit);
}
/****************************************************************************
* Name: rp23xx_dma_register
*
* Description:
* Get the address of a DMA register based on the given dma handle that
* can be used in the various putreg, getreg and modifyreg functions.
*
* This allows other configuration options not normally supplied.
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
*
****************************************************************************/
uintptr_t rp23xx_dma_register(DMA_HANDLE handle, uint16_t offset)
{
struct dma_channel_s *dmach = (struct dma_channel_s *)handle;
DEBUGASSERT(dmach && dmach->inuse);
return RP23XX_DMA_CH(dmach->chan) + offset;
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_dmac.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_DMAC_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_DMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "hardware/rp23xx_dma.h"
#include "hardware/rp23xx_dreq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_DMA_NCHANNELS 16
/* DMA data size ************************************************************/
#define RP23XX_DMA_SIZE_BYTE 0
#define RP23XX_DMA_SIZE_HALFWORD 1
#define RP23XX_DMA_SIZE_WORD 2
/* Use this as last item in a DMA control block chain */
#define RP23XX_DMA_CTRL_BLOCK_END \
{ \
RP23XX_DMA_CTRL_TRIG_IRQ_QUIET, \
0, \
0, \
0 \
}
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA_HANDLE provides an opaque reference that can be used to represent a
* DMA channel.
*/
typedef void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:
* handle - Refers to the DMA channel or stream
* status - The completion status (0:no error)
* arg - A user-provided value that was provided when rp23xx_dmastart()
* was called.
*/
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
/* Type of 'config' argument passed to rp23xx_rxdmasetup() and
* rp23xx_txdmasetup().
*/
typedef struct
{
uint8_t dreq;
uint8_t size;
uint8_t noincr;
} dma_config_t;
/* Type of items in the array items to 'ctrl_blks' argument for
* rp23xx_ctrl_dmasetup().
*/
typedef struct
{
uint32_t ctrl_trig;
uintptr_t read_addr;
uintptr_t write_addr;
uint32_t xfer_count;
} dma_control_block_t;
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_dmachannel
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually
* exclusive access to a DMA channel.
*
* If no DMA channel is available, then rp23xx_dmachannel() will wait until
* the holder of a channel relinquishes the channel by calling
* rp23xx_dmafree().
*
* Input parameters:
* None
*
* Returned Value:
* This function ALWAYS returns a non-NULL, void* DMA channel handle.
*
* Assumptions:
* - The caller can wait for a DMA channel to be freed if it is
* not available.
*
****************************************************************************/
DMA_HANDLE rp23xx_dmachannel(void);
/****************************************************************************
* Name: rp23xx_dmafree
*
* Description:
* Release a DMA channel.
* If another thread is waiting for this DMA channel in a call to
* rp23xx_dmachannel, then this function will re-assign the DMA channel to
* that thread and wake it up.
* NOTE:
* The 'handle' used in this argument must NEVER be used again until
* rp23xx_dmachannel() is called again to re-gain access to the channel.
*
* Returned Value:
* None
*
* Assumptions:
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
****************************************************************************/
void rp23xx_dmafree(DMA_HANDLE handle);
/****************************************************************************
* Name: rp23xx_rxdmasetup
*
* Description:
* Configure an RX (peripheral-to-memory) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (source)
* maddr - Memory address (destination)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void rp23xx_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/****************************************************************************
* Name: rp23xx_txdmasetup
*
* Description:
* Configure an TX (memory-to-peripheral) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (destination)
* maddr - Memory address (source)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void rp23xx_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/****************************************************************************
* Name: rp23xx_ctrl_dmasetup
*
* Description:
* Configure a dma channel to send a list of channel control blocks to
* a second dma channel..
*
* Input Parameters:
* control - the DMA handle that reads the control blocks. This is
* the one that should be started.
* transfer - the DMA handle the transfers data to the peripheral. No
* setup of this handle is required by the caller.
* ctrl_blks - the array of control blocks to used. Terminate this
* list with an all zero control block.
* callback - callback when last transfer completes
* arg - arg to pass to callback
*
****************************************************************************/
void rp23xx_ctrl_dmasetup(DMA_HANDLE control,
DMA_HANDLE transfer,
dma_control_block_t *ctrl_blks,
dma_callback_t callback,
void *arg);
/****************************************************************************
* Name: rp23xx_ctrl_dmasetup
*
* Description:
* Configure a dma channel to send a list of channel control blocks to
* a second dma channel..
*
* Input Parameters:
* control - the DMA handle that reads the control blocks. This is
* the one that should be started.
* size - transfer size for this block
* pacing - dma pacing register for this block
* ctrl - Additional bits to set in CTRL_TRIG for this block.
*
****************************************************************************/
uint32_t rp23xx_dma_ctrl_blk_ctrl(DMA_HANDLE control,
int size,
uint32_t pacing,
uint32_t ctrl);
/****************************************************************************
* Name: rp23xx_dmastart
*
* Description:
* Start the DMA transfer
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
* - No DMA in progress
*
****************************************************************************/
void rp23xx_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/****************************************************************************
* Name: rp23xx_dmastop
*
* Description:
* Cancel the DMA. After rp23xx_dmastop() is called, the DMA channel is
* reset and rp23xx_dmasetup() must be called before rp23xx_dmastart() can
* be called again.
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
*
****************************************************************************/
void rp23xx_dmastop(DMA_HANDLE handle);
/****************************************************************************
* Name: rp23xx_dma_register
*
* Description:
* Get the address of a DMA register based on the given DMA handle that
* can be used in the various putreg, getreg and modifyreg functions.
*
* This allows other configuration options not normally supplied.
*
* Assumptions:
* - DMA handle allocated by rp23xx_dmachannel()
*
****************************************************************************/
uintptr_t rp23xx_dma_register(DMA_HANDLE handle, uint16_t offset);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_DMAC_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_gpio.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "rp23xx_gpio.h"
/****************************************************************************
* Private Data
****************************************************************************/
/* GPIO interrupt initialize flag */
static bool g_gpio_irq_init = false;
/* GPIO interrupt handlers information */
static xcpt_t g_gpio_irq_handlers[RP23XX_GPIO_NUM];
static void *g_gpio_irq_args[RP23XX_GPIO_NUM];
static int g_gpio_irq_modes[RP23XX_GPIO_NUM];
/* GPIO pins function assignment */
static int g_gpio_function[RP23XX_GPIO_NUM];
/* GPIO pins function mapping table */
#ifdef CONFIG_RP23XX_RV_RP2350B
static const int g_gpio_function_mapping_spi[2][7] =
#else
static const int g_gpio_function_mapping_spi[2][5] =
#endif
{
{
0, 4, 16, 20,
#ifdef CONFIG_RP23XX_RV_RP2350B
32, 36,
#endif
-1
}, /* pin numbers assignable to SPI0 */
{
8, 12, 24, 28,
#ifdef CONFIG_RP23XX_RV_RP2350B
40, 44
#endif
-1
}, /* pin numbers assignable to SPI1 */
};
#ifdef CONFIG_RP23XX_RV_RP2350B
static const int g_gpio_function_mapping_uart[2][7] =
#else
static const int g_gpio_function_mapping_uart[2][5] =
#endif
{
{
0, 12, 16, 28,
#ifdef CONFIG_RP23XX_RV_RP2350B
32, 44,
#endif
-1
}, /* pin numbers assignable to UART0 */
{
4, 8, 20, 24,
-1,
#ifdef CONFIG_RP23XX_RV_RP2350B
36, 40,
#endif
}, /* pin numbers assignable to UART1 */
};
#ifdef CONFIG_RP23XX_RV_RP2350B
static const int g_gpio_function_mapping_i2c[2][13] =
#else
static const int g_gpio_function_mapping_i2c[2][9] =
#endif
{
{
0, 4, 8, 12, 16, 20, 24, 28,
#ifdef CONFIG_RP23XX_RV_RP2350B
32, 36, 40, 44,
#endif
-1
}, /* pin numbers assignable to I2C0 */
{
2, 6, 10, 14, 18, 22, 26,
#ifdef CONFIG_RP23XX_RV_RP2350B
30, 34, 38, 42
#endif
-1
}, /* pin numbers assignable to I2C1 */
};
#ifdef CONFIG_RP23XX_RV_RP2350B
static const int g_gpio_function_mapping_pwm[12][3] =
#else
static const int g_gpio_function_mapping_pwm[8][3] =
#endif
{
{ 0, 16, -1 }, /* pin numbers assignable to PWM0 */
{ 2, 18, -1 }, /* pin numbers assignable to PWM1 */
{ 4, 20, -1 }, /* pin numbers assignable to PWM2 */
{ 6, 22, -1 }, /* pin numbers assignable to PWM3 */
{ 8, 24, -1 }, /* pin numbers assignable to PWM4 */
{ 10, 26, -1 }, /* pin numbers assignable to PWM5 */
{ 12, 28, -1 }, /* pin numbers assignable to PWM6 */
#ifdef CONFIG_RP23XX_RV_RP2350B
{ 14, 30, -1 }, /* pin numbers assignable to PWM7 */
{ 32, 40, -1 }, /* pin numbers assignable to PWM8 */
{ 34, 42, -1 }, /* pin numbers assignable to PWM9 */
{ 36, 44, -1 }, /* pin numbers assignable to PWM10 */
{ 38, 46, -1 }, /* pin numbers assignable to PWM11 */
#else
{ 14, -1, -1 }, /* pin numbers assignable to PWM7 */
#endif
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_gpio_interrupt
*
* Description:
* GPIO interrupt handler
*
****************************************************************************/
static int rp23xx_gpio_interrupt(int irq, void *context, void *arg)
{
int i;
int j;
uint32_t stat;
uint32_t gpio;
xcpt_t handler;
/* Scan all GPIO interrupt status registers */
for (i = 0; i < 6; i++)
{
/* Get and clear pending GPIO interrupt status */
stat = getreg32(RP23XX_IO_BANK0_PROC_INTS(i * 8, 0));
if (i == 3)
{
stat &= 0x00ffffff; /* Clear reserved bits */
}
putreg32(stat, RP23XX_IO_BANK0_INTR(i * 8));
while (stat != 0)
{
/* Scan all GPIO pins in one register */
for (j = 0; j < 8; j++)
{
if (stat & (0xf << (j * 4)))
{
stat &= ~(0xf << (j * 4));
gpio = i * 8 + j;
handler = g_gpio_irq_handlers[gpio];
/* Call GPIO interrupt handler */
if (handler)
{
handler(gpio, context, g_gpio_irq_args[gpio]);
}
}
}
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_gpio_get_function_pin
*
* Description:
* Get the GPIO pin number to which the specified function is assigned
*
****************************************************************************/
int rp23xx_gpio_get_function_pin(uint32_t func, uint32_t port)
{
int i;
const int *mapping;
/* Get GPIO pins function mapping table */
switch (func)
{
case RP23XX_GPIO_FUNC_SPI:
if (port >= 2)
{
return -1;
}
mapping = g_gpio_function_mapping_spi[port];
break;
case RP23XX_GPIO_FUNC_UART:
if (port >= 2)
{
return -1;
}
mapping = g_gpio_function_mapping_uart[port];
break;
case RP23XX_GPIO_FUNC_I2C:
if (port >= 2)
{
return -1;
}
mapping = g_gpio_function_mapping_i2c[port];
break;
case RP23XX_GPIO_FUNC_PWM:
if (port >= 8)
{
return -1;
}
mapping = g_gpio_function_mapping_pwm[port];
break;
default:
return -1;
}
/* Find the specified function in the current assignment */
for (i = 0; mapping[i] >= 0; i++)
{
if (g_gpio_function[mapping[i]] == func)
{
return mapping[i];
}
}
return -1;
}
/****************************************************************************
* Name: rp23xx_gpio_set_function
*
* Description:
* Assign functions to the specified GPIO pin
*
****************************************************************************/
void rp23xx_gpio_set_function(uint32_t gpio, uint32_t func)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
modbits_reg32(RP23XX_PADS_BANK0_GPIO_IE,
RP23XX_PADS_BANK0_GPIO_ISO |
RP23XX_PADS_BANK0_GPIO_IE |
RP23XX_PADS_BANK0_GPIO_OD,
RP23XX_PADS_BANK0_GPIO(gpio));
putreg32(func & RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK,
RP23XX_IO_BANK0_GPIO_CTRL(gpio));
g_gpio_function[gpio] = func;
}
/****************************************************************************
* Name: rp23xx_gpio_set_pulls
*
* Description:
* Set pull-up or pull-down to the specified GPIO pin
*
****************************************************************************/
void rp23xx_gpio_set_pulls(uint32_t gpio, int up, int down)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
modbits_reg32((up ? RP23XX_PADS_BANK0_GPIO_PUE : 0) |
(down ? RP23XX_PADS_BANK0_GPIO_PDE : 0),
RP23XX_PADS_BANK0_GPIO_PUE | RP23XX_PADS_BANK0_GPIO_PDE,
RP23XX_PADS_BANK0_GPIO(gpio));
}
/****************************************************************************
* Name: rp23xx_gpio_init
*
* Description:
* Initialize software-controlled GPIO function
*
****************************************************************************/
void rp23xx_gpio_init(uint32_t gpio)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
rp23xx_gpio_setdir(gpio, false);
rp23xx_gpio_put(gpio, false);
rp23xx_gpio_set_function(gpio, RP23XX_GPIO_FUNC_SIO);
}
/****************************************************************************
* Name: rp23xx_gpio_irq_attach
*
* Description:
* Configure the interrupt generated by the specified GPIO pin.
*
****************************************************************************/
int rp23xx_gpio_irq_attach(uint32_t gpio, uint32_t intrmode,
xcpt_t isr, void *arg)
{
if (!g_gpio_irq_init)
{
/* Initialize - register GPIO interrupt handler */
g_gpio_irq_init = true;
irq_attach(RP23XX_IO_IRQ_BANK0, rp23xx_gpio_interrupt, NULL);
up_enable_irq(RP23XX_IO_IRQ_BANK0);
}
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
DEBUGASSERT(intrmode <= RP23XX_GPIO_INTR_EDGE_HIGH);
/* Save handler information */
g_gpio_irq_handlers[gpio] = isr;
g_gpio_irq_args[gpio] = arg;
g_gpio_irq_modes[gpio] = intrmode;
/* Clear pending interrupts */
setbits_reg32(0xf << ((gpio % 8) * 4), RP23XX_IO_BANK0_INTR(gpio));
return OK;
}
/****************************************************************************
* Name: rp23xx_gpio_enable_irq
*
* Description:
* Enable the GPIO IRQ specified by 'gpio'
*
****************************************************************************/
void rp23xx_gpio_enable_irq(uint32_t gpio)
{
uint32_t reg;
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
if (g_gpio_irq_handlers[gpio] != NULL)
{
/* Set interrupt enable bit */
reg = RP23XX_IO_BANK0_PROC_INTE(gpio, 0);
clrbits_reg32(0xf << ((gpio % 8) * 4), reg);
setbits_reg32(0x1 << ((gpio % 8) * 4 + g_gpio_irq_modes[gpio]), reg);
}
}
/****************************************************************************
* Name: rp23xx_gpio_disable_irq
*
* Description:
* Disable the GPIO IRQ specified by 'gpio'
*
****************************************************************************/
void rp23xx_gpio_disable_irq(uint32_t gpio)
{
uint32_t reg;
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
if (g_gpio_irq_handlers[gpio] != NULL)
{
/* Clear interrupt enable bit */
reg = RP23XX_IO_BANK0_PROC_INTE(gpio, 0);
clrbits_reg32(0xf << ((gpio % 8) * 4), reg);
}
}
/****************************************************************************
* Name: rp23xx_gpio_clear_interrupt
*
* Description:
* Clear the interrupt flags for a gpio pin.
*
****************************************************************************/
void rp23xx_gpio_clear_interrupt(uint32_t gpio,
bool edge_low,
bool edge_high)
{
uint32_t reg;
uint32_t bits = 0;
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
reg = RP23XX_IO_BANK0_INTR(gpio);
if (edge_low) bits |= 0x04 << (gpio % 8);
if (edge_high) bits |= 0x08 << (gpio % 8);
clrbits_reg32(bits, reg);
}
/****************************************************************************
* Name: rp23xx_gpio_initialize
*
* Description:
* Initialize GPIO function management
*
****************************************************************************/
void rp23xx_gpio_initialize(void)
{
int i;
for (i = 0; i < RP23XX_GPIO_NUM; i++)
{
g_gpio_function[i] = RP23XX_GPIO_FUNC_NULL;
}
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_GPIO_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include "riscv_internal.h"
#include "hardware/rp23xx_sio.h"
#include "hardware/rp23xx_pads_bank0.h"
#include "hardware/rp23xx_io_bank0.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_RP2350B
#define RP23XX_GPIO_NUM 48 /* Number of GPIO pins */
#else
#define RP23XX_GPIO_NUM 30 /* Number of GPIO pins */
#endif
/* GPIO function types ******************************************************/
#define RP23XX_GPIO_FUNC_HSTX RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_HSTX
#define RP23XX_GPIO_FUNC_SPI RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SPI
#define RP23XX_GPIO_FUNC_UART RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART
#define RP23XX_GPIO_FUNC_I2C RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_I2C
#define RP23XX_GPIO_FUNC_PWM RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PWM
#define RP23XX_GPIO_FUNC_SIO RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SIO
#define RP23XX_GPIO_FUNC_PIO0 RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO0
#define RP23XX_GPIO_FUNC_PIO1 RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO1
#define RP23XX_GPIO_FUNC_PIO2 RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO2
#define RP23XX_GPIO_FUNC_GPCK RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_GPCK
#define RP23XX_GPIO_FUNC_USB RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_USB
#define RP23XX_GPIO_FUNC_UART_AUX RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART_AUX
#define RP23XX_GPIO_FUNC_NULL RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL
/* GPIO function pins *******************************************************/
#define RP23XX_GPIO_PIN_CLK_GPOUT0 (21)
#define RP23XX_GPIO_PIN_CLK_GPOUT1 (23)
#define RP23XX_GPIO_PIN_CLK_GPOUT2 (24)
#define RP23XX_GPIO_PIN_CLK_GPOUT3 (25)
/* GPIO interrupt modes *****************************************************/
#define RP23XX_GPIO_INTR_LEVEL_LOW 0
#define RP23XX_GPIO_INTR_LEVEL_HIGH 1
#define RP23XX_GPIO_INTR_EDGE_LOW 2
#define RP23XX_GPIO_INTR_EDGE_HIGH 3
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
static inline void rp23xx_gpio_put(uint32_t gpio, int set)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
#if (RP23XX_GPIO_NUM <= 32)
uint32_t value = 1 << gpio;
if (set)
{
putreg32(value, RP23XX_SIO_GPIO_OUT_SET);
}
else
{
putreg32(value, RP23XX_SIO_GPIO_OUT_CLR);
}
#else
uint32_t mask = 1ul << (gpio & 0x1fu);
if (gpio < 32)
{
if (set)
{
putreg32(mask, RP23XX_SIO_GPIO_OUT_SET);
}
else
{
putreg32(mask, RP23XX_SIO_GPIO_OUT_CLR);
}
}
else
{
if (set)
{
putreg32(mask, RP23XX_SIO_GPIO_HI_OUT_SET);
}
else
{
putreg32(mask, RP23XX_SIO_GPIO_HI_OUT_CLR);
}
}
#endif
}
static inline bool rp23xx_gpio_get(uint32_t gpio)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
#if (RP23XX_GPIO_NUM <= 32)
uint32_t value = 1 << gpio;
return (getreg32(RP23XX_SIO_GPIO_IN) & value) != 0;
#else
if (gpio < 32)
{
uint32_t value = 1 << gpio;
return (getreg32(RP23XX_SIO_GPIO_IN) & value) != 0;
}
else
{
uint32_t value = 1 << (gpio -32);
return (getreg32(RP23XX_SIO_GPIO_HI_IN) & value) != 0;
}
#endif
}
static inline void rp23xx_gpio_setdir(uint32_t gpio, int out)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
#if (RP23XX_GPIO_NUM <= 32)
uint32_t value = 1 << gpio;
if (out)
{
putreg32(value, RP23XX_SIO_GPIO_OE_SET);
}
else
{
putreg32(value, RP23XX_SIO_GPIO_OE_CLR);
}
#else
uint32_t mask = 1ul << (gpio & 0x1fu);
if (gpio < 32)
{
if (out)
{
putreg32(mask, RP23XX_SIO_GPIO_OE_SET);
}
else
{
putreg32(mask, RP23XX_SIO_GPIO_OE_CLR);
}
}
else
{
if (out)
{
putreg32(mask, RP23XX_SIO_GPIO_HI_OE_SET);
}
else
{
putreg32(mask, RP23XX_SIO_GPIO_HI_OE_CLR);
}
}
#endif
}
/****************************************************************************
* Name: rp23xx_gpio_set_input_hysteresis_enabled
*
* Description:
* Set whether the pin's input hysteresis will be enabled.
*
****************************************************************************/
static inline void rp23xx_gpio_set_input_hysteresis_enabled(uint32_t gpio,
bool enabled)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
modbits_reg32(enabled ? RP23XX_PADS_BANK0_GPIO_SCHMITT : 0,
RP23XX_PADS_BANK0_GPIO_SCHMITT,
RP23XX_PADS_BANK0_GPIO(gpio));
}
/****************************************************************************
* Name: rp23xx_gpio_set_slew_fast
*
* Description:
* Set whether the pin's fast slew rate will be enabled.
*
****************************************************************************/
static inline void rp23xx_gpio_set_slew_fast(uint32_t gpio,
bool enabled)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
modbits_reg32(enabled ? RP23XX_PADS_BANK0_GPIO_SLEWFAST : 0,
RP23XX_PADS_BANK0_GPIO_SLEWFAST,
RP23XX_PADS_BANK0_GPIO(gpio));
}
/****************************************************************************
* Name: rp23xx_gpio_set_drive_strength
*
* Description:
* Set the pin's drive strength.
*
****************************************************************************/
static inline void rp23xx_gpio_set_drive_strength(uint32_t gpio,
uint32_t drive_strength)
{
DEBUGASSERT(gpio < RP23XX_GPIO_NUM);
modbits_reg32(drive_strength,
RP23XX_PADS_BANK0_GPIO_DRIVE_MASK,
RP23XX_PADS_BANK0_GPIO(gpio));
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_gpio_get_function_pin
*
* Description:
* Get the GPIO pin number to which the specified function is assigned
*
****************************************************************************/
int rp23xx_gpio_get_function_pin(uint32_t func, uint32_t port);
/****************************************************************************
* Name: rp23xx_gpio_set_function
*
* Description:
* Assign functions to the specified GPIO pin
*
****************************************************************************/
void rp23xx_gpio_set_function(uint32_t gpio, uint32_t func);
/****************************************************************************
* Name: rp23xx_gpio_set_pulls
*
* Description:
* Set pull-up or pull-down to the specified GPIO pin
*
****************************************************************************/
void rp23xx_gpio_set_pulls(uint32_t gpio, int up, int down);
/****************************************************************************
* Name: rp23xx_gpio_init
*
* Description:
* Initialize software-controlled GPIO function
*
****************************************************************************/
void rp23xx_gpio_init(uint32_t gpio);
/****************************************************************************
* Name: rp23xx_gpio_irq_attach
*
* Description:
* Configure the interrupt generated by the specified GPIO pin.
*
****************************************************************************/
int rp23xx_gpio_irq_attach(uint32_t gpio, uint32_t intrmode,
xcpt_t isr, void *arg);
/****************************************************************************
* Name: rp23xx_gpio_enable_irq
*
* Description:
* Enable the GPIO IRQ specified by 'gpio'
*
****************************************************************************/
void rp23xx_gpio_enable_irq(uint32_t gpio);
/****************************************************************************
* Name: rp23xx_gpio_disable_irq
*
* Description:
* Disable the GPIO IRQ specified by 'gpio'
*
****************************************************************************/
void rp23xx_gpio_disable_irq(uint32_t gpio);
/****************************************************************************
* Name: rp23xx_gpio_clear_interrupt
*
* Description:
* Clear the interrupt flags for a gpio pin.
*
****************************************************************************/
void rp23xx_gpio_clear_interrupt(uint32_t gpio,
bool edge_low,
bool edge_high);
/****************************************************************************
* Name: rp23xx_gpio_initialize
*
* Description:
* Initialize GPIO function management
*
****************************************************************************/
void rp23xx_gpio_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_GPIO_H */

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arch/risc-v/src/rp23xx-rv/rp23xx_head.S Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_head.S
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "chip.h"
#include "hardware/rp23xx_memorymap.h"
#include "riscv_internal.h"
/****************************************************************************
* Public Symbols
****************************************************************************/
/* Imported symbols */
.extern __trap_vec
.section .text
.global __start
__start:
/* Set stack pointer to the idle thread stack */
la sp, RP23XX_IDLE_STACK
/* Disable all interrupts (i.e. timer, external) in mie */
csrw CSR_MIE, zero
/* Initialize the Machine Trap Vector */
la t0, __trap_vec
csrw CSR_MTVEC, t0
/* Jump to __rp23xx_start */
jal x1, __rp23xx_start
/* We shouldn't return from __rpx23xx_start */
.global _init
.global _fini
_init:
_fini:
/* These don't have to do anything since we use init_array/fini_array. */
ret

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arch/risc-v/src/rp23xx-rv/rp23xx_heaps.c Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_heaps.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/arch.h>
#include <nuttx/config.h>
#include <nuttx/kmalloc.h>
#include <nuttx/mm/mm.h>
#include "riscv_internal.h"
#if defined(CONFIG_RP23XX_RV_PSRAM)
/****************************************************************************
* Private Data
****************************************************************************/
static void * const psram_start = (void *)0x11000000ul;
static const size_t psram_size = 8 * 1024 * 1024;
/****************************************************************************
* Public Functions
****************************************************************************/
#if defined(CONFIG_RP23XX_RV_PSRAM_HEAP_SEPARATE)
static struct mm_heap_s *g_psramheap;
#endif
#if defined(CONFIG_RP23XX_RV_PSRAM_HEAP_SINGLE)
#if defined(CONFIG_MM_KERNEL_HEAP)
#error cannot use CONFIG_MM_KERNEL_HEAP with single heap
#endif
#if CONFIG_MM_REGIONS > 1
void riscv_addregion(void)
{
/* Add the PSRAM region to main heap */
kumm_addregion(psram_start, psram_size);
}
#endif
#elif defined (CONFIG_RP23XX_RV_PSRAM_HEAP_USER)
#if !defined(CONFIG_MM_KERNEL_HEAP)
#error MM_KERNEL_HEAP is required for separate kernel heap
#endif
/* Use the internal SRAM as the kernel heap */
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
*heap_start = (void *)g_idle_topstack;
#ifdef CONFIG_ARCH_PGPOOL_PBASE
*heap_size = CONFIG_ARCH_PGPOOL_PBASE - g_idle_topstack;
#else
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif
}
/* Use the external PSRAM as the default user heap */
void up_allocate_heap(void **heap_start, size_t *heap_size)
{
*heap_start = psram_start;
*heap_size = psram_size;
}
#elif defined (CONFIG_RP23XX_RV_PSRAM_HEAP_SEPARATE)
#if !defined(CONFIG_ARCH_HAVE_EXTRA_HEAPS)
#error ARCH_HAVE_EXTRA_HEAPS is required for multiple heaps
#endif
void up_extraheaps_init(void)
{
g_psramheap = mm_initialize("psram", psram_start, psram_size);
}
#endif
#endif

952
arch/risc-v/src/rp23xx-rv/rp23xx_i2c.c Normal file
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@ -0,0 +1,952 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2c.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <nuttx/mutex.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
#include "riscv_internal.h"
#include "rp23xx_i2c.h"
#include "hardware/rp23xx_i2c.h"
#include "hardware/rp23xx_resets.h"
#include "rp23xx_gpio.h"
#ifdef CONFIG_RP23XX_RV_I2C
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
#define I2C_DEFAULT_FREQUENCY 400000
#define I2C_FIFO_MAX_SIZE 16
#define I2C_INTR_ENABLE ((RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET) | \
(RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT) | \
(RP23XX_RV_I2C_IC_INTR_STAT_R_TX_OVER) | \
(RP23XX_RV_I2C_IC_INTR_STAT_R_RX_OVER) | \
(RP23XX_RV_I2C_IC_INTR_STAT_R_RX_UNDER))
/****************************************************************************
* Private Data
****************************************************************************/
struct rp23xx_i2cdev_s
{
struct i2c_master_s dev; /* Generic I2C device */
unsigned int base; /* Base address of registers */
uint16_t irqid; /* IRQ for this device */
int8_t port; /* Port number */
uint32_t base_freq; /* branch frequency */
mutex_t lock; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for transfer completion */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
ssize_t reg_buff_offset;
ssize_t rw_size;
struct i2c_msg_s *msgs;
int error; /* Error status of each transfers */
int refs; /* Reference count */
};
#ifdef CONFIG_RP23XX_RV_I2C0
static struct rp23xx_i2cdev_s g_i2c0dev =
{
.port = 0,
.base = RP23XX_RV_I2C0_BASE,
.irqid = RP23XX_RV_I2C0_IRQ,
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
#endif
#ifdef CONFIG_RP23XX_RV_I2C1
static struct rp23xx_i2cdev_s g_i2c1dev =
{
.port = 1,
.base = RP23XX_RV_I2C1_BASE,
.irqid = RP23XX_RV_I2C1_IRQ,
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
static inline uint32_t i2c_reg_read(struct rp23xx_i2cdev_s *priv,
uint32_t offset);
static inline void i2c_reg_write(struct rp23xx_i2cdev_s *priv,
uint32_t offset,
uint32_t val);
static inline void i2c_reg_rmw(struct rp23xx_i2cdev_s *dev,
uint32_t offset,
uint32_t val, uint32_t mask);
static int rp23xx_i2c_disable(struct rp23xx_i2cdev_s *priv);
static void rp23xx_i2c_init(struct rp23xx_i2cdev_s *priv);
static void rp23xx_i2c_enable(struct rp23xx_i2cdev_s *priv);
static int rp23xx_i2c_interrupt(int irq, void *context, void *arg);
static void rp23xx_i2c_timeout(wdparm_t arg);
static void rp23xx_i2c_setfrequency(struct rp23xx_i2cdev_s *priv,
uint32_t frequency);
static int rp23xx_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int rp23xx_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
* I2C device operations
****************************************************************************/
struct i2c_ops_s rp23xx_i2c_ops =
{
.transfer = rp23xx_i2c_transfer,
#ifdef CONFIG_I2C_RESET
.reset = rp23xx_i2c_reset,
#endif
};
/****************************************************************************
* Name: rp23xx_i2c_setfrequency
*
* Description:
* Set the frequency for the next transfer
*
****************************************************************************/
static void rp23xx_i2c_setfrequency(struct rp23xx_i2cdev_s *priv,
uint32_t frequency)
{
int32_t lcnt;
int32_t hcnt;
uint64_t lcnt64;
uint64_t hcnt64;
uint64_t speed;
uint64_t t_low;
uint64_t t_high;
uint32_t base = BOARD_PERI_FREQ;
uint32_t spklen;
ASSERT(base);
if ((priv->frequency == frequency) && (priv->base_freq == base))
{
return;
}
priv->frequency = frequency;
priv->base_freq = base;
base /= 1000;
if (frequency <= 100000)
{
t_low = 4700000;
t_high = 4000000;
}
else if (frequency <= 400000)
{
t_low = 1300000;
t_high = 600000;
}
else
{
t_low = 500000;
t_high = 260000;
}
if (frequency > 100000)
{
if (base < 20032)
{
spklen = 1;
}
else if (base < 40064)
{
spklen = 2;
}
else
{
spklen = 3;
}
}
else
{
spklen = 1;
}
lcnt64 = (t_low + 6500ull / 20000ull) * base;
lcnt = ((lcnt64 + 999999999ull) / 1000000000ull) - 1; /* ceil */
lcnt = lcnt < 8 ? 8 : lcnt;
hcnt64 = (t_high - 6500ull) * base;
hcnt = ((hcnt64 + 999999999ull) / 1000000000ull) - 6 - spklen; /* ceil */
hcnt = hcnt < 6 ? 6 : hcnt;
speed =
1000000000000000000ull /
(((lcnt + 1) * 1000000000000ull +
(hcnt + 6 + spklen) * 1000000000000ull) / base +
20000ull / 1000ull * 1000000ull);
if (speed > (frequency * 1000ull))
{
uint64_t adj;
adj = ((1000000000000000000ull / (frequency * 1000ull)) -
(1000000000000000000ull / speed)) *
base;
hcnt += (adj + 999999999999ull) / 1000000000000ull;
}
/* use FS register in SS and FS mode */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_FS_SCL_HCNT_OFFSET, hcnt);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_FS_SCL_LCNT_OFFSET, lcnt);
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_CON_OFFSET,
RP23XX_RV_I2C_IC_CON_SPEED_FAST,
RP23XX_RV_I2C_IC_CON_SPEED_MASK);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_FS_SPKLEN_OFFSET, spklen);
}
/****************************************************************************
* Name: rp23xx_i2c_timeout
*
* Description:
* Watchdog timer for timeout of I2C operation
*
****************************************************************************/
static void rp23xx_i2c_timeout(wdparm_t arg)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)arg;
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
nxsem_post(&priv->wait);
leave_critical_section(flags);
}
/****************************************************************************
* Name: rp23xx_i2c_drainrxfifo
*
* Description:
* Receive I2C data
*
****************************************************************************/
static void rp23xx_i2c_drainrxfifo(struct rp23xx_i2cdev_s *priv)
{
struct i2c_msg_s *msg = priv->msgs;
uint32_t status;
uint32_t dat;
ssize_t i;
DEBUGASSERT(msg != NULL);
status = i2c_reg_read(priv, RP23XX_RV_I2C_IC_STATUS_OFFSET);
for (i = 0; i < priv->rw_size &&
status & RP23XX_RV_I2C_IC_STATUS_RFNE; i++)
{
dat = i2c_reg_read(priv, RP23XX_RV_I2C_IC_DATA_CMD_OFFSET);
msg->buffer[priv->reg_buff_offset + i] = dat & 0xff;
status = i2c_reg_read(priv, RP23XX_RV_I2C_IC_STATUS_OFFSET);
}
priv->reg_buff_offset += priv->rw_size;
}
/****************************************************************************
* Name: rp23xx_i2c_interrupt
*
* Description:
* The I2C Interrupt Handler
*
****************************************************************************/
static int rp23xx_i2c_interrupt(int irq, void *context, void *arg)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)arg;
uint32_t state;
int ret;
state = i2c_reg_read(priv, RP23XX_RV_I2C_IC_INTR_STAT_OFFSET);
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT)
{
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_TX_ABRT_OFFSET);
priv->error = -ENODEV;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_OVER)
{
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_TX_OVER_OFFSET);
priv->error = -EIO;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_OVER)
{
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_RX_OVER_OFFSET);
priv->error = -EIO;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_UNDER)
{
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_RX_UNDER_OFFSET);
priv->error = -EIO;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY)
{
/* TX_EMPTY is automatically cleared by hardware
* when the buffer level goes above the threshold.
*/
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET,
0, RP23XX_RV_I2C_IC_INTR_MASK_M_TX_EMPTY);
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL)
{
/* RX_FULL is automatically cleared by hardware
* when the buffer level goes below the threshold.
*/
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET,
0, RP23XX_RV_I2C_IC_INTR_MASK_M_RX_FULL);
rp23xx_i2c_drainrxfifo(priv);
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET)
{
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_STOP_DET_OFFSET);
}
if ((priv->error) || (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY) ||
(state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL))
{
/* Failure of wd_cancel() means that the timer expired.
* In this case, nxsem_post() has already been called.
* Therefore, call nxsem_post() only when wd_cancel() succeeds.
*/
ret = wd_cancel(&priv->timeout);
if (ret == OK)
{
nxsem_post(&priv->wait);
}
}
return OK;
}
/****************************************************************************
* Name: rp23xx_i2c_receive
*
* Description:
* Receive data from I2C bus.
* Prohibit all interrupt because the STOP condition might happen
* if the interrupt occurs when the writing request.
* Actual receiving data is in RX_FULL interrupt handler.
*
* TODO : The argument "last" is not used.
****************************************************************************/
static int rp23xx_i2c_receive(struct rp23xx_i2cdev_s *priv, int last)
{
struct i2c_msg_s *msg = priv->msgs;
int i;
int en;
ssize_t msg_length;
irqstate_t flags;
priv->reg_buff_offset = 0;
DEBUGASSERT(msg != NULL);
for (msg_length = msg->length; msg_length > 0; msg_length -= priv->rw_size)
{
if (msg_length <= I2C_FIFO_MAX_SIZE)
{
priv->rw_size = msg_length;
en = 1;
}
else
{
priv->rw_size = I2C_FIFO_MAX_SIZE;
en = 0;
}
/* update threshold value of the receive buffer */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_RX_TL_OFFSET, priv->rw_size - 1);
for (i = 0; i < priv->rw_size - 1; i++)
{
i2c_reg_write(priv, RP23XX_RV_I2C_IC_DATA_CMD_OFFSET,
RP23XX_RV_I2C_IC_DATA_CMD_CMD);
}
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp23xx_i2c_timeout, (wdparm_t)priv);
/* Set stop flag for indicate the last data */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_DATA_CMD_OFFSET,
RP23XX_RV_I2C_IC_DATA_CMD_CMD |
(en ? RP23XX_RV_I2C_IC_DATA_CMD_STOP : 0));
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET,
RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL,
RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
if (priv->error != OK)
{
break;
}
}
return 0;
}
/****************************************************************************
* Name: rp23xx_i2c_send
*
* Description:
* Send data to I2C bus.
*
****************************************************************************/
static int rp23xx_i2c_send(struct rp23xx_i2cdev_s *priv, int last)
{
struct i2c_msg_s *msg = priv->msgs;
ssize_t i;
irqstate_t flags;
DEBUGASSERT(msg != NULL);
for (i = 0; i < msg->length - 1; i++)
{
while (!(i2c_reg_read(priv, RP23XX_RV_I2C_IC_STATUS_OFFSET)
& RP23XX_RV_I2C_IC_STATUS_TFNF))
;
i2c_reg_write(priv, RP23XX_RV_I2C_IC_DATA_CMD_OFFSET,
(uint32_t)msg->buffer[i]);
}
while (!(i2c_reg_read(priv, RP23XX_RV_I2C_IC_STATUS_OFFSET)
& RP23XX_RV_I2C_IC_STATUS_TFNF))
;
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp23xx_i2c_timeout, (wdparm_t)priv);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_DATA_CMD_OFFSET,
(uint32_t)msg->buffer[i] |
(last ? RP23XX_RV_I2C_IC_DATA_CMD_STOP : 0));
/* Enable TX_EMPTY interrupt for determine transfer done. */
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET,
RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY,
RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
return 0;
}
/****************************************************************************
* Name: rp23xx_i2c_transfer
*
* Description:
* Perform a sequence of I2C transfers
*
* TODO: Multiple i2c_msg_s read operations with the same address are not
* currently guaranteed.
****************************************************************************/
static int rp23xx_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)dev;
int i;
int ret = 0;
int semval = 0;
int addr = -1;
static int wostop = 0;
DEBUGASSERT(dev != NULL);
/* Get exclusive access to the I2C bus */
nxmutex_lock(&priv->lock);
/* Check wait semaphore value. If the value is not 0, the transfer can not
* be performed normally.
*/
ret = nxsem_get_value(&priv->wait, &semval);
DEBUGASSERT(ret == OK && semval == 0);
for (i = 0; i < count; i++, msgs++)
{
/* Pass msg descriptor via device context */
priv->msgs = msgs;
priv->error = OK;
if ((addr != msgs->addr) && !wostop)
{
rp23xx_i2c_disable(priv);
rp23xx_i2c_setfrequency(priv, msgs->frequency);
i2c_reg_rmw(priv, RP23XX_RV_I2C_IC_CON_OFFSET,
RP23XX_RV_I2C_IC_CON_IC_RESTART_EN,
RP23XX_RV_I2C_IC_CON_IC_RESTART_EN);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_TAR_OFFSET,
msgs->addr & 0x7f);
rp23xx_i2c_enable(priv);
addr = msgs->addr;
}
if (msgs->flags & I2C_M_NOSTOP)
{
/* Don't send stop condition even if the last data */
wostop = 1;
}
else
{
wostop = 0;
}
if (msgs->flags & I2C_M_READ)
{
ret = rp23xx_i2c_receive(priv, (wostop) ? 0 : (i + 1 == count));
}
else
{
ret = rp23xx_i2c_send(priv, (wostop) ? 0 : (i + 1 == count));
}
if (ret < 0)
{
break;
}
if (priv->error != OK)
{
ret = priv->error;
wostop = 0;
break;
}
/* Clear msg descriptor for prevent illegal access in interrupt */
priv->msgs = NULL;
}
if (!wostop)
{
rp23xx_i2c_disable(priv);
}
nxmutex_unlock(&priv->lock);
return ret;
}
/****************************************************************************
* Name: rp23xx_i2c_reset
*
* Description:
* Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int rp23xx_i2c_reset(struct i2c_master_s *dev)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)dev;
unsigned int clock_count;
unsigned int stretch_count;
uint32_t scl_gpio;
uint32_t sda_gpio;
uint32_t subsys;
uint32_t frequency;
int pin;
int ret;
DEBUGASSERT(dev);
/* Our caller must own a ref */
DEBUGASSERT(priv->refs > 0);
/* Lock out other clients */
nxmutex_lock(&priv->lock);
ret = -EIO;
/* De-init the port */
rp23xx_i2c_disable(priv);
/* Use GPIO configuration to un-wedge the bus */
pin = rp23xx_gpio_get_function_pin(RP23XX_GPIO_FUNC_I2C, priv->port);
if (pin < 0)
{
goto out_without_reinit;
}
sda_gpio = pin;
scl_gpio = pin + 1;
subsys = (priv->port == 0) ? RP23XX_RESETS_RESET_I2C0 :
RP23XX_RESETS_RESET_I2C1;
rp23xx_gpio_init(sda_gpio);
rp23xx_gpio_setdir(sda_gpio, true);
rp23xx_gpio_set_pulls(sda_gpio, true, false); /* Pull up */
rp23xx_gpio_put(sda_gpio, true);
rp23xx_gpio_init(scl_gpio);
rp23xx_gpio_setdir(scl_gpio, true);
rp23xx_gpio_set_pulls(scl_gpio, true, false);
rp23xx_gpio_put(scl_gpio, true);
/* Let SDA go high */
rp23xx_gpio_put(sda_gpio, true);
/* Clock the bus until any slaves currently driving it let it go. */
clock_count = 0;
while (!rp23xx_gpio_get(sda_gpio))
{
/* Give up if we have tried too hard */
if (clock_count++ > 10)
{
goto out;
}
/* Sniff to make sure that clock stretching has finished. If the bus
* never relaxes, the reset has failed.
*/
stretch_count = 0;
while (!rp23xx_gpio_get(scl_gpio))
{
/* Give up if we have tried too hard */
if (stretch_count++ > 10)
{
goto out;
}
up_udelay(10);
}
/* Drive SCL low */
rp23xx_gpio_put(scl_gpio, false);
up_udelay(10);
/* Drive SCL high again */
rp23xx_gpio_put(scl_gpio, true);
up_udelay(10);
}
/* Generate a start followed by a stop to reset slave state machines. */
rp23xx_gpio_put(sda_gpio, false);
up_udelay(10);
rp23xx_gpio_put(scl_gpio, false);
up_udelay(10);
rp23xx_gpio_put(scl_gpio, true);
up_udelay(10);
rp23xx_gpio_put(sda_gpio, true);
up_udelay(10);
ret = OK;
out:
/* Revert the GPIO configuration. */
rp23xx_gpio_set_function(sda_gpio, RP23XX_GPIO_FUNC_I2C);
rp23xx_gpio_set_function(scl_gpio, RP23XX_GPIO_FUNC_I2C);
/* Reset I2C subsystem */
setbits_reg32(subsys, RP23XX_RESETS_RESET);
clrbits_reg32(subsys, RP23XX_RESETS_RESET);
while ((getreg32(RP23XX_RESETS_RESET_DONE) & subsys) == 0)
;
/* Re-init the port */
rp23xx_i2c_disable(priv);
rp23xx_i2c_init(priv);
/* Restore the frequency */
frequency = priv->frequency;
priv->frequency = 0;
rp23xx_i2c_setfrequency(priv, frequency);
out_without_reinit:
/* Release the port for reuse by other clients */
nxmutex_unlock(&priv->lock);
return ret;
}
#endif /* CONFIG_I2C_RESET */
static inline uint32_t i2c_reg_read(struct rp23xx_i2cdev_s *priv,
uint32_t offset)
{
return getreg32(priv->base + offset);
}
static inline void i2c_reg_write(struct rp23xx_i2cdev_s *priv,
uint32_t offset, uint32_t val)
{
putreg32(val, priv->base + offset);
}
static inline void i2c_reg_rmw(struct rp23xx_i2cdev_s *priv, uint32_t offset,
uint32_t val, uint32_t mask)
{
modbits_reg32(val, mask, priv->base + offset);
}
static int rp23xx_i2c_disable(struct rp23xx_i2cdev_s *priv)
{
int retry = 25000;
uint32_t stat;
/* disable all interrupt */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET, 0x0);
/* clear all interrupt status */
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_INTR_OFFSET);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_ENABLE_OFFSET, 0);
do
{
stat = i2c_reg_read(priv, RP23XX_RV_I2C_IC_ENABLE_STATUS_OFFSET);
}
while (--retry && (stat & RP23XX_RV_I2C_IC_ENABLE_STATUS_IC_EN));
if (!retry)
{
i2cerr("i2c wait timeout.\n");
return -EBUSY;
}
/* clear all interrupt status again */
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_INTR_OFFSET);
return 0;
}
static void rp23xx_i2c_init(struct rp23xx_i2cdev_s *priv)
{
i2c_reg_write(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET, 0x00);
i2c_reg_read(priv, RP23XX_RV_I2C_IC_CLR_INTR_OFFSET);
/* set threshold level of the Rx/Tx FIFO */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_RX_TL_OFFSET, 0xff);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_TX_TL_OFFSET, 0);
/* set hold time for margin */
i2c_reg_write(priv, RP23XX_RV_I2C_IC_SDA_HOLD_OFFSET, 1);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_CON_OFFSET,
(RP23XX_RV_I2C_IC_CON_IC_RESTART_EN |
RP23XX_RV_I2C_IC_CON_IC_SLAVE_DISABLE |
RP23XX_RV_I2C_IC_CON_MASTER_MODE |
RP23XX_RV_I2C_IC_CON_TX_EMPTY_CTRL));
}
static void rp23xx_i2c_enable(struct rp23xx_i2cdev_s *priv)
{
i2c_reg_write(priv, RP23XX_RV_I2C_IC_INTR_MASK_OFFSET, I2C_INTR_ENABLE);
i2c_reg_write(priv, RP23XX_RV_I2C_IC_ENABLE_OFFSET, 1);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2cbus_initialize
*
* Description:
* Initialise an I2C device
*
****************************************************************************/
struct i2c_master_s *rp23xx_i2cbus_initialize(int port)
{
struct rp23xx_i2cdev_s *priv;
#ifdef CONFIG_RP23XX_RV_I2C0
if (port == 0)
{
priv = &g_i2c0dev;
priv->dev.ops = &rp23xx_i2c_ops;
}
else
#endif
#ifdef CONFIG_RP23XX_RV_I2C1
if (port == 1)
{
priv = &g_i2c1dev;
priv->dev.ops = &rp23xx_i2c_ops;
}
else
#endif
{
i2cerr("I2C Only support 0,1\n");
return NULL;
}
nxmutex_lock(&priv->lock);
/* Test if already initialized or not */
if (1 < ++priv->refs)
{
nxmutex_unlock(&priv->lock);
return &priv->dev;
}
priv->port = port;
priv->frequency = 0;
priv->base_freq = BOARD_PERI_FREQ;
rp23xx_i2c_disable(priv);
rp23xx_i2c_init(priv);
rp23xx_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, rp23xx_i2c_interrupt, priv);
/* Enable Interrupt Handler */
up_enable_irq(priv->irqid);
nxmutex_unlock(&priv->lock);
return &priv->dev;
}
/****************************************************************************
* Name: rp23xx_i2cbus_uninitialize
*
* Description:
* Uninitialise an I2C device
*
****************************************************************************/
int rp23xx_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)dev;
/* Decrement reference count and check for underflow */
if (priv->refs == 0)
{
return ERROR;
}
nxmutex_lock(&priv->lock);
if (--priv->refs)
{
nxmutex_unlock(&priv->lock);
return OK;
}
rp23xx_i2c_disable(priv);
up_disable_irq(priv->irqid);
irq_detach(priv->irqid);
wd_cancel(&priv->timeout);
nxmutex_unlock(&priv->lock);
return OK;
}
#endif /* CONFIG_RP23XX_RV_I2C */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2c.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2C_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "hardware/rp23xx_i2c.h"
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameter:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2c_master_s *rp23xx_i2cbus_initialize(int port);
/****************************************************************************
* Name: rp23xx_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the rp23xx_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int rp23xx_i2cbus_uninitialize(struct i2c_master_s *dev);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2C_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2c_slave.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <nuttx/i2c/i2c_slave.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <arch/chip/i2c_slave.h>
#include <arch/board/board.h>
#include "chip.h"
#include "riscv_internal.h"
#include "rp23xx_i2c.h"
#include "hardware/rp23xx_i2c.h"
#include "hardware/rp23xx_resets.h"
#include "rp23xx_gpio.h"
#ifdef CONFIG_RP23XX_RV_I2C_SLAVE
#define FIFO_LENGTH 16
#define TX_BUF_LEN 8
#define RX_BUF_LEN 8
/****************************************************************************
* Private Types
****************************************************************************/
typedef struct rp23xx_i2c_slave_s
{
struct i2c_slave_s dev; /* Generic I2C device */
int8_t controller; /* I2C controller number */
int error; /* Error value */
uint8_t *rx_buffer;
uint8_t *rx_buf_ptr;
uint8_t *rx_buf_end;
const uint8_t *tx_buffer;
const uint8_t *tx_buf_ptr;
const uint8_t *tx_buf_end;
i2c_slave_callback_t *callback; /* Callback function */
void *callback_arg; /* Argument for callback */
} rp23xx_i2c_slave_t;
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int i2c_interrupt(int irq,
void *context,
void *arg);
static int my_set_own_address(struct i2c_slave_s *dev,
int address,
int nbits);
static int my_write(struct i2c_slave_s *dev,
const uint8_t *buffer,
int length);
static int my_read(struct i2c_slave_s *dev,
uint8_t *buffer,
int length);
static int my_register_callback(struct i2c_slave_s *dev,
i2c_slave_callback_t *callback,
void *arg);
static void enable_i2c_slave(struct i2c_slave_s *dev);
/****************************************************************************
* Private Data
****************************************************************************/
struct i2c_slaveops_s i2c_slaveops =
{
.setownaddress = my_set_own_address,
.write = my_write,
.read = my_read,
.registercallback = my_register_callback,
};
#ifdef CONFIG_RP23XX_RV_I2C0_SLAVE
rp23xx_i2c_slave_t i2c0_slave_dev =
{
.dev.ops = &i2c_slaveops, /* Slave operations */
.controller = 0, /* I2C controller number */
};
#endif
#ifdef CONFIG_RP23XX_RV_I2C1_SLAVE
rp23xx_i2c_slave_t i2c1_slave_dev =
{
.dev.ops = &i2c_slaveops, /* Slave operations */
.controller = 1, /* I2C controller number */
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: i2c_interrupt
*
* Description:
* The I2C Interrupt Handler
*
****************************************************************************/
static int i2c_interrupt(int irq, void *context, void *arg)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *)arg;
uint32_t data_cmd;
uint32_t state;
int length;
state = getreg32(RP23XX_RV_I2C_IC_INTR_STAT(priv->controller));
/* -- We need to transmit data (Read Request) -- */
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RD_REQ)
{
length = priv->tx_buf_end - priv->tx_buf_ptr;
if (length > 0)
{
while (priv->tx_buf_ptr < priv->tx_buf_end
&& getreg32(RP23XX_RV_I2C_IC_TXFLR(priv->controller))
< FIFO_LENGTH)
{
putreg32(*priv->tx_buf_ptr++,
RP23XX_RV_I2C_IC_DATA_CMD(priv->controller));
}
if (priv->callback != NULL)
{
priv->callback(priv, I2CS_TX_COMPLETE, length);
}
}
else
{
putreg32(0, RP23XX_RV_I2C_IC_DATA_CMD(priv->controller));
}
getreg32(RP23XX_RV_I2C_IC_CLR_RD_REQ(priv->controller));
}
/* -- We are receiving data (Write Request) -- */
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL)
{
while (getreg32(RP23XX_RV_I2C_IC_RXFLR(priv->controller)) > 0)
{
data_cmd = getreg32(RP23XX_RV_I2C_IC_DATA_CMD(priv->controller));
if (data_cmd & RP23XX_RV_I2C_IC_DATA_CMD_FIRST_DATA_BYTE)
{
priv->rx_buf_ptr = priv->rx_buffer;
}
if (priv->rx_buf_ptr < priv->rx_buf_end)
{
*priv->rx_buf_ptr++ = (uint8_t) data_cmd;
}
}
}
/* -- Restart -- */
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RESTART_DET)
{
if (priv->callback != NULL && priv->rx_buf_ptr > priv->rx_buffer)
{
priv->callback(priv, I2CS_RX_COMPLETE,
priv->rx_buf_ptr - priv->rx_buffer);
priv->rx_buf_ptr = priv->rx_buffer;
}
getreg32(RP23XX_RV_I2C_IC_CLR_RESTART_DET(priv->controller));
}
/* -- End of transfer -- */
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET)
{
if (priv->callback != NULL && priv->rx_buf_ptr > priv->rx_buffer)
{
priv->callback(priv, I2CS_RX_COMPLETE,
priv->rx_buf_ptr - priv->rx_buffer);
priv->rx_buf_ptr = priv->rx_buffer;
}
getreg32(RP23XX_RV_I2C_IC_CLR_STOP_DET(priv->controller));
}
/* -- Transmit Abort -- */
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT)
{
getreg32(RP23XX_RV_I2C_IC_CLR_TX_ABRT(priv->controller));
priv->error = -ENODEV;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_OVER)
{
getreg32(RP23XX_RV_I2C_IC_CLR_TX_OVER(priv->controller));
priv->error = -EIO;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_OVER)
{
getreg32(RP23XX_RV_I2C_IC_CLR_RX_OVER(priv->controller));
priv->error = -EIO;
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_UNDER)
{
getreg32(RP23XX_RV_I2C_IC_CLR_RX_UNDER(priv->controller));
priv->error = -EIO;
}
#ifdef NEEDED_FOR_MASTER_MODE_
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY)
{
/* TX_EMPTY is automatically cleared by hardware
* when the buffer level goes above the threshold.
*/
modbits_reg32(RP23XX_RV_I2C_IC_INTR_MASK(priv->controller),
0,
RP23XX_RV_I2C_IC_INTR_MASK_M_TX_EMPTY);
}
if (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL)
{
/* RX_FULL is automatically cleared by hardware
* when the buffer level goes below the threshold.
*/
modbits_reg32(RP23XX_RV_I2C_IC_INTR_MASK(priv->controller),
0,
RP23XX_RV_I2C_IC_INTR_MASK_M_RX_FULL);
rp23xx_i2c_drainrxfifo(priv);
}
if ((priv->error) || (state & RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY)
|| (state & RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL))
{
/* Failure of wd_cancel() means that the timer expired.
* In this case, nxsem_post() has already been called.
* Therefore, call nxsem_post() only when wd_cancel() succeeds.
*/
ret = wd_cancel(&priv->timeout);
if (ret == OK)
{
nxsem_post(&priv->wait);
}
}
#endif
return OK;
}
/****************************************************************************
* Name: enable_i2c_slave
*
* Description:
* Enable the I2C device as a slave and start handing I2C interrupts.
*
****************************************************************************/
static void enable_i2c_slave(struct i2c_slave_s *dev)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *) dev;
irqstate_t flags;
flags = enter_critical_section();
uint32_t intr_mask = RP23XX_RV_I2C_IC_INTR_STAT_R_RD_REQ
| RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL
| RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET
| RP23XX_RV_I2C_IC_INTR_STAT_R_RESTART_DET
| RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT;
putreg32(0, RP23XX_RV_I2C_IC_ENABLE(priv->controller));
putreg32(intr_mask, RP23XX_RV_I2C_IC_INTR_MASK(priv->controller));
putreg32(0, RP23XX_RV_I2C_IC_ENABLE(priv->controller));
if (priv->controller == 0)
{
irq_attach(RP23XX_RV_I2C0_IRQ, i2c_interrupt, dev);
up_enable_irq(RP23XX_RV_I2C0_IRQ);
}
else
{
irq_attach(RP23XX_RV_I2C1_IRQ, i2c_interrupt, dev);
up_enable_irq(RP23XX_RV_I2C1_IRQ);
}
putreg32(RP23XX_RV_I2C_IC_ENABLE_ENABLE,
RP23XX_RV_I2C_IC_ENABLE(priv->controller));
leave_critical_section(flags);
}
/****************************************************************************
* Name: my_set_own_address
*
* Description:
* Called to set the address listened to, and enable I2C as a slave device.
*
****************************************************************************/
static int my_set_own_address(struct i2c_slave_s *dev,
int address,
int nbits)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *) dev;
uint32_t con = RP23XX_RV_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
| RP23XX_RV_I2C_IC_CON_SPEED_FAST;
irqstate_t flags;
flags = enter_critical_section();
putreg32(address, RP23XX_RV_I2C_IC_SAR(priv->controller));
if (nbits == 10)
{
con |= RP23XX_RV_I2C_IC_CON_IC_10BITADDR_SLAVE;
}
putreg32(con, RP23XX_RV_I2C_IC_CON(priv->controller));
enable_i2c_slave(dev);
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: my_write
*
* Description:
* Called to set the data to be read on the next I2C read transaction.
*
****************************************************************************/
static int my_write(struct i2c_slave_s *dev,
const uint8_t *buffer,
int length)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *) dev;
irqstate_t flags;
flags = enter_critical_section();
priv->tx_buffer = buffer;
priv->tx_buf_ptr = buffer;
priv->tx_buf_end = priv->tx_buffer + length;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: my_read
*
* Description:
* Called to register a buffer to receive data from the next I2C write
* transaction.
*
****************************************************************************/
static int my_read(struct i2c_slave_s *dev,
uint8_t *buffer,
int length)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *) dev;
irqstate_t flags;
flags = enter_critical_section();
priv->rx_buffer = buffer;
priv->rx_buf_ptr = buffer;
priv->rx_buf_end = priv->rx_buffer + length;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: my_register_callback
*
* Description:
* Called to register a callback function that will be called when
* data becomes available due to an I2C write transaction.
*
****************************************************************************/
static int my_register_callback(struct i2c_slave_s *dev,
i2c_slave_callback_t *callback,
void *arg)
{
rp23xx_i2c_slave_t *priv = (rp23xx_i2c_slave_t *) dev;
irqstate_t flags;
flags = enter_critical_section();
priv->callback = callback;
priv->callback_arg = arg;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2c0_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Input Parameters:
* sda_pin - The GPIO pin for the SDA line.
* scl_pin - The GPIO pin for the SCL line.
* address - The slave address to listen to.
* ten_bin - Set true for 10-bit I2C addressing.
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C0_SLAVE
struct i2c_slave_s * rp23xx_i2c0_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback)
{
rp23xx_i2c_slave_t *priv = &i2c0_slave_dev;
rp23xx_gpio_set_function(CONFIG_RP23XX_RV_I2C0_SDA_GPIO,
RP23XX_GPIO_FUNC_I2C);
rp23xx_gpio_set_pulls(CONFIG_RP23XX_RV_I2C0_SDA_GPIO, true, false);
rp23xx_gpio_set_function(CONFIG_RP23XX_RV_I2C0_SCL_GPIO,
RP23XX_GPIO_FUNC_I2C);
rp23xx_gpio_set_pulls(CONFIG_RP23XX_RV_I2C0_SCL_GPIO, true, false);
priv->rx_buffer = rx_buffer;
priv->rx_buf_ptr = rx_buffer;
priv->rx_buf_end = priv->rx_buffer + rx_buffer_len;
if (callback != NULL)
{
my_register_callback(&(priv->dev), callback, priv);
}
#ifdef CONFIG_RP23XX_RV_I2C0_SLAVE_10BIT
my_set_own_address(&(priv->dev),
CONFIG_RP23XX_RV_I2C0_SLAVE_ADDRESS,
10);
#else
my_set_own_address(&(priv->dev),
CONFIG_RP23XX_RV_I2C0_SLAVE_ADDRESS,
7);
#endif
return &(priv->dev);
}
#endif /* CONFIG_RP23XX_RV_I2C0_SLAVE */
/****************************************************************************
* Name: rp23xx_i2c1_slave_initialize
*
* Description:
* Initialize I2C controller one for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Input Parameters:
* sda_pin - The GPIO pin for the SDA line.
* scl_pin - The GPIO pin for the SCL line.
* address - The slave address to listen to.
* ten_bin - Set true for 10-bit I2C addressing.
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C1_SLAVE
struct i2c_slave_s * rp23xx_i2c1_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback)
{
rp23xx_i2c_slave_t *priv = &i2c1_slave_dev;
rp23xx_gpio_set_function(CONFIG_RP23XX_RV_I2C1_SDA_GPIO,
RP23XX_GPIO_FUNC_I2C);
rp23xx_gpio_set_pulls(CONFIG_RP23XX_RV_I2C1_SDA_GPIO, true, false);
rp23xx_gpio_set_function(CONFIG_RP23XX_RV_I2C1_SCL_GPIO,
RP23XX_GPIO_FUNC_I2C);
rp23xx_gpio_set_pulls(CONFIG_RP23XX_RV_I2C1_SCL_GPIO, true, false);
priv->rx_buffer = rx_buffer;
priv->rx_buf_ptr = rx_buffer;
priv->rx_buf_end = priv->rx_buffer + rx_buffer_len;
if (callback != NULL)
{
my_register_callback(&(priv->dev), callback, priv);
}
#ifdef CONFIG_RP23XX_RV_I2C1_SLAVE_10BIT
my_set_own_address(&(priv->dev),
CONFIG_RP23XX_RV_I2C1_SLAVE_ADDRESS,
10);
#else
my_set_own_address(&(priv->dev),
CONFIG_RP23XX_RV_I2C1_SLAVE_ADDRESS,
7);
#endif
return &(priv->dev);
}
#endif /* CONFIG_RP23XX_RV_I2C1_SLAVE */
#endif /* CONFIG_RP23XX_RV_I2C_SLAVE */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2s.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/audio/i2s.h>
#include "chip.h"
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2sbus_initialize
*
* Description:
* Initialize the selected I2S port
*
* Input Parameters:
* Port number (for hardware that has multiple I2S interfaces)
*
* Returned Value:
* Valid I2S device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2s_dev_s *rp23xx_i2sbus_initialize(int port);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2s_pio.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/board/board.h>
#include "rp23xx_i2s_pio.h"
#include "rp23xx_pio.h"
#include "rp23xx_pio_instructions.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_RP23XX_RV_I2S_PIO
#define CONFIG_RP23XX_RV_I2S_PIO 0
#endif
#ifndef CONFIG_RP23XX_RV_I2S_PIO_SM
#define CONFIG_RP23XX_RV_I2S_PIO_SM 0
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct rp23xx_i2s_pio_config
{
const rp23xx_pio_program_t program;
uint32_t entry;
uint32_t wrap_target;
uint32_t wrap;
bool autopull;
uint32_t clocks;
};
/****************************************************************************
* Private Data
****************************************************************************/
/* PIO program for 16bit stereo I2S transfer */
static const uint16_t pio_program_i2s_16s[] =
{
/* .wrap_target */
0x6870, /* 0: out null, 16 side 1 */
0x6001, /* 1: out pins, 1 side 0 */
0xe82d, /* 2: set x, 13 side 1 */
0x6001, /* 3: out pins, 1 side 0 */
0x0843, /* 4: jmp x--, 3 side 1 */
0x7001, /* 5: out pins, 1 side 2 */
0x7870, /* 6: out null, 16 side 3 */
0x7001, /* 7: out pins, 1 side 2 */
0xf82d, /* 8: set x, 13 side 3 */
0x7001, /* 9: out pins, 1 side 2 */
0x1849, /* 10: jmp x--, 9 side 3 */
0x6001, /* 11: out pins, 1 side 0 */
/* .wrap */
};
/* PIO program for 16bit mono I2S transfer */
static const uint16_t pio_program_i2s_16m[] =
{
/* .wrap_target */
0x80a0, /* 0: pull block side 0 */
0x6870, /* 1: out null, 16 side 1 */
0xa847, /* 2: mov y, osr side 1 */
0x6101, /* 3: out pins, 1 side 0 [1] */
0xe92d, /* 4: set x, 13 side 1 [1] */
0x6101, /* 5: out pins, 1 side 0 [1] */
0x0945, /* 6: jmp x--, 5 side 1 [1] */
0x7101, /* 7: out pins, 1 side 2 [1] */
0xb9e2, /* 8: mov osr, y side 3 [1] */
0x7101, /* 9: out pins, 1 side 2 [1] */
0xf92d, /* 10: set x, 13 side 3 [1] */
0x7101, /* 11: out pins, 1 side 2 [1] */
0x194b, /* 12: jmp x--, 11 side 3 [1] */
0x6001, /* 13: out pins, 1 side 0 */
/* .wrap */
};
/* PIO program for 8bit stereo I2S transfer */
static const uint16_t pio_program_i2s_8s[] =
{
/* .wrap_target */
0x80a0, /* 0: pull block side 0 */
0x6078, /* 1: out null, 24 side 0 */
0xa9ef, /* 2: mov osr, !osr side 1 [1] */
0x6101, /* 3: out pins, 1 side 0 [1] */
0xa8ef, /* 4: mov osr, !osr side 1 */
0xe826, /* 5: set x, 6 side 1 */
0x6101, /* 6: out pins, 1 side 0 [1] */
0x0946, /* 7: jmp x--, 6 side 1 [1] */
0xe100, /* 8: set pins, 0 side 0 [1] */
0xe925, /* 9: set x, 5 side 1 [1] */
0xa142, /* 10: nop side 0 [1] */
0x094a, /* 11: jmp x--, 10 side 1 [1] */
0x90a0, /* 12: pull block side 2 */
0x7078, /* 13: out null, 24 side 2 */
0xb9ef, /* 14: mov osr, !osr side 3 [1] */
0x7101, /* 15: out pins, 1 side 2 [1] */
0xb8ef, /* 16: mov osr, !osr side 3 */
0xf826, /* 17: set x, 6 side 3 */
0x7101, /* 18: out pins, 1 side 2 [1] */
0x1952, /* 19: jmp x--, 18 side 3 [1] */
0xf100, /* 20: set pins, 0 side 2 [1] */
0xf925, /* 21: set x, 5 side 3 [1] */
0xb142, /* 22: nop side 2 [1] */
0x1956, /* 23: jmp x--, 22 side 3 [1] */
/* .wrap */
};
/* PIO program for 8bit mono I2S transfer */
static const uint16_t pio_program_i2s_8m[] =
{
/* .wrap_target */
0x80a0, /* 0: pull block side 0 */
0x6078, /* 1: out null, 24 side 0 */
0xa8ef, /* 2: mov osr, !osr side 1 */
0xa847, /* 3: mov y, osr side 1 */
0x6101, /* 4: out pins, 1 side 0 [1] */
0xa8ef, /* 5: mov osr, !osr side 1 */
0xe826, /* 6: set x, 6 side 1 */
0x6101, /* 7: out pins, 1 side 0 [1] */
0x0947, /* 8: jmp x--, 7 side 1 [1] */
0xe100, /* 9: set pins, 0 side 0 [1] */
0xe925, /* 10: set x, 5 side 1 [1] */
0xa142, /* 11: nop side 0 [1] */
0x094b, /* 12: jmp x--, 11 side 1 [1] */
0xb142, /* 13: nop side 2 [1] */
0xb9e2, /* 14: mov osr, y side 3 [1] */
0x7101, /* 15: out pins, 1 side 2 [1] */
0xb8ef, /* 16: mov osr, !osr side 3 */
0xf826, /* 17: set x, 6 side 3 */
0x7101, /* 18: out pins, 1 side 2 [1] */
0x1952, /* 19: jmp x--, 18 side 3 [1] */
0xf100, /* 20: set pins, 0 side 2 [1] */
0xf925, /* 21: set x, 5 side 3 [1] */
0xb142, /* 22: nop side 2 [1] */
0x1956, /* 23: jmp x--, 22 side 3 [1] */
/* .wrap */
};
/* PIO configuration table */
static const struct rp23xx_i2s_pio_config g_pio_i2s_configs[] =
{
[RP23XX_RV_I2S_PIO_16BIT_STEREO] =
{
{
pio_program_i2s_16s,
sizeof(pio_program_i2s_16s) / sizeof(uint16_t),
-1
},
0, 0, 11,
true, 16 * 2 * 2
},
[RP23XX_RV_I2S_PIO_16BIT_MONO] =
{
{
pio_program_i2s_16m,
sizeof(pio_program_i2s_16m) / sizeof(uint16_t),
-1
},
0, 0, 13,
false, 16 * 2 * 4
},
[RP23XX_RV_I2S_PIO_8BIT_STEREO] =
{
{
pio_program_i2s_8s,
sizeof(pio_program_i2s_8s) / sizeof(uint16_t),
-1
},
0, 0, 23,
false, 16 * 2 * 4
},
[RP23XX_RV_I2S_PIO_8BIT_MONO] =
{
{
pio_program_i2s_8m,
sizeof(pio_program_i2s_8m) / sizeof(uint16_t),
-1
},
0, 0, 23,
false, 16 * 2 * 4
}
};
static const uint32_t g_i2s_pio = CONFIG_RP23XX_RV_I2S_PIO;
static const uint32_t g_i2s_pio_sm = CONFIG_RP23XX_RV_I2S_PIO_SM;
/* PIO I2S status */
static int g_pio_current_mode = -1;
static uint32_t g_pio_current_samplerate;
static uint32_t g_pio_current_offset;
/****************************************************************************
* Private Functions
****************************************************************************/
static float get_clkdiv(int mode, uint32_t samplerate)
{
float div = (float)BOARD_SYS_FREQ /
(samplerate * g_pio_i2s_configs[mode].clocks);
return div;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2s_pio_configure
*
* Description:
* Configure RP23XX PIO for I2S
*
****************************************************************************/
int rp23xx_i2s_pio_configure(int mode, uint32_t samplerate)
{
const struct rp23xx_i2s_pio_config *conf;
rp23xx_pio_sm_config sm_config;
uint32_t data_pin = CONFIG_RP23XX_RV_I2S_DATA;
uint32_t clock_pin_base = CONFIG_RP23XX_RV_I2S_CLOCK;
uint32_t pin_mask = (1u << data_pin) | (3u << clock_pin_base);
/* Check parameters */
if (mode < 0 || mode >= RP23XX_RV_I2S_PIO_MAX_MODE ||
samplerate == 0)
{
return -1;
}
if (mode == g_pio_current_mode)
{
if (samplerate == g_pio_current_samplerate)
{
return 0;
}
else
{
/* Only changing the sampling rate */
rp23xx_pio_sm_set_clkdiv(g_i2s_pio, g_i2s_pio_sm,
get_clkdiv(mode, samplerate));
rp23xx_pio_sm_clkdiv_restart(g_i2s_pio, g_i2s_pio_sm);
return 0;
}
}
if (g_pio_current_mode < 0)
{
/* Claim to use PIO state machine for I2S */
rp23xx_pio_sm_claim(g_i2s_pio, g_i2s_pio_sm);
}
else
{
/* Remove existing PIO program to change the I2S mode */
rp23xx_pio_remove_program(CONFIG_RP23XX_RV_I2S_PIO,
&g_pio_i2s_configs[g_pio_current_mode].program,
g_pio_current_offset);
}
/* Program the PIO */
conf = &g_pio_i2s_configs[mode];
g_pio_current_offset = rp23xx_pio_add_program(CONFIG_RP23XX_RV_I2S_PIO,
&conf->program);
g_pio_current_mode = mode;
/* Configure the state machine */
sm_config = rp23xx_pio_get_default_sm_config();
rp23xx_sm_config_set_wrap(&sm_config,
g_pio_current_offset + conf->wrap_target,
g_pio_current_offset + conf->wrap);
rp23xx_sm_config_set_sideset(&sm_config, 2, false, false);
rp23xx_sm_config_set_out_pins(&sm_config, data_pin, 1);
rp23xx_sm_config_set_sideset_pins(&sm_config, clock_pin_base);
rp23xx_sm_config_set_out_shift(&sm_config, false, conf->autopull, 32);
rp23xx_sm_config_set_set_pins(&sm_config, data_pin, 1);
rp23xx_sm_config_set_clkdiv(&sm_config, get_clkdiv(mode, samplerate));
rp23xx_pio_sm_init(g_i2s_pio, g_i2s_pio_sm,
g_pio_current_offset, &sm_config);
rp23xx_pio_sm_set_pindirs_with_mask(g_i2s_pio, g_i2s_pio_sm,
pin_mask, pin_mask);
rp23xx_pio_sm_set_pins(g_i2s_pio, g_i2s_pio_sm, 1); /* clear pins */
rp23xx_pio_sm_exec(g_i2s_pio, g_i2s_pio_sm,
pio_encode_jmp(g_pio_current_offset + conf->entry));
return 0;
}
/****************************************************************************
* Name: rp23xx_i2s_pio_enable
*
* Description:
* Set enable I2S transfer
*
****************************************************************************/
void rp23xx_i2s_pio_enable(bool enable)
{
rp23xx_pio_sm_set_enabled(g_i2s_pio, g_i2s_pio_sm, enable);
}
/****************************************************************************
* Name: rp23xx_i2s_pio_getdmaaddr
*
* Description:
* Get DMA peripheral address for I2S transfer
*
****************************************************************************/
uintptr_t rp23xx_i2s_pio_getdmaaddr(void)
{
return RP23XX_PIO_TXF(g_i2s_pio, g_i2s_pio_sm);
}
/****************************************************************************
* Name: rp23xx_i2s_pio_getdmaaddr
*
* Description:
* Get DMA peripheral address for I2S transfer
*
****************************************************************************/
uint8_t rp23xx_i2s_pio_getdreq(void)
{
return RP23XX_DMA_DREQ_PIO0_TX0 + g_i2s_pio_sm + g_i2s_pio * 8;
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_i2s_pio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_PIO_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_RV_I2S_PIO_16BIT_STEREO 0
#define RP23XX_RV_I2S_PIO_16BIT_MONO 1
#define RP23XX_RV_I2S_PIO_8BIT_STEREO 2
#define RP23XX_RV_I2S_PIO_8BIT_MONO 3
#define RP23XX_RV_I2S_PIO_MAX_MODE 4
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2s_pio_configure
*
* Description:
* Configure RP23XX PIO for I2S
*
****************************************************************************/
int rp23xx_i2s_pio_configure(int mode, uint32_t samplerate);
/****************************************************************************
* Name: rp23xx_i2s_pio_enable
*
* Description:
* Set enable I2S transfer
*
****************************************************************************/
void rp23xx_i2s_pio_enable(bool enable);
/****************************************************************************
* Name: rp23xx_i2s_pio_getdmaaddr
*
* Description:
* Get DMA peripheral address for I2S transfer
*
****************************************************************************/
uintptr_t rp23xx_i2s_pio_getdmaaddr(void);
/****************************************************************************
* Name: rp23xx_i2s_pio_getdmaaddr
*
* Description:
* Get DREQ number for I2S transfer
*
****************************************************************************/
uint8_t rp23xx_i2s_pio_getdreq(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2S_PIO_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_idle.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/irq.h>
#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Sleep until an interrupt occurs to save power */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_irq.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/chip/irq.h>
#include "hardware/rp23xx_hazard3.h"
#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Disable Machine interrupts */
up_irq_save();
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15);
riscv_stack_color(g_intstackalloc, intstack_size);
#endif
/* Attach the common interrupt handler */
riscv_exception_attach();
for (uint8_t i = 0; i < RP23XX_IRQ_NEXTINT; ++i)
{
uint8_t hardware_priority = (uint8_t)((0x80 >> 4) ^ 0xf);
hazard3_irqarray_clear(RVCSR_MEIPRA_OFFSET, i / 4,
0xfu << (4 * (i % 4)));
hazard3_irqarray_set(RVCSR_MEIPRA_OFFSET, i / 4,
hardware_priority << (4 * (i % 4)));
}
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
void up_enable_irq(int irq)
{
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
SET_CSR(CSR_MIE, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & set machine timer interrupt enable in mie */
SET_CSR(CSR_MIE, MIE_MTIE);
}
else if (irq >= RP23XX_IRQ_EXTINT)
{
int n = (irq - RP23XX_IRQ_EXTINT) / 32;
int bit_pos = (irq - RP23XX_IRQ_EXTINT) % 32;
int mask = 1u << bit_pos;
hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu);
hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16);
hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu);
hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16);
}
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
if (irq == RISCV_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
CLEAR_CSR(CSR_MIE, MIE_MSIE);
}
else if (irq == RISCV_IRQ_MTIMER)
{
/* Read mstatus & clear machine timer interrupt enable in mie */
CLEAR_CSR(CSR_MIE, MIE_MTIE);
}
else if (irq >= RP23XX_IRQ_EXTINT)
{
int n = (irq - RP23XX_IRQ_EXTINT) / 32;
int bit_pos = (irq - RP23XX_IRQ_EXTINT) % 32;
int mask = 1u << bit_pos;
hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu);
hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16);
}
}
/****************************************************************************
* Name: riscv_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void riscv_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_irq_enable
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
irqstate_t up_irq_enable(void)
{
uint32_t oldstat;
/* Enable MEIE (machine external interrupt enable) */
SET_CSR(CSR_MIE, MIE_MEIE);
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE);
return oldstat;
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_irq_dispatch.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "riscv_internal.h"
#include "rp23xx_gpio.h"
#include "hardware/rp23xx_hazard3.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
static void *riscv_dispatch_irq_ext(uintreg_t irq, uintreg_t *regs)
{
uint32_t meinext;
uint32_t extirq;
uint32_t meicontext;
meicontext = READ_AND_SET_CSR(RVCSR_MEICONTEXT_OFFSET,
RVCSR_MEICONTEXT_CLEARTS_BITS);
while (1)
{
meinext = READ_AND_SET_CSR(RVCSR_MEINEXT_OFFSET,
RVCSR_MEINEXT_UPDATE_BITS);
if (meinext & RVCSR_MEINEXT_NOIRQ_BITS)
{
break;
}
extirq = (meinext & RVCSR_MEINEXT_IRQ_BITS) >> 2;
SET_CSR(CSR_MSTATUS, MSTATUS_MIE);
regs = riscv_doirq(RP23XX_IRQ_EXTINT + extirq, regs);
CLEAR_CSR(CSR_MSTATUS, MSTATUS_MIE);
}
#if 0
uint32_t ppreempt = ((meicontext >> 28) & 0xf) << 24;
uint32_t preempt = ((meicontext >> 24) & 0xf) << 16;
uint32_t parentirq = meicontext & 0xc;
WRITE_CSR(RVCSR_MEICONTEXT_OFFSET, ppreempt | preempt | parentirq);
#endif
WRITE_CSR(RVCSR_MEICONTEXT_OFFSET, meicontext);
return regs;
}
static void *riscv_dispatch_async_irq(uintreg_t irq, uintreg_t *regs)
{
irq += RISCV_IRQ_ASYNC;
if (irq == RISCV_IRQ_EXT)
{
regs = riscv_dispatch_irq_ext(irq, regs);
}
else
{
regs = riscv_doirq(irq, regs);
}
return regs;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* riscv_dispatch_irq
****************************************************************************/
void *riscv_dispatch_irq(uintreg_t vector, uintreg_t *regs)
{
int irq = vector & (~RISCV_IRQ_BIT);
if ((vector & RISCV_IRQ_BIT) != 0)
{
regs = riscv_dispatch_async_irq(irq, regs);
}
else
{
regs = riscv_doirq(irq, regs);
}
return regs;
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pio.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/spinlock.h>
#include <arch/board/board.h>
#include "hardware/rp23xx_pio.h"
#include "rp23xx_pio.h"
#include "rp23xx_pio_instructions.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_SMP
#define hw_claim_lock() spin_lock_irqsave(&pio_lock)
#define hw_claim_unlock(save) spin_unlock_irqrestore(&pio_lock, save)
#else
#define hw_claim_lock() up_irq_save()
#define hw_claim_unlock(save) up_irq_restore(save)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_SMP
static spinlock_t pio_lock;
#endif
static uint8_t claimed;
static uint32_t _used_instruction_space[2];
/****************************************************************************
* Private Functions
****************************************************************************/
static void hw_claim_or_assert(uint8_t *bits, uint32_t bit_index,
const char *message)
{
uint32_t save = hw_claim_lock();
if (bits[bit_index >> 3u] & (1u << (bit_index & 7u)))
{
DEBUGPANIC();
}
else
{
bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
}
hw_claim_unlock(save);
}
static int hw_claim_unused_from_range(uint8_t *bits, bool required,
uint32_t bit_lsb, uint32_t bit_msb,
const char *message)
{
/* don't bother check lsb / msb order as if wrong, then it'll fail anyway */
uint32_t save = hw_claim_lock();
int found_bit = -1;
for (uint32_t bit = bit_lsb; bit <= bit_msb; bit++)
{
if (!(bits[bit >> 3u] & (1u << (bit & 7u))))
{
bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
found_bit = (int)bit;
break;
}
}
hw_claim_unlock(save);
if (found_bit < 0 && required)
{
DEBUGPANIC();
}
return found_bit;
}
static void hw_claim_clear(uint8_t *bits, uint32_t bit_index)
{
uint32_t save = hw_claim_lock();
ASSERT(bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
hw_claim_unlock(save);
}
static int _pio_find_offset_for_program(uint32_t pio,
const rp23xx_pio_program_t *program)
{
ASSERT(program->length < PIO_INSTRUCTION_COUNT);
uint32_t used_mask = _used_instruction_space[rp23xx_pio_get_index(pio)];
uint32_t program_mask = (1u << program->length) - 1;
if (program->origin >= 0)
{
if (program->origin > 32 - program->length)
{
return -1;
}
return used_mask & (program_mask << program->origin) ?
-1 : program->origin;
}
else
{
/* work down from the top always */
for (int i = 32 - program->length; i >= 0; i--)
{
if (!(used_mask & (program_mask << (uint32_t) i)))
{
return i;
}
}
return -1;
}
}
static bool _pio_can_add_program_at_offset(uint32_t pio,
const rp23xx_pio_program_t *program,
uint32_t offset)
{
valid_params_if(PIO, offset < PIO_INSTRUCTION_COUNT);
valid_params_if(PIO, offset + program->length <= PIO_INSTRUCTION_COUNT);
if (program->origin >= 0 && (uint32_t)program->origin != offset)
{
return false;
}
uint32_t used_mask = _used_instruction_space[rp23xx_pio_get_index(pio)];
uint32_t program_mask = (1u << program->length) - 1;
return !(used_mask & (program_mask << offset));
}
static void _pio_add_program_at_offset(uint32_t pio,
const rp23xx_pio_program_t *program,
uint32_t offset)
{
if (!_pio_can_add_program_at_offset(pio, program, offset))
{
DEBUGPANIC(); /* "No program space" */
}
for (uint32_t i = 0; i < program->length; ++i)
{
uint16_t instr = program->instructions[i];
putreg32(pio_instr_bits_jmp != _pio_major_instr_bits(instr) ?
instr : instr + offset,
RP23XX_PIO_INSTR_MEM(pio, offset + i));
}
uint32_t program_mask = (1u << program->length) - 1;
_used_instruction_space[rp23xx_pio_get_index(pio)] |=
program_mask << offset;
}
/****************************************************************************
* Public Functions
****************************************************************************/
void rp23xx_pio_sm_claim(uint32_t pio, uint32_t sm)
{
check_sm_param(sm);
uint32_t which = rp23xx_pio_get_index(pio);
if (which)
{
hw_claim_or_assert(&claimed, RP23XX_PIO_SM_NUM + sm,
"PIO 1 SM (%d - 4) already claimed");
}
else
{
hw_claim_or_assert(&claimed, sm,
"PIO 0 SM %d already claimed");
}
}
void rp23xx_pio_claim_sm_mask(uint32_t pio, uint32_t sm_mask)
{
for (uint32_t i = 0; sm_mask; i++, sm_mask >>= 1u)
{
if (sm_mask & 1u)
{
rp23xx_pio_sm_claim(pio, i);
}
}
}
void rp23xx_pio_sm_unclaim(uint32_t pio, uint32_t sm)
{
check_sm_param(sm);
uint32_t which = rp23xx_pio_get_index(pio);
hw_claim_clear(&claimed, which * RP23XX_PIO_SM_NUM + sm);
}
int rp23xx_pio_claim_unused_sm(uint32_t pio, bool required)
{
/* PIO index is 0 or 1. */
uint32_t which = rp23xx_pio_get_index(pio);
uint32_t base = which * RP23XX_PIO_SM_NUM;
int index = hw_claim_unused_from_range((uint8_t *)&claimed, required, base,
base + RP23XX_PIO_SM_NUM - 1,
"No PIO state machines are available");
return index >= (int)base ? index - (int)base : -1;
}
bool rp23xx_pio_can_add_program(uint32_t pio,
const rp23xx_pio_program_t *program)
{
uint32_t save = hw_claim_lock();
bool rc = -1 != _pio_find_offset_for_program(pio, program);
hw_claim_unlock(save);
return rc;
}
bool rp23xx_pio_can_add_program_at_offset(uint32_t pio,
const rp23xx_pio_program_t *program,
uint32_t offset)
{
uint32_t save = hw_claim_lock();
bool rc = _pio_can_add_program_at_offset(pio, program, offset);
hw_claim_unlock(save);
return rc;
}
/* these assert if unable */
uint32_t rp23xx_pio_add_program(uint32_t pio,
const rp23xx_pio_program_t *program)
{
uint32_t save = hw_claim_lock();
int offset = _pio_find_offset_for_program(pio, program);
if (offset < 0)
{
DEBUGPANIC(); /* "No program space" */
}
_pio_add_program_at_offset(pio, program, (uint32_t)offset);
hw_claim_unlock(save);
return (uint32_t)offset;
}
void rp23xx_pio_add_program_at_offset(uint32_t pio,
const rp23xx_pio_program_t *program,
uint32_t offset)
{
uint32_t save = hw_claim_lock();
_pio_add_program_at_offset(pio, program, offset);
hw_claim_unlock(save);
}
void rp23xx_pio_remove_program(uint32_t pio,
const rp23xx_pio_program_t *program,
uint32_t loaded_offset)
{
uint32_t program_mask = (1u << program->length) - 1;
program_mask <<= loaded_offset;
uint32_t save = hw_claim_lock();
ASSERT(program_mask ==
(_used_instruction_space[rp23xx_pio_get_index(pio)] &
program_mask));
_used_instruction_space[rp23xx_pio_get_index(pio)] &= ~program_mask;
hw_claim_unlock(save);
}
void rp23xx_pio_clear_instruction_memory(uint32_t pio)
{
uint32_t save = hw_claim_lock();
_used_instruction_space[rp23xx_pio_get_index(pio)] = 0;
for (uint32_t i = 0; i < PIO_INSTRUCTION_COUNT; i++)
{
putreg32(pio_encode_jmp(i), RP23XX_PIO_INSTR_MEM(pio, i));
}
hw_claim_unlock(save);
}
/* Set the value of all PIO pins. This is done by forcibly executing
* instructions on a "victim" state machine, sm. Ideally you should choose
* one which is not currently running a program. This is intended for
* one-time setup of initial pin states.
*/
void rp23xx_pio_sm_set_pins(uint32_t pio, uint32_t sm, uint32_t pins)
{
check_pio_param(pio);
check_sm_param(sm);
uint32_t pinctrl_saved = getreg32(RP23XX_PIO_SM_PINCTRL(pio, sm));
uint32_t remaining = 32;
uint32_t base = 0;
while (remaining)
{
uint32_t decrement = remaining > 5 ? 5 : remaining;
putreg32((decrement << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT) |
(base << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT),
RP23XX_PIO_SM_PINCTRL(pio, sm));
rp23xx_pio_sm_exec(pio, sm,
pio_encode_set(pio_pins, pins & 0x1fu));
remaining -= decrement;
base += decrement;
pins >>= 5;
}
putreg32(pinctrl_saved, RP23XX_PIO_SM_PINCTRL(pio, sm));
}
void rp23xx_pio_sm_set_pins_with_mask(uint32_t pio, uint32_t sm,
uint32_t pinvals, uint32_t pin_mask)
{
check_pio_param(pio);
check_sm_param(sm);
uint32_t pinctrl_saved = getreg32(RP23XX_PIO_SM_PINCTRL(pio, sm));
while (pin_mask)
{
uint32_t base = (uint32_t)__builtin_ctz(pin_mask);
putreg32((1u << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT) |
(base << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT),
RP23XX_PIO_SM_PINCTRL(pio, sm));
rp23xx_pio_sm_exec(pio, sm,
pio_encode_set(pio_pins,
(pinvals >> base) & 0x1u));
pin_mask &= pin_mask - 1;
}
putreg32(pinctrl_saved, RP23XX_PIO_SM_PINCTRL(pio, sm));
}
void rp23xx_pio_sm_set_pindirs_with_mask(uint32_t pio, uint32_t sm,
uint32_t pindirs,
uint32_t pin_mask)
{
check_pio_param(pio);
check_sm_param(sm);
uint32_t pinctrl_saved = getreg32(RP23XX_PIO_SM_PINCTRL(pio, sm));
while (pin_mask)
{
uint32_t base = (uint32_t)__builtin_ctz(pin_mask);
putreg32((1u << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT) |
(base << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT),
RP23XX_PIO_SM_PINCTRL(pio, sm));
rp23xx_pio_sm_exec(pio, sm,
pio_encode_set(pio_pindirs,
(pindirs >> base) & 0x1u));
pin_mask &= pin_mask - 1;
}
putreg32(pinctrl_saved, RP23XX_PIO_SM_PINCTRL(pio, sm));
}
void rp23xx_pio_sm_set_consecutive_pindirs(uint32_t pio, uint32_t sm,
uint32_t pin,
uint32_t count, bool is_out)
{
check_pio_param(pio);
check_sm_param(sm);
valid_params_if(PIO, pin < 32u);
uint32_t pinctrl_saved = getreg32(RP23XX_PIO_SM_PINCTRL(pio, sm));
uint32_t pindir_val = is_out ? 0x1f : 0;
while (count > 5)
{
putreg32((5u << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT) |
(pin << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT),
RP23XX_PIO_SM_PINCTRL(pio, sm));
rp23xx_pio_sm_exec(pio, sm,
pio_encode_set(pio_pindirs, pindir_val));
count -= 5;
pin = (pin + 5) & 0x1f;
}
putreg32((count << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT) |
(pin << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT),
RP23XX_PIO_SM_PINCTRL(pio, sm));
rp23xx_pio_sm_exec(pio, sm,
pio_encode_set(pio_pindirs, pindir_val));
putreg32(pinctrl_saved, RP23XX_PIO_SM_PINCTRL(pio, sm));
}
void rp23xx_pio_sm_init(uint32_t pio, uint32_t sm, uint32_t initial_pc,
const rp23xx_pio_sm_config *config)
{
valid_params_if(PIO, initial_pc < PIO_INSTRUCTION_COUNT);
/* Halt the machine, set some sensible defaults */
rp23xx_pio_sm_set_enabled(pio, sm, false);
if (config)
{
rp23xx_pio_sm_set_config(pio, sm, config);
}
else
{
rp23xx_pio_sm_config c = rp23xx_pio_get_default_sm_config();
rp23xx_pio_sm_set_config(pio, sm, &c);
}
rp23xx_pio_sm_clear_fifos(pio, sm);
/* Clear FIFO debug flags */
const uint32_t fdebug_sm_mask = (1u << RP23XX_PIO_FDEBUG_TXOVER_SHIFT) |
(1u << RP23XX_PIO_FDEBUG_RXUNDER_SHIFT) |
(1u << RP23XX_PIO_FDEBUG_TXSTALL_SHIFT) |
(1u << RP23XX_PIO_FDEBUG_RXSTALL_SHIFT);
putreg32(fdebug_sm_mask << sm, RP23XX_PIO_FDEBUG(pio));
/* Finally, clear some internal SM state */
rp23xx_pio_sm_restart(pio, sm);
rp23xx_pio_sm_clkdiv_restart(pio, sm);
rp23xx_pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc));
}
void rp23xx_pio_sm_drain_tx_fifo(uint32_t pio, uint32_t sm)
{
uint32_t instr = (getreg32(RP23XX_PIO_SM_SHIFTCTRL(pio, sm)) &
RP23XX_PIO_SM_SHIFTCTRL_AUTOPULL) ?
pio_encode_out(pio_null, 32) :
pio_encode_pull(false, false);
while (!rp23xx_pio_sm_is_tx_fifo_empty(pio, sm))
{
rp23xx_pio_sm_exec(pio, sm, instr);
}
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pio_instructions.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_PIO_INSTRUCTIONS_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_PIO_INSTRUCTIONS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include "rp23xx_pio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS,
* Enable/disable assertions in the PIO instructions, type=bool, default=0,
* group=hardware_pio
*/
#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0
#endif
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Types
****************************************************************************/
enum pio_instr_bits
{
pio_instr_bits_jmp = 0x0000,
pio_instr_bits_wait = 0x2000,
pio_instr_bits_in = 0x4000,
pio_instr_bits_out = 0x6000,
pio_instr_bits_push = 0x8000,
pio_instr_bits_pull = 0x8080,
pio_instr_bits_mov = 0xa000,
pio_instr_bits_irq = 0xc000,
pio_instr_bits_set = 0xe000,
};
#ifndef NDEBUG
#define _PIO_INVALID_IN_SRC 0x08u
#define _PIO_INVALID_OUT_DEST 0x10u
#define _PIO_INVALID_SET_DEST 0x20u
#define _PIO_INVALID_MOV_SRC 0x40u
#define _PIO_INVALID_MOV_DEST 0x80u
#else
#define _PIO_INVALID_IN_SRC 0u
#define _PIO_INVALID_OUT_DEST 0u
#define _PIO_INVALID_SET_DEST 0u
#define _PIO_INVALID_MOV_SRC 0u
#define _PIO_INVALID_MOV_DEST 0u
#endif
enum pio_src_dest
{
pio_pins = 0u,
pio_x = 1u,
pio_y = 2u,
pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC |
_PIO_INVALID_MOV_DEST,
pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST |
_PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST |
_PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST |
_PIO_INVALID_MOV_SRC,
pio_isr = 6u | _PIO_INVALID_SET_DEST,
pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST,
pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST |
_PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
};
/****************************************************************************
* Inline Functions
****************************************************************************/
inline static uint32_t _pio_major_instr_bits(uint32_t instr)
{
return instr & 0xe000u;
}
inline static uint32_t _pio_encode_instr_and_args(
enum pio_instr_bits instr_bits,
uint32_t arg1, uint32_t arg2)
{
valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
#if PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
uint32_t major = _pio_major_instr_bits(instr_bits);
if (major == pio_instr_bits_in || major == pio_instr_bits_out)
{
ASSERT(arg2 && arg2 <= 32);
}
else
{
ASSERT(arg2 <= 31);
}
#endif
return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
}
inline static uint32_t _pio_encode_instr_and_src_dest(
enum pio_instr_bits instr_bits,
enum pio_src_dest dest,
uint32_t value)
{
return _pio_encode_instr_and_args(instr_bits, dest & 7u, value);
}
inline static uint32_t pio_encode_delay(uint32_t cycles)
{
valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
return cycles << 8u;
}
inline static uint32_t pio_encode_sideset(uint32_t sideset_bit_count,
uint32_t value)
{
valid_params_if(PIO_INSTRUCTIONS,
sideset_bit_count >= 1 && sideset_bit_count <= 5);
valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count));
return value << (13u - sideset_bit_count);
}
inline static uint32_t pio_encode_sideset_opt(uint32_t sideset_bit_count,
uint32_t value)
{
valid_params_if(PIO_INSTRUCTIONS,
sideset_bit_count >= 2 && sideset_bit_count <= 5);
valid_params_if(PIO_INSTRUCTIONS, value <= (0x1fu >> sideset_bit_count));
return 0x1000u | value << (12u - sideset_bit_count);
}
inline static uint32_t pio_encode_jmp(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
}
inline static uint32_t pio_encode_jmp_not_x(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr);
}
inline static uint32_t pio_encode_jmp_x_dec(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr);
}
inline static uint32_t pio_encode_jmp_not_y(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr);
}
inline static uint32_t pio_encode_jmp_y_dec(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr);
}
inline static uint32_t pio_encode_jmp_x_ne_y(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr);
}
inline static uint32_t pio_encode_jmp_pin(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr);
}
inline static uint32_t pio_encode_jmp_not_osre(uint32_t addr)
{
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr);
}
inline static uint32_t _pio_encode_irq(bool relative, uint32_t irq)
{
valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
return (relative ? 0x10u : 0x0u) | irq;
}
inline static uint32_t pio_encode_wait_gpio(bool polarity, uint32_t pin)
{
return _pio_encode_instr_and_args(pio_instr_bits_wait,
0u | (polarity ? 4u : 0u), pin);
}
inline static uint32_t pio_encode_wait_pin(bool polarity, uint32_t pin)
{
return _pio_encode_instr_and_args(pio_instr_bits_wait,
1u | (polarity ? 4u : 0u), pin);
}
inline static uint32_t pio_encode_wait_irq(bool polarity, bool relative,
uint32_t irq)
{
valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
return _pio_encode_instr_and_args(pio_instr_bits_wait,
2u | (polarity ? 4u : 0u),
_pio_encode_irq(relative, irq));
}
inline static uint32_t pio_encode_in(enum pio_src_dest src, uint32_t value)
{
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, value);
}
inline static uint32_t pio_encode_out(enum pio_src_dest dest, uint32_t value)
{
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST));
return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, value);
}
inline static uint32_t pio_encode_push(bool if_full, bool block)
{
return _pio_encode_instr_and_args(pio_instr_bits_push,
(if_full ? 2u : 0u) | (block ? 1u : 0u),
0);
}
inline static uint32_t pio_encode_pull(bool if_empty, bool block)
{
return _pio_encode_instr_and_args(pio_instr_bits_pull,
(if_empty ? 2u : 0u) | (block ? 1u : 0u),
0);
}
inline static uint32_t pio_encode_mov(enum pio_src_dest dest,
enum pio_src_dest src)
{
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest,
src & 7u);
}
inline static uint32_t pio_encode_mov_not(enum pio_src_dest dest,
enum pio_src_dest src)
{
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest,
(1u << 3u) | (src & 7u));
}
inline static uint32_t pio_encode_mov_reverse(enum pio_src_dest dest,
enum pio_src_dest src)
{
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest,
(2u << 3u) | (src & 7u));
}
inline static uint32_t pio_encode_irq_set(bool relative, uint32_t irq)
{
return _pio_encode_instr_and_args(pio_instr_bits_irq, 0,
_pio_encode_irq(relative, irq));
}
inline static uint32_t pio_encode_irq_wait(bool relative, uint32_t irq)
{
return _pio_encode_instr_and_args(pio_instr_bits_irq, 1,
_pio_encode_irq(relative, irq));
}
inline static uint32_t pio_encode_irq_clear(bool relative, uint32_t irq)
{
return _pio_encode_instr_and_args(pio_instr_bits_irq, 2,
_pio_encode_irq(relative, irq));
}
inline static uint32_t pio_encode_set(enum pio_src_dest dest, uint32_t value)
{
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST));
return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value);
}
inline static uint32_t pio_encode_nop(void)
{
return pio_encode_mov(pio_y, pio_y);
}
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_PIO_INSTRUNCTIONS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pll.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "rp23xx_pll.h"
#include "hardware/rp23xx_pll.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_pll_init
*
* Description:
* Initialize PLL.
*
****************************************************************************/
void rp23xx_pll_init(uint32_t base, uint32_t refdiv, uint32_t vco_freq,
uint32_t post_div1, uint8_t post_div2)
{
/* Turn off PLL in case it is already running */
putreg32(0xffffffff, base + RP23XX_PLL_PWR_OFFSET);
putreg32(0, base + RP23XX_PLL_FBDIV_INT_OFFSET);
uint32_t ref_mhz = BOARD_XOSC_FREQ / refdiv;
putreg32(refdiv, base + RP23XX_PLL_CS_OFFSET);
/* What are we multiplying the reference clock by to get the vco freq
* (The regs are called div, because you divide the vco output and compare
* it to the refclk)
*/
uint32_t fbdiv = vco_freq / ref_mhz;
/* Check parameter ranges */
ASSERT(fbdiv >= 16 && fbdiv <= 320);
ASSERT((post_div1 >= 1 && post_div1 <= 7) &&
(post_div2 >= 1 && post_div2 <= 7));
ASSERT(post_div2 <= post_div1);
ASSERT(ref_mhz <= (vco_freq / 16));
/* Put calculated value into feedback divider */
putreg32(fbdiv, base + RP23XX_PLL_FBDIV_INT_OFFSET);
/* Turn on PLL */
clrbits_reg32(RP23XX_PLL_PWR_PD | RP23XX_PLL_PWR_VCOPD,
base + RP23XX_PLL_PWR_OFFSET);
/* Wait for PLL to lock */
while (!(getreg32(base + RP23XX_PLL_CS_OFFSET) & RP23XX_PLL_CS_LOCK))
;
/* Set up post dividers */
putreg32((post_div1 << RP23XX_PLL_PRIM_POSTDIV1_SHIFT) |
(post_div2 << RP23XX_PLL_PRIM_POSTDIV2_SHIFT),
base + RP23XX_PLL_PRIM_OFFSET);
/* Turn on post divider */
clrbits_reg32(RP23XX_PLL_PWR_POSTDIVPD, base + RP23XX_PLL_PWR_OFFSET);
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pll.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_PLL_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_PLL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_pll_init
*
* Description:
* Initialize PLL.
*
****************************************************************************/
void rp23xx_pll_init(uint32_t base, uint32_t refdiv, uint32_t vco_freq,
uint32_t post_div1, uint8_t post_div2);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_PLL_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/timers/pwm.h>
#include <arch/board/board.h>
#include "rp23xx_gpio.h"
#include "rp23xx_pwm.h"
/****************************************************************************
* Local Function Prototypes
****************************************************************************/
static int pwm_setup (struct pwm_lowerhalf_s * dev);
static int pwm_shutdown (struct pwm_lowerhalf_s * dev);
static int pwm_start (struct pwm_lowerhalf_s * dev,
const struct pwm_info_s * info);
static int pwm_stop (struct pwm_lowerhalf_s * dev);
static int pwm_ioctl (struct pwm_lowerhalf_s * dev,
int cmd,
unsigned long arg);
static void setup_period (struct rp23xx_pwm_lowerhalf_s * priv);
static void setup_pulse (struct rp23xx_pwm_lowerhalf_s * priv);
static void set_enabled (struct rp23xx_pwm_lowerhalf_s * priv);
static void clear_enabled(struct rp23xx_pwm_lowerhalf_s * priv);
/****************************************************************************
* Private Data
****************************************************************************/
/* PWM operations */
static const struct pwm_ops_s g_pwmops =
{
.setup = pwm_setup,
.shutdown = pwm_shutdown,
.start = pwm_start,
.stop = pwm_stop,
.ioctl = pwm_ioctl
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_pwm_initialize
*
* Description:
* Initialize the selected PWM port. And return a unique instance of struct
* struct rp23xx_pwm_lowerhalf_s. This function may be called to obtain
* multiple instances of the interface, each of which may be set up with a
* different frequency and address.
*
* Input Parameters:
* Port number (for hardware that has multiple PWM interfaces)
* GPIO pin number for pin A
* GPIO pin number for pin B (CONFIG_PWM_NCHANNELS == 2)
*
* Returned Value:
* Valid PWM device structure reference on success; a NULL on failure
*
****************************************************************************/
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
struct rp23xx_pwm_lowerhalf_s *rp23xx_pwm_initialize(int port,
int pin_a,
int pin_b,
uint32_t flags)
#else
struct rp23xx_pwm_lowerhalf_s *rp23xx_pwm_initialize(int port,
int pin,
uint32_t flags)
#endif
{
struct rp23xx_pwm_lowerhalf_s *data;
data = calloc(1, sizeof (struct rp23xx_pwm_lowerhalf_s));
if (data != NULL)
{
data->ops = &g_pwmops;
data->num = port;
data->flags = flags;
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
if (pin_a == 2*port || pin_a == 2*port + 16)
{
data->pin[0] = pin_a;
}
else
{
data->pin[0] = -1;
}
if (pin_b == 2*port + 1 || pin_b == 2*port + 17)
{
data->pin[1] = pin_b;
}
else
{
data->pin[1] = -1;
}
#else
if (pin == 2*port || pin == 2*port + 16)
{
data->pin = pin;
}
else
{
data->pin = -1;
}
#endif
}
return data;
}
/****************************************************************************
* Name: rp23xx_pwm_uninitialize
*
* Description:
* De-initialize the selected pwm port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the rp23xx_pwmdev_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int rp23xx_pwm_uninitialize(struct pwm_lowerhalf_s *dev)
{
free(dev);
return (OK);
}
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: pwm_setup
*
* Description:
* This method is called when the driver is opened. The lower half driver
* should configure and initialize the device so that it is ready for use.
* It should not, however, output pulses until the start method is called.
*
* Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int pwm_setup(struct pwm_lowerhalf_s * dev)
{
struct rp23xx_pwm_lowerhalf_s *priv = (struct rp23xx_pwm_lowerhalf_s *)dev;
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
pwminfo("PWM%d pin_a %d pin_b %d\n",
priv->num,
priv->pin[0],
priv->pin[1]);
if (priv->pin[0] >= 0)
{
rp23xx_gpio_set_function(priv->pin[0], RP23XX_GPIO_FUNC_PWM);
}
if (priv->pin[1] >= 0)
{
rp23xx_gpio_set_function(priv->pin[1], RP23XX_GPIO_FUNC_PWM);
}
#else
if (priv->pin >= 0)
{
rp23xx_gpio_set_function(priv->pin, RP23XX_GPIO_FUNC_PWM);
}
#endif
return 0;
}
/****************************************************************************
* Name: pwm_shutdown
*
* Description:
* This method is called when the driver is closed. The lower half driver
* stop pulsed output, free any resources, disable the timer hardware, and
* put the system into the lowest possible power usage state
*
* Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int pwm_shutdown (struct pwm_lowerhalf_s * dev)
{
struct rp23xx_pwm_lowerhalf_s *priv = (struct rp23xx_pwm_lowerhalf_s *)dev;
pwminfo("PWM%d\n", priv->num);
/* Stop timer */
pwm_stop(dev);
/* Force the GPIO pins to the appropriate idle state */
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
pwminfo("PWM%d pin_a %d pin_b %d\n",
priv->num,
priv->pin[0],
priv->pin[1]);
if (priv->pin[0] >= 0)
{
pwminfo("PWM%d setting pin_a %d\n",
priv->num,
(priv->flags & RP23XX_RV_PWM_CSR_A_INV) ? 1 : 0);
rp23xx_gpio_setdir(priv->pin[0], true);
rp23xx_gpio_put(priv->pin[0],
((priv->flags & RP23XX_RV_PWM_CSR_A_INV) != 0));
rp23xx_gpio_set_function(priv->pin[0], RP23XX_GPIO_FUNC_SIO);
}
if (priv->pin[1] >= 0)
{
pwminfo("PWM%d setting pin_b %d\n",
priv->num,
(priv->flags & RP23XX_RV_PWM_CSR_B_INV) ? 1 : 0);
rp23xx_gpio_setdir(priv->pin[1], true);
rp23xx_gpio_put(priv->pin[1],
((priv->flags & RP23XX_RV_PWM_CSR_B_INV) != 0));
rp23xx_gpio_set_function(priv->pin[1], RP23XX_GPIO_FUNC_SIO);
}
#else
pwminfo("PWM%d pin %d\n", priv->num, priv->pin);
if (priv->pin >= 0)
{
rp23xx_gpio_setdir(priv->pin, true);
rp23xx_gpio_put(priv->pin,
((priv->flags & RP23XX_RV_PWM_CSR_A_INV) != 0));
rp23xx_gpio_set_function(priv->pin, RP23XX_GPIO_FUNC_SIO);
}
#endif
/* Clear timer and channel configuration */
priv->frequency = 0;
priv->divisor = 0x00000010; /* hex 1.0 */
priv->top = 0xffff;
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
for (int i = 0; i < CONFIG_PWM_NCHANNELS; ++i)
{
priv->duty[i] = 0;
}
#else
priv->duty = 0;
#endif
return 0;
}
/****************************************************************************
* Name: pwm_start
*
* Description:
* (Re-)initialize the timer resources and start the pulsed output
*
* Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* info - A reference to the characteristics of the pulsed output
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int pwm_start(struct pwm_lowerhalf_s * dev,
const struct pwm_info_s * info)
{
struct rp23xx_pwm_lowerhalf_s *priv = (struct rp23xx_pwm_lowerhalf_s *)dev;
pwminfo("PWM%d\n", priv->num);
/* Update timer with given PWM timer frequency */
if (priv->frequency != info->frequency)
{
priv->frequency = info->frequency;
/* We want to compute the top and divisor to give the finest control */
setup_period(priv);
}
/* Update timer with given PWM channel duty */
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
for (int i = 0; i < CONFIG_PWM_NCHANNELS; i++)
{
if (priv->duty[i] != info->channels[i].duty)
{
priv->duty[i] = info->channels[i].duty;
}
}
#else
if (priv->duty != info[0].duty)
{
priv->duty = info[0].duty;
}
#endif
setup_pulse(priv);
set_enabled(priv);
return 0;
}
/****************************************************************************
* Name: pwm_stop
*
* Description:
* Stop the pulsed output.
*
* Input Parameters:
* dev - A reference to the lower half PWM driver state structure
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int pwm_stop(struct pwm_lowerhalf_s * dev)
{
struct rp23xx_pwm_lowerhalf_s *priv = (struct rp23xx_pwm_lowerhalf_s *)dev;
pwminfo("PWM%d\n", priv->num);
clear_enabled(priv);
return 0;
}
/****************************************************************************
* Name: pwm_ioctl
*
* Description:
* Lower-half logic may support platform-specific ioctl commands
*
* Input Parameters:
* dev - A reference to the lower half PWM driver state structure
* cmd - The ioctl command
* arg - The argument accompanying the ioctl command
*
* Returned Value:
* Zero on success; a negated errno value on failure
*
****************************************************************************/
int pwm_ioctl(struct pwm_lowerhalf_s * dev,
int cmd,
unsigned long arg)
{
struct rp23xx_pwm_lowerhalf_s *priv = (struct rp23xx_pwm_lowerhalf_s *)dev;
#ifdef CONFIG_DEBUG_PWM_INFO
pwminfo("PWM%d\n", priv->num);
#endif
switch (cmd)
{
case PWMIOC_RP23XX_SETINVERTPULSE:
priv->flags &= ~(RP23XX_RV_PWM_CSR_B_INV | RP23XX_RV_PWM_CSR_A_INV);
priv->flags |= (arg & 0x03) << 2;
setup_period(priv);
setup_pulse(priv);
return 0;
case PWMIOC_RP23XX_GETINVERTPULSE:
return (priv->flags & (RP23XX_RV_PWM_CSR_B_INV
| RP23XX_RV_PWM_CSR_A_INV)) >> 2;
case PWMIOC_RP23XX_SETPHASECORRECT:
priv->flags &= ~(RP23XX_RV_PWM_CSR_PH_CORRECT);
priv->flags |= (arg != 0) ? RP23XX_RV_PWM_CSR_PH_CORRECT : 0x00;
setup_period(priv);
setup_pulse(priv);
return 0;
case PWMIOC_RP23XX_GETPHASECORRECT:
return (priv->flags & RP23XX_RV_PWM_CSR_PH_CORRECT) ? 1 : 0;
}
return -ENOTTY;
}
/****************************************************************************
* Name: setup_period
*
* Description:
* compute and set the clock divisor and top value based on frequency.
*
* Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
****************************************************************************/
void setup_period(struct rp23xx_pwm_lowerhalf_s * priv)
{
irqstate_t flags;
uint32_t max_freq = BOARD_SYS_FREQ / 0x10000; /* initially, with full range count */
uint32_t frequency = priv->frequency;
/* If we are running phase correct we double the frequency value
* since the PWM will generate a pulse chain at half what it
* would be in normal (non-phase correct) mode
*/
if (priv->flags & RP23XX_RV_PWM_CSR_PH_CORRECT)
{
frequency *= 2;
}
pwminfo("PWM%d freq %ld max %ld\n", priv->num, priv->frequency, max_freq);
if (frequency <= max_freq)
{
/* We can keep full range count and slow clock down with divisor */
priv->top = 0xffff;
}
else
{
/* we need to speed things up by reducing top */
priv->top = 0xffff / (frequency / max_freq);
/* compute new maximum frequency */
max_freq = BOARD_SYS_FREQ / (priv->top + 1);
}
priv->divisor = 16 * max_freq / frequency;
pwminfo("PWM%d top 0x%08X div 0x%08lX\n",
priv->num,
priv->top,
priv->divisor);
flags = enter_critical_section();
putreg32(priv->top, RP23XX_RV_PWM_TOP(priv->num));
putreg32(priv->divisor, RP23XX_RV_PWM_DIV(priv->num));
leave_critical_section(flags);
}
/****************************************************************************
* Name: setup_pulse
*
* Description:
* compute and set the compare values and set CSR flags.
*
* Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
****************************************************************************/
void setup_pulse(struct rp23xx_pwm_lowerhalf_s * priv)
{
irqstate_t flags;
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
uint32_t compare =
(0xffff * (uint32_t)priv->duty[0] / priv->top)
+ ((0xffff * (uint32_t)priv->duty[1] / priv->top) << 16);
#else
uint32_t compare = 0xffff * (uint32_t)priv->duty / priv->top;
#endif
pwminfo("PWM%d compare 0x%08lX flags 0x%08lX\n",
priv->num,
compare,
priv->flags);
flags = enter_critical_section();
putreg32(compare, RP23XX_RV_PWM_CC(priv->num));
modreg32(priv->flags,
RP23XX_RV_PWM_CSR_DIVMODE_MASK
| RP23XX_RV_PWM_CSR_B_INV
| RP23XX_RV_PWM_CSR_A_INV
| RP23XX_RV_PWM_CSR_PH_CORRECT,
RP23XX_RV_PWM_CSR(priv->num));
leave_critical_section(flags);
}
/****************************************************************************
* Name: set_enabled
*
* Description:
* set the enable bit for a given slice.
*
* Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
****************************************************************************/
static inline void set_enabled(struct rp23xx_pwm_lowerhalf_s * priv)
{
irqstate_t flags = enter_critical_section();
modreg32(1 << priv->num, 1 << priv->num, RP23XX_RV_PWM_EN);
leave_critical_section(flags);
}
/****************************************************************************
* Name: clear_enabled
*
* Description:
* clear the enable bit for a given slice.
*
* Input Parameters:
* priv - A reference to the lower half PWM driver state structure
*
****************************************************************************/
static inline void clear_enabled(struct rp23xx_pwm_lowerhalf_s * priv)
{
irqstate_t flags = enter_critical_section();
modreg32(0, 1 << priv->num, RP23XX_RV_PWM_EN);
leave_critical_section(flags);
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_pwm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_PWM_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/rp23xx_pwm.h"
#include "nuttx/timers/pwm.h"
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* This structure represents the state of one PWM timer */
struct rp23xx_pwm_lowerhalf_s
{
const struct pwm_ops_s * ops; /* PWM operations */
uint32_t frequency; /* PWM current frequency */
uint32_t divisor; /* PWM current clock divisor */
uint32_t flags; /* PWM mode flags */
uint16_t top; /* PWM current top value */
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
uint16_t duty[2];
int8_t pin[2];
#else
uint16_t duty; /* Time duty value */
int8_t pin;
#endif
uint8_t num; /* Timer ID */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_pwm_initialize
*
* Description:
* Initialize the selected PWM port. And return a unique instance of struct
* struct rp23xx_pwm_lowerhalf_s. This function may be called to obtain
* multiple instances of the interface, each of which may be set up with a
* different frequency and address.
*
* Input Parameters:
* Port number (for hardware that has multiple PWM interfaces)
* GPIO pin number for pin A
* GPIO pin number for pin B (CONFIG_PWM_NCHANNELS == 2)
*
* Returned Value:
* Valid PWM device structure reference on success; a NULL on failure
*
****************************************************************************/
#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2
struct rp23xx_pwm_lowerhalf_s *rp23xx_pwm_initialize(int port,
int pin_a,
int pin_b,
uint32_t flags);
#else
struct rp23xx_pwm_lowerhalf_s *rp23xx_pwm_initialize(int port,
int pin,
uint32_t flags);
#endif
/****************************************************************************
* Name: rp23xx_pwmdev_uninitialize
*
* Description:
* De-initialize the selected pwm port, and power down the device.
*
* Input Parameter:
* Device structure as returned by the rp23xx_pwmdev_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int rp23xx_pwm_uninitialize(struct pwm_lowerhalf_s *dev);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_I2C_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_rom.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ROM FUNCTIONS */
/* RP2040 & RP2350 */
#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R')
#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X')
#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X')
#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C')
#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F')
#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E')
#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P')
/* RP2350 only */
#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B')
#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I')
#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B')
#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A')
#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D')
#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O')
#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B')
#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P')
#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S')
#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U')
#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P')
#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A')
#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T')
#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A')
#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B')
#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C')
#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C')
#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P')
#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R')
#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S')
#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F')
#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M')
#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B')
/* these form a bit set */
#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01
#define BOOTROM_STATE_RESET_OTHER_CORE 0x02
#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 /* reset any global state (e.g. permissions) */
#define RT_FLAG_FUNC_RISCV 0x0001
#define RT_FLAG_FUNC_RISCV_FAR 0x0003
#define RT_FLAG_FUNC_ARM_SEC 0x0004
/* reserved for 32-bit pointer: 0x0008 */
#define RT_FLAG_FUNC_ARM_NONSEC 0x0010
#define BOOTROM_FUNC_TABLE_OFFSET 0x14
#define BOOTROM_IS_A2() ((*(volatile uint8_t *)0x13) == 2)
#define BOOTROM_WELL_KNOWN_PTR_SIZE (BOOTROM_IS_A2() ? 2 : 4)
#if defined(__riscv)
#define BOOTROM_ENTRY_OFFSET 0x7dfc
#define BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE)
#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE*2)
#else
#define BOOTROM_VTABLE_OFFSET 0x00
#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE)
#endif
#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
/****************************************************************************
* Public Type Definitions
****************************************************************************/
typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask);
static __inline void *rom_func_lookup(uint32_t code)
{
#ifdef __riscv
uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0;
/* on RISC-V the code (a jmp) is actually embedded in the table */
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
*(uint16_t *)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust);
return rom_table_lookup(code, RT_FLAG_FUNC_RISCV);
#else
/* on ARM the function pointer is stored in the table, so we dereference
* it via lookup() rather than lookup_entry()
*/
rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)
*(uint16_t *)(BOOTROM_TABLE_LOOKUP_OFFSET);
if (pico_processor_state_is_nonsecure())
{
return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC);
}
else
{
return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC);
}
#endif
}

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_serial.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_SERIAL_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "rp23xx_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_SERIAL_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <string.h>
#include <stdio.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/sched_note.h>
#include "sched/sched.h"
#include "riscv_internal.h"
#include "hardware/rp23xx_sio.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if 0
#define DPRINTF(fmt, args...) llinfo(fmt, ##args)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif
/****************************************************************************
* Name: rp23xx_handle_irqreq
*
* Description:
* If an irq handling request is found on cpu, call up_enable_irq() or
* up_disable_irq().
*
* Input Parameters:
* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
*
****************************************************************************/
static void rp23xx_handle_irqreq(int irqreq)
{
DEBUGASSERT(this_cpu() == 0);
if (irqreq > 0)
{
up_enable_irq(irqreq);
}
else
{
up_disable_irq(-irqreq);
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: rp23xx_smp_call_handler
*
* Description:
* This is the handler for SMP_CALL.
*
* Returned Value:
* Should always return OK
*
****************************************************************************/
int rp23xx_smp_call_handler(int irq, void *c, void *arg)
{
int cpu = this_cpu();
int irqreq;
uint32_t stat;
nxsched_smp_call_handler(irq, c, arg);
stat = getreg32(RP23XX_SIO_FIFO_ST);
if (stat & (RP23XX_SIO_FIFO_ST_ROE | RP23XX_SIO_FIFO_ST_WOF))
{
/* Clear sticky flag */
putreg32(0, RP23XX_SIO_FIFO_ST);
}
if (!(stat & RP23XX_SIO_FIFO_ST_VLD))
{
/* No data received */
return OK;
}
irqreq = getreg32(RP23XX_SIO_FIFO_RD);
if (irqreq != 0)
{
/* Handle IRQ enable/disable request */
rp23xx_handle_irqreq(irqreq);
return OK;
}
DPRINTF("cpu%d will be paused\n", cpu);
nxsched_process_delivered(cpu);
return OK;
}
/****************************************************************************
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
* check whether there are tasks delivered to specified cpu
* and try to run them.
*
* Input Parameters:
* cpu - The index of the CPU to be paused.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
* Assumptions:
* Called from within a critical section;
*
****************************************************************************/
int up_send_smp_sched(int cpu)
{
/* Generate IRQ for CPU(cpu) */
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
;
putreg32(0, RP23XX_SIO_FIFO_WR);
return OK;
}
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
int cpu;
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_send_smp_sched(cpu);
}
}
/****************************************************************************
* Name: rp23xx_send_irqreq()
*
* Description:
* Send up_enable_irq() / up_disable_irq() request to the Core #0
*
* This function is called from up_enable_irq() or up_disable_irq()
* to be handled on specified CPU. Locking protocol in the sequence is
* the same as up_pause_cpu() plus up_resume_cpu().
*
* Input Parameters:
* irqreq - The IRQ number to be handled (>0 : enable / <0 : disable)
*
****************************************************************************/
void rp23xx_send_irqreq(int irqreq)
{
/* Send IRQ number to Core #0 */
while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY))
;
putreg32(irqreq, RP23XX_SIO_FIFO_WR);
}
#endif /* CONFIG_SMP */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_spi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_SPI_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/spi.h>
#include "hardware/rp23xx_spi.h"
#ifdef CONFIG_RP23XX_RV_SPI_DMA
#include "rp23xx_dmac.h"
#endif
#if defined(CONFIG_RP23XX_RV_SPI0) || defined(CONFIG_RP23XX_RV_SPI1)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This header file defines interfaces to common SPI logic.
* To use this common SPI logic on your board:
*
* 1. Provide logic in rp23xx_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide rp23xx_spi0/1select() and rp23xx_spi0/1status() functions in
* your board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* rp23xx_spi0/1cmddata() functions in your board-specific logic. These
* functions will perform cmd/data selection operations using GPIOs in the
* way your board is configured.
* 4. Your low level board initialization logic should call
* rp23xx_spibus_initialize.
* 5. The handle returned by rp23xx_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic
* (e.g., calling mmcsd_spislotinitialize(), for example, will bind the
* SPI driver to the SPI MMC/SD driver).
*/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_spibus_initialize
*
* Description:
* Initialize the selected SPI port
*
* Input Parameter:
* port - Port number
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *rp23xx_spibus_initialize(int port);
/****************************************************************************
* Name: rp23xx_spiXselect, rp23xx_spiXstatus, and rp23xx_spiXcmddata
*
* Description:
* These functions must be provided in your board-specific logic.
* The rp23xx_spi0/1select functions will perform chip selection and the
* rp23xx_spi0/1status will perform status operations using GPIOs in
* the way your board is configured.
*
* If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
* rp23xx_spi0/1cmddata must also be provided.
* This functions performs cmd/data selection operations using GPIOs in
* the way your board is configured.
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_SPI0
void rp23xx_spi0select(struct spi_dev_s *dev,
uint32_t devid,
bool selected);
uint8_t rp23xx_spi0status(struct spi_dev_s *dev,
uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int rp23xx_spi0cmddata(struct spi_dev_s *dev,
uint32_t devid,
bool cmd);
#endif
#endif
#ifdef CONFIG_RP23XX_RV_SPI1
void rp23xx_spi1select(struct spi_dev_s *dev,
uint32_t devid,
bool selected);
uint8_t rp23xx_spi1status(struct spi_dev_s *dev,
uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int rp23xx_spi1cmddata(struct spi_dev_s *dev,
uint32_t devid,
bool cmd);
#endif
#endif
/****************************************************************************
* Name: spi_flush
*
* Description:
* Flush and discard any words left in the RX fifo. This can be called
* from spi0/1select after a device is deselected (if you worry about such
* things).
*
* Input Parameters:
* dev - Device-specific state data
*
* Returned Value:
* None
*
****************************************************************************/
void spi_flush(struct spi_dev_s *dev);
/****************************************************************************
* Name: rp23xx_spiXregister
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
* must be implemented. These functions implements the registercallback
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_RP23XX_RV_SPI0
int rp23xx_spi0register(struct spi_dev_s *dev,
spi_mediachange_t callback, void *arg);
#endif
#ifdef CONFIG_RP23XX_RV_SPI1
int rp23xx_spi1register(struct spi_dev_s *dev,
spi_mediachange_t callback, void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_RP23XX_RV_SPI0/1 */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_SPI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_start.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <sys/param.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "riscv_internal.h"
#include "rp23xx_config.h"
#include "rp23xx_clock.h"
#include "rp23xx_uart.h"
#include "hardware/rp23xx_sio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
void riscv_usbinitialize(void);
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#if defined(CONFIG_DEBUG_FEATURES) && defined(HAVE_SERIAL_CONSOLE)
# define showprogress(c) riscv_lowputc((uint32_t)c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __rp23xx_start(void)
{
#ifdef CONFIG_BOOT_RUNFROMFLASH
const uint32_t *src;
#endif
uint32_t *dest;
if (this_cpu() != 0)
{
while (1)
{
__asm__ volatile ("wfi");
}
}
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
{
*dest++ = 0;
}
/* Move the initialized data section from its temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
for (src = (const uint32_t *)_eronly,
dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
)
{
*dest++ = *src++;
}
#endif
/* Set up clock */
rp23xx_clockconfig();
rp23xx_boardearlyinitialize();
/* Configure the uart so that we can get debug output as soon as possible */
rp23xx_lowsetup();
showprogress('A');
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
riscv_earlyserialinit();
#endif
showprogress('B');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
rp23xx_userspace();
showprogress('C');
#endif
/* Initialize onboard resources */
rp23xx_boardinitialize();
showprogress('D');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}

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arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_alarm.h>
#include <arch/board/board.h>
#include "clock/clock.h"
#include "riscv_internal.h"
#include "riscv_mtimer.h"
#include "chip.h"
#include "hardware/rp23xx_memorymap.h"
#include "hardware/rp23xx_sio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIME_CTRL_OFFSET);
putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIME_OFFSET);
putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIMEH_OFFSET);
putreg32(RP23XX_SIO_MTIMECMP_MASK,
RP23XX_SIO_BASE + RP23XX_SIO_MTIMECMP_OFFSET);
putreg32(RP23XX_SIO_MTIMECMPH_MASK,
RP23XX_SIO_BASE + RP23XX_SIO_MTIMECMPH_OFFSET);
struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize(
RP23XX_SIO_BASE + RP23XX_SIO_MTIME_OFFSET,
RP23XX_SIO_BASE + RP23XX_SIO_MTIMECMP_OFFSET,
RISCV_IRQ_MTIMER, BOARD_SYS_FREQ);
DEBUGASSERT(lower);
up_alarm_set_lowerhalf(lower);
putreg32(RP23XX_SIO_MTIME_CTRL_EN | RP23XX_SIO_MTIME_CTRL_FULLSPEED,
RP23XX_SIO_BASE + RP23XX_SIO_MTIME_CTRL_OFFSET);
}

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arch/risc-v/src/rp23xx-rv/rp23xx_uart.c Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_uart.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/spinlock.h>
#include <arch/board/board.h>
#include <errno.h>
#include "riscv_internal.h"
#include "chip.h"
#include "rp23xx_config.h"
#include "rp23xx_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define CONSOLE_BASE RP23XX_RV_UART0_BASE
#define CONSOLE_BASEFREQ BOARD_UART_BASEFREQ
#define CONSOLE_BAUD CONFIG_UART0_BAUD
#define CONSOLE_BITS CONFIG_UART0_BITS
#define CONSOLE_PARITY CONFIG_UART0_PARITY
#define CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define CONSOLE_BASE RP23XX_RV_UART1_BASE
#define CONSOLE_BASEFREQ BOARD_UART_BASEFREQ
#define CONSOLE_BAUD CONFIG_UART1_BAUD
#define CONSOLE_BITS CONFIG_UART1_BITS
#define CONSOLE_PARITY CONFIG_UART1_PARITY
#define CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(HAVE_CONSOLE)
#error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
/* Get word length setting for the console */
#if defined(HAVE_CONSOLE)
#if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8
#define CONSOLE_LCR_WLS RP23XX_RV_UART_LCR_H_WLEN(CONSOLE_BITS)
#else
#error "Invalid CONFIG_UARTn_BITS setting for console "
#endif
#endif
/* Get parity setting for the console */
#if defined(HAVE_CONSOLE)
#if CONSOLE_PARITY == 0
#define CONSOLE_LCR_PAR 0
#elif CONSOLE_PARITY == 1
#define CONSOLE_LCR_PAR (RP23XX_RV_UART_UARTLCR_H_PEN)
#elif CONSOLE_PARITY == 2
#define CONSOLE_LCR_PAR (RP23XX_RV_UART_UARTLCR_H_PEN | RP23XX_RV_UART_UARTLCR_H_EPS)
#else
#error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
#endif
#endif
/* Get stop-bit setting for the console and UART0/1 */
#if defined(HAVE_CONSOLE)
#if CONSOLE_2STOP != 0
#define CONSOLE_LCR_STOP RP23XX_RV_UART_UARTLCR_H_STP2
#else
#define CONSOLE_LCR_STOP 0
#endif
#endif
/* LCR and FCR values for the console */
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_rp23xx_uart_lock = SP_UNLOCKED;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: riscv_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void riscv_lowputc(char ch)
{
#if defined HAVE_UART && defined HAVE_CONSOLE
/* Wait for the transmitter to be available */
while ((getreg32(CONSOLE_BASE + RP23XX_RV_UART_UARTFR_OFFSET) &
RP23XX_RV_UART_UARTFR_TXFF))
;
/* Send the character */
putreg32((uint32_t)ch, CONSOLE_BASE + RP23XX_RV_UART_UARTDR_OFFSET);
#endif
}
/****************************************************************************
* Name: rp23xx_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void rp23xx_lowsetup(void)
{
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
cr = getreg32(CONSOLE_BASE + RP23XX_RV_UART_UARTCR_OFFSET);
putreg32(cr & ~RP23XX_RV_UART_UARTCR_UARTEN,
CONSOLE_BASE + RP23XX_RV_UART_UARTCR_OFFSET);
putreg32(CONSOLE_LCR_VALUE,
CONSOLE_BASE + RP23XX_RV_UART_UARTLCR_H_OFFSET);
rp23xx_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
putreg32(0, CONSOLE_BASE + RP23XX_RV_UART_UARTIFLS_OFFSET);
putreg32(RP23XX_RV_UART_INTR_ALL,
CONSOLE_BASE + RP23XX_RV_UART_UARTICR_OFFSET);
cr |= RP23XX_RV_UART_UARTCR_RXE | RP23XX_RV_UART_UARTCR_TXE |
RP23XX_RV_UART_UARTCR_UARTEN;
putreg32(cr, CONSOLE_BASE + RP23XX_RV_UART_UARTCR_OFFSET);
#endif
}
/****************************************************************************
* Name: rp23xx_setbaud
*
****************************************************************************/
void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
{
uint32_t ibrd;
uint32_t fbrd;
uint32_t div;
uint32_t lcr_h;
irqstate_t flags = spin_lock_irqsave(&g_rp23xx_uart_lock);
div = basefreq / (16 * baud / 100);
ibrd = div / 100;
/* fbrd will be up to 63 ((99 * 64 + 50) / 100 = 6386 / 100 = 63) */
fbrd = (((div % 100) * 64) + 50) / 100;
/* Invalid baud rate divider setting combination */
if (ibrd == 0 || (ibrd == 65535 && fbrd != 0))
{
goto finish;
}
putreg32(ibrd, uartbase + RP23XX_RV_UART_UARTIBRD_OFFSET);
putreg32(fbrd, uartbase + RP23XX_RV_UART_UARTFBRD_OFFSET);
/* Baud rate is updated by writing to LCR_H */
lcr_h = getreg32(uartbase + RP23XX_RV_UART_UARTLCR_H_OFFSET);
putreg32(lcr_h, uartbase + RP23XX_RV_UART_UARTLCR_H_OFFSET);
finish:
spin_unlock_irqrestore(&g_rp23xx_uart_lock, flags);
}

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arch/risc-v/src/rp23xx-rv/rp23xx_uart.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/rp23xx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_UART_H
#define __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/rp23xx_uart.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
void rp23xx_lowsetup(void);
void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_RP23XX_RV_UART_H */

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