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arch/risc-v/src/mpfs/mpfs_coremmc: MPFS_FPGA_FIC0_CLK defined as config value

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Jari Nippula 2025-02-12 09:42:02 +02:00 • committed by Xiang Xiao
parent 96298efac8
commit 31f691e9ed
2 changed files with 7 additions and 1 deletions
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6
arch/risc-v/src/mpfs/Kconfig
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@ -397,6 +397,12 @@ config MPFS_COREMMC_WRCOMPLETE_IRQNUM
design, select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE and configure the
correct IRQ line here.
config MPFS_FPGA_FIC0_CLK_FREQ
int "FIC0 clk freq"
default 125000000
---help---
Frequency of FPGA FIC0 clock.
config MPFS_IHC_CLIENT
bool "IHC slave"
depends on RPTUN && !MPFS_BOOTLOADER

2
arch/risc-v/src/mpfs/mpfs_coremmc.c
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@ -125,7 +125,7 @@
/* Clocks and timing */
#define MPFS_FPGA_FIC0_CLK (125000000)
#define MPFS_FPGA_FIC0_CLK (CONFIG_MPFS_FPGA_FIC0_CLK_FREQ)
#define COREMMC_CMDTIMEOUT (100000)
#define COREMMC_LONGTIMEOUT (100000000)