This commit includes a change to the esp_txint function in the arch/risc-v/src/common/espressif/esp_usbserial.c file. The change primarily involves removing an optimization workaround and adding a call to flush the transmit FIFO.
After this change the usbserial config is able to work using all optimization levels.
Changes in esp_txint function:
Removed the __attribute__((optimize("O0"))) workaround.
Added a call to usb_serial_jtag_ll_txfifo_flush() at the beginning of the function.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
In the USB interface descriptor of the cdcacm device, class:2 (CDC)
subclass:2 (ACM) protocol:0 (NONE) may appear. At this time, the
usb host does not match the correct protocol byte, which will cause
the device identification to fail.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
It is now possible to configure SPI delays for st7789 controller if
CONFIG_SPI_DELAY_CONTROL is set. Default values for SPI peripheral
may be too long or too short, therefore the display controller set
its own values as required. The default values in configuration
are taken from the reference manual, but it is possible they may
require tuning for different revisions or temperatures for
example.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This PR adds support for the ESWIN EIC7700X RISC-V SoC.
This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.
Most of the code was derived from NuttX for SOPHGO SG2000 SoC.
The modified code is explained here:
https://lupyuen.github.io/articles/starpro64#appendix-port-nuttx-to-starpro64
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_EIC7700X for EIC7700X SoC
New Files in arch/risc-v:
include/eic7700x/chip.h: EIC7700X Definitions
include/eic7700x/irq.h: External Interrupts
src/eic7700x/chip.h: Interrupt Stack Macro
src/eic7700x/eic7700x_allocateheap.c: Kernel Heap
src/eic7700x/eic7700x_head.S: Linux Header and Boot Code
src/eic7700x/eic7700x_irq.c: Configure Interrupts
src/eic7700x/eic7700x_irq_dispatch.c: Dispatch Interrupts
src/eic7700x/eic7700x_memorymap.h: Memory Map
src/eic7700x/eic7700x_mm_init.c, eic7700x_mm_init.h: Memory Mgmt
src/eic7700x/eic7700x_pgalloc.c: Page Allocator
src/eic7700x/eic7700x_start.c: Startup Code
src/eic7700x/eic7700x_timerisr.c: Timer Interrupt
src/eic7700x/hardware/eic7700x_memorymap.h: PLIC and UART Base Address
src/eic7700x/hardware/eic7700x_plic.h: PLIC Register Addresses
src/eic7700x/Kconfig: EIC7700X Config
src/eic7700x/Make.defs: Makefile
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This PR adds support for the ESWIN EIC7700X RISC-V SoC.
This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.
Most of the code was derived from NuttX for SOPHGO SG2000 SoC.
The modified code is explained here:
https://lupyuen.github.io/articles/starpro64#appendix-port-nuttx-to-starpro64
platforms/risc-v/eic7700x/index.rst: Added EIC7700X SoC
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
The alloctab can be looped, if the first check the corresponding
bit is set, it will not continue to loop
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
This PR fixes the typos in the Code Comments of chip.h, allocateheap.c
and start.c. The typos were discovered here:
- https://github.com/apache/nuttx/pull/15921
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
add discard-data=on in proxy launch command, so the proxy side
will clean the share memory to make sure that the shared memory is clean
every time server and proxy are started.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
misc/rpmsgblk_server.c:135:16: warning: format '%d' expects argument of type 'int', but argument 3 has type 'int32_t' {aka 'long int'} [-Wformat=]
135 | ferr("block device open failed, ret=%d\n", msg->header.result);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~
| |
| int32_t {aka long int}
misc/rpmsgblk_server.c:135:48: note: format string is defined here
135 | ferr("block device open failed, ret=%d\n", msg->header.result);
| ~^
| |
| int
| %ld
misc/rpmsgblk_server.c: In function 'rpmsgblk_close_handler':
misc/rpmsgblk_server.c:170:16: warning: format '%d' expects argument of type 'int', but argument 3 has type 'int32_t' {aka 'long int'} [-Wformat=]
170 | ferr("block device close failed, ret=%d\n", msg->header.result);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~
| |
| int32_t {aka long int}
misc/rpmsgblk_server.c:170:49: note: format string is defined here
170 | ferr("block device close failed, ret=%d\n", msg->header.result);
| ~^
| |
| int
| %ld
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Use PRIu32 instead of %d/%u for uint32_t to avoid build warnings on different architectures.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Summary
Board logic change.
This PR adds weak_function attributes to the RP2040 common SPI board logic.
This allows board developers to override and extend the SPI board logic.
Signed-off-by: Kevin Witteveen (MartiniMarter) <kevinwit1999@gmail.com>
This commit improves the configuration of complementary PWM mode for
Tiva C-Series microcontrollers by moving the complementary flag
definition directly into each channel structure.
Changes made:
- Renamed 'complementary_generation' to 'complementary' for clarity.
- Moved complementary mode configuration into the static PWM
channel structures.
- Replaced runtime conditional checks with compile-time configuration
using '#ifdef CONFIG_TIVA_PWM_COMPLEMENTARY_Gx'.
- Improved readability and maintainability of the PWM driver.
These modifications ensure a more efficient initialization process,
reduce runtime conditionals, and align better with NuttX coding practices.
Signed-off-by: Sydeney Araujo <sydney.wagner39@gmail.com>
Added detailed information about the SX126x and its current state in development.
Added directories for wireless character driver and LPWAN.
Added indexes to each directory and its contents within.
Signed-off-by: Kevin Witteveen (MartiniMarter) <kevinwit1999@gmail.com>
[Experimental]
This adds a driver for the SX126x (SX1261 and SX1262) LoRa chips.
All functions and definitions are coming directly from the DS SX1261-2 V2.1 datasheet.
Signed-off-by: Kevin Witteveen (MartiniMarter) <kevinwit1999@gmail.com>
This ioctl clears the active fault inputs. Some faults can be latched
(still active even if the source is not active anymore), so they have
to be cleared from the software. The argument is a pointer to unsigned
long bitmask variable. This bitmask specifies which faults are to be
cleared.
The ioctl also can fetch the faults active prior to the clear. These
faults are saved to the argument specifying which faults are to be
cleared. Therefore passing zero bitmask means the driver will only return
active faults and clear none. Passing NULL pointer means the driver
will clear all active and return none.
The implementation of this ioctl is per driver.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The documentation concerns the cyclictest in apps/benchmarks/cyclictest.
The documentation describes the usage of the NuttX device timer
in this benchmark, the app usage and an example with an output.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Some improvements are made to the following commits:
| commit f22b93b337
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Fri Jan 31 07:01:07 2025 +0800
|
| sched/spin_lock: rename raw_spin_lock to spin_lock_notrace
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
`boot_stage_puts` used by early asm calls arm64_lowputc() for each
character in a loop. During that loop it uses x1 as the pointer to
the next character to be printed. However, x1 is clobbered by
arm64_lowputc(), resulting in undefined behaviour (only the first
character of the string is guaranteed to be printed).
Fix this by using x19 instead.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Following the https://github.com/apache/nuttx/pull/14741, add the
`ARCH_HAVE_RAMFUNCS` config to ESP32-C6 and ESP32-H2 to suppress
the RWX memory region warning.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
Now, espressif qemu supports MCUboot, so we can switch the app
format.
The build was failing with the legacy app format because
_ext_ram_bss_end and _ext_ram_bss_start are not defined in the
legacy linker file.
Update the wireless symbols from ESP32_* to ESPRESSIF_* for using common layer.
Remove ESP32 specific WiFi files and edit build system to use common layer.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, switch the pin mode to I2C at the end of the i2c
initialization function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, add clock gating process and disable GPIO input
to the I2C reset function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
