Return 0 for CPU ID for any hart ID, and return the current Hart ID for
any CPU ID. At least these values are somewhat usable / meaningful in
non-SMP configurations.
MPFS implements external interrupt control on a per-hart basis i.e. there
are PLIC control registers for each hart separately. This means we need
a procedure to initialize such registers for each hart individually,
instead of only for the boot hart like it is now.
Fix this by implementing mpfs_plic_init_hart which can be called by each
hart as needed.
Note: it is not a good idea to initialize all harts from the boot hart,
as the boot hart may not know which harts are used by NuttX in AMP
configuration. It is better that the hart initializes itself.
Note: The hartid must be provided as explicit parameter, as it cannot
be queried via riscv_mhartid() yet; the per-cpu structure is initialized
later on which means riscv_mhartid() would return 0 for all harts except
the boot hart.
that pr requires chip turn on CONFIG_DRIVERS_BLUETOOTH to use bluetooth,
but not all defconig enable this option, so let's map bt_driver_register
to bt_netdev_register in header file in this case, and revert the unnessary
change in the related chip and board folders.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
When sig dispatch do up_schedule_sigaction, need to make a new frame to
run arm_sigdeliver. But the exception_direct cannot handle xcp.regs as
we are using c-function exception handler.
Need to use exception_common to handle SMP call.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
Implement hartid<->cpuid mapping for RISC-V. This is necessary for some
platforms which cannot use 1:1 mapping between logical and physical CPU /
core IDs. One example is MPFS where hart0 cannot be used for NuttX SMP as
it is a less capable "monitor" core (E51) compared to the application
cores hart1...3 (E54).
Why not just use a generic offset then? We also need the physical hart ID
for many things:
- Communication between harts (IPI)
- External interrupt acknowledgment (interrupt claim for specific CPU)
- Communication to SBI
Thus, create procedures that can do this translation:
- The default mapping is still logical=physical.
- Another flavor is to use the existing CONFIG_ARCH_RV_HARTID_BASE config
variable, which is just a simple offset
- The final flavor is to overload hartid<->cpuid on a per chip basis (no
example for this is provided yet)
This implements empty hooks to the arch/chip layer, which can implement
an optional translation between logical<->physical CPU/core id.
The default mapping is 1:1 i.e. logical=physical.
The function is supposed to return the physical hart ID. It is needed
for e.g. external interrupt acknowledgment (see mpfs_plic.c).
This offset is moved initially to up_cpu_index (which is also wrong, but
less wrong than the current implementation). Finally, a translation
between physical <-> logical shall be provided.
this_task obtains the CPU ID through the GS register, so the initial value of GS needs to be configured in x86_64_cpu_priv_set
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
x86_64/intel64: fix SMP compilation warnings
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Implement PIC loading in armv8-m qemu,
for example: load address-independent AP ELF in the bootloader,
and the text segment in AP ELF is XIP,
no need to apply for memory and modify it.
Two config:
bootloader abbreviation bl:
use romfs to load ap elf, use the boot command to parse and jump to ap
application abbreviation ap:
run os test
We need to compile ap first, then compile bl.
compile step:
./tools/configure.sh mps3-an547:ap
make -j20
mkdir -p pic
cp boot pic/.
genromfs -a 128 -f ../romfs.img -d pic
make distclean -j20
./tools/configure.sh mps3-an547:bl
make -j20
run qemu:
qemu-system-arm -M mps3-an547 -m 2G -nographic -kernel nuttx.bin \
-gdb tcp::1127 -device loader,file=../romfs.img,addr=0x60000000
nsh> boot /etc/boot
ap> ostest
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Need to start up a new to setup special registers use
`arm_pic_setupxcp`.
Note that CONFIG_BUILD_PIC compiles the entire NuttX image
as position-independent(PIC), enable CONFIG_PIC to load PIC
application code.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The default heap management in nuttx returns a valid memory address when malloc(0).
In sim_heap, malloc(0) returns NULL, aligning the behavior of sim_heap with mm_heap
The man manual describes malloc as follows:
https://man7.org/linux/man-pages/man3/malloc.3.html
The malloc() function allocates size bytes and returns a pointer
to the allocated memory. The memory is not initialized. If size
is 0, then malloc() returns a unique pointer value that can later
be successfully passed to free(). (See "Nonportable behavior"
for portability issues.)
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
This commit addresses the issue of unauthorized writes to cntfrq_el0 during boot when not in EL3 mode.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
The segment of the Xen PVH boot protocol was not specified during linking and was placed before .loader.text, causing the boot to fail
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
