These archs only align the size of the stack, forgeting to do the
stack start addr alignment, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
Fix bug in temperature sensor driver where direct casting of lower half
structure pointer could lead to incorrect memory access.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Introduce EXT1 wakeup functionality to the ESP32-S3 power management
subsystem. With this feature, the ESP32-S3 can wake up from PM_STANDBY
or PM_SLEEP when one or more RTC GPIOs trigger the EXT1 condition.
Changes include:
- Added EXT1 wakeup configuration and preparation logic in rtc code.
- Integrated EXT1 handling in pmstandby() and pmsleep().
- New board-level Kconfig options under ESP32-S3 DevKit menu:
- CONFIG_PM_EXT1_WAKEUP: enable EXT1 wakeup support
- CONFIG_PM_EXT1_WAKEUP_RTC_GPIO<n>: select RTC GPIOs as wake sources
- CONFIG_PM_EXT1_WAKEUP_TRIGGER_MODE: choose wakeup on HIGH or LOW level
- Fixing Kconfig style
- Fixing comments standard
- Adding PM documentation for esp32s3-devkit
Impact:
- No build impact unless CONFIG_PM_EXT1_WAKEUP is enabled.
- When enabled, ESP32-S3 can wake from low-power states via RTC GPIOs.
- No new public API introduced; controlled via board Kconfig.
Tested on ESP32-S3 DevKit:
- Configured GPIO4 and GPIO5 as EXT1 wake sources.
- Verified wakeup from light sleep and deep sleep on external signals.
- Wakeup reason correctly reported as EXT1.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
Set the affinity of the task before activating it. There is no parameter
or other interface in "kthread_create" to set the affinity mask,
like in "pthread_create".
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Prior to this commit, it wasn't possible to load ELF modules from
the external PSRAM. There were two main issues about it: 1) copying
data using the instruction bus was being used instead of the data
bus (this, per si, isn't a problem, but requires special attention
regarding data alignment), and 2) the cache was not being properly
cleaned and flushed to properly access the loaded data using the
instruction bus.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
If both SPI Flash support (`CONFIG_ESP32S3_SPIFLASH`) and PSRAM
(`CONFIG_ESP32S3_SPIRAM`) are enabled, the PSRAM can only be
assigned to the user's heap (`CONFIG_ESP32S3_SPIRAM_USER_HEAP`).
Additionaly, `CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK` must be
set because the system will end up allocating tasks' stacks from
the external PSRAM. This has an impact when dealing with SPI flash
operations because the cache must be disabled and the running task
should not rely on any data from the PSRAM. To accomplish that, It
offloads the SPI flash operation to a work queue (which, by
definition, allocates its heap from the kernel heap).
The same (assigning the PSRAM to the user's heap) is valid when the
Wi-Fi is enabled because the lower-half driver requires data being
allocated from the internal memory (which can only be achieved by
allocating from the kernel heap when both the kernel and user heaps
exists).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[REG_PS]) will enable them if they were
enabled in the context.
Any interrupt on this cpu before xtensa_context_restore() would set
the rtcb->xcp.regs to NULL, causing a crash in context restore.
Fix this by calling leave_critical_section(up_irq_save()) instead.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
return early due to signal interruption (EINTR). This makes the
main thread think the async operation is done, but the background
worker thread is still running—risking access to freed memory,
race conditions, crashes or undefined behavior.
Using nxsem_wait_uninterruptible():the main thread waits until the
worker thread finishes, preventing these issues.
Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts. For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Previously, if an event was generated in hardware after taking spin
lock it was not correctly accounted for in current reading cycle.
Now, we check for events and compensate count accordingly.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Port fix from risc-v code. Providing original description:
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.
Fixed by enabling the associated interrupt events.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Original-fix-by: michal matias <mich4l.matias@gmail.com>
Decouples the NuttX build from the MCUBoot common source on Xtensa
devices. Allows using different branches for each.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This enables the use of the cryptographic accelerator within
the ESP32. The support algorithms are: SHA1, SHA256, SHA384
and SHA512.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
Or will be catch by codespell, when do checkpatch.sh
Also fix the relative comment file changed.
include/nuttx/scsi.h
drivers/syslog/ramlog.c
excluded as we have to modify field name in struct
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
The version and the git repository of Espressif's MCUboot port can
be changed by setting the `MCUBOOT_VERSION` and `MCUBOOT_URL`
environment variables before running the `make bootloader` command.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
with a fixed seq of 1, which causes ota_get_bootseq() to return ota_0.
The current solution is to directly use the target partition's number (num)
as next_seq to ensure the correct increment logic of seq. Ensure the formula
(seq-1) % OTA_DATA_NUM + OTA_IMG_BOOT_OTA_0 correctly maps to ota_0 or ota_1
Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
Modify types.h and inttypes.h to use the correct _int32_t and _uint32_t types.
Type is now defined according to recent compiler versions.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
