Added subclasses of STM32G0 (such as STM32G07X) to Kconfig for use in dmamux driver. Added definitions to stm32g0_dmamux.h. Added configuration of number of dma and dmamux channels.
Added missing dma mappings for stm32g0.
Remove reserved defines.
Formatting fixes.
Added DMA2 IRQ mappings for STM32G0B and STM32G0C. Changed STM32_DMAMUX_BASE to STM32_DMAMUX1_BASE to align with stm32_dma_v1mux.c and C0 defines.
Provide correct mapping for ADC1_DMA_CHAN. Add STM32F0L0G0_HAVE_ADC1_DMA to STM32G0.
Add support for continuous mode to the ADC. Also added support to set smp1 and smp2 in board.h, as well as smpsel.
Removed unnecessary selects of STM32F0L0G0_STM32G0. Changed board level files to properly define A0-A3 on nucleo-g0b1re.
Add new Kconfig changes.
Made combined configs for STM32G0. Ex. STM32G0BX for STM32G0B0 and STM32G0B1.
Fixed defines and references in Kconfig and stm32_dma_v1mux.c
Defined adc_sampletime_write and adc_sampletime_set. Changed adc_sample_time_s structure to be much simpler. Old way made no sense. You can only have 2 sample times, so defining one for each channel makes no sense. The new adc_sample_time_s contains smp1, smp2, and smpsel. Also define ADC_HAVE_SMPR_SMP2 for STM32C0.
Added adc_sampletime_write and adc_sampletime_set. Altered adc_sample_time_s structure to be more appropriate for g0 and c0. Only two sample times can be defined. Added rcc support for DMA2.
Added defconfig for nucleo-g0b1re:adc_dma config.
Restore correct Kconfig from my original branch
Removed redundant ifdefs. If we select for G0 and C0, we know they have SMP2. Fixed formatting.
Formatting feedback. Aligned columns in irq and dma headers.
When the vaddr parameter passed to map_region() is not aligned to the page directory,
it causes incorrect address mapping for later regions.
For example, in the sv32 case, `PGPOOL` started at `0x80a00000` with a size of `1024*4096B`,
leading to page table errors for the range `0x80c00000~0x80e00000`.
This patch fixes the issue by ensuring map_region() correctly handles unaligned vaddr cases.
Signed-off-by: wushenhui <wushenhui@xiaomi.com>
This commit fixes an issue when `CONFIG_DEBUG_SYSCALL_INFO=y`: the
`cmd` variable doesn't exist (instead, `regs[REG_A0]` represents
the syscall command directly. Also, it fixes the parameter for
`up_dump_register`, as `tcb` is a pointer here. By applying these
fixes, debugging syscall info is now possible again.
Previously, if an event was generated in hardware after taking spin
lock it was not correctly accounted for in current reading cycle.
Now, we check for events and compensate count accordingly.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Port fix from risc-v code. Providing original description:
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.
Fixed by enabling the associated interrupt events.
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Original-fix-by: michal matias <mich4l.matias@gmail.com>
Some code paths in drivers/serial/serial.c load head and tail values
of receive and transmit circular buffers with interrupts enabled,
making it possible that the interrupt handler changes the value.
As noted in the code, this is safe as long as the load itself is atomic.
That is not true for 8bit architectures which fetch the 16-bit values
using two load instructions. If interrupt handler runs between those
two instructions and changes the value, the read returns corrupted data.
This patch introduces CONFIG_ARCH_LDST_16BIT_NOT_ATOMIC configuration
option which is automatically selected for AVR architecture. Based
on this option, head and tail values are reduced to 8-bit length
so the read remains atomic.
Patch was tested by building on rv-virt:nsh - disassembly of functions
from serial.c showed no difference which is correct as Risc-V does
not need to protect reads of these values. There should be no impact
for architectures that do not set the new configuration option.
It was also tested by by custom echo application running on AVR128DA28.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
First commit of ADC for G0. Have it working basically. Need to make changes regarding adccmn stuff.
Added changes to make stm32_adc.c compatible with both G0 and other families.
Add oversampling support. This is for G0 and L0. Add ADC oversampling to Kconfig. Use adccmn_modifyreg for all, updated hw file to accomodate G0.
Style fixes. Move init of oversampling to a function, and call it if OVERSAMPLE is configured.
Limited changes to stm32_bringup.c
Style fixes to hardware/stm32_adc.h
Changed nucleo-g0b1re to run at 64 MHz. Fixed errors in clock setup. Added defines for setting up ADC clock.
Added code for STM32G0 ADC clock configuration.
Added adc_ckmode_cfg function. ckmode bits were previously neglected, assuming async clock to ADC was used. Added other feedback from pull request #16500.
Added feedback from pull request #16500.
Changed format of STM32F0L0G0_HAVE_ADC_OVERSAMPLE config.
Removed FARs from ioc_set_oversample.
Fixed formatting of helps in Kconfig. Adjusted spacing on help content.
Simplified adc_common_cfg. CCR_PRESC relies on board.h
Fixed formatting
Add ADC pinmaps for stm32g0
Add an option that configure the number of regular group conversions
that will trigger a DMA callback transfering data to the upper-half driver.
By default this value is 1 and the driver behaves the same as before
the change. Increasing this value allows to reduce the number of
DMA interrupts and achieve higher sampling rates.
DMA support for H5 and H7 is not complete so this change has no effect,
but for consistency they have also been modified.
The naming between ports has also been unified:
- dmabuffer -> r_dmabuffer
- nchannels -> rnchannels
- chanlist -> r_chanlist
- jchanlist -> j_chanlist
Signed-off-by: raiden00pl <raiden00@railab.me>
Decouples the NuttX build from the MCUBoot common source on RISC-V Espressif
devices. Allows using different branches for each.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Decouples the NuttX build from the MCUBoot common source on Xtensa
devices. Allows using different branches for each.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
This helps in debugging loaded elf files in CONFIG_BUILD_KERNEL. If a user space exception occurs,
one would beed the process name in order to debug the correct process/elf file.
Only dumping the pid and name of the crashed task/thread doesn't help, since different processes
may have helper threads with the same name.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
__start should call up_perf_init, initialization of hardware performance
counter, if CONFIG_ARCH_PERF_EVENTS option is set. This allows the
usage of ARM cycle count register DWT_CYCCNT in benchmark
measurements instead of software clock.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
A deadlock occurs for priv->lock when uart_xmitchars is called from
within imx9_txint. This is because uart_xmitchars does a callback to
imx9_txint and tries to acquire the lock again.
However, there is no reason to hold the lock over uart_xmitchars, as it
has its own lock for mutual exclusion. Only the UART device needs to
be protected, and priv->lock does that.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
For AVR, atomic functions generated by LOAD macro turn into load surrounded
by up_irq_save and up_irq_restore. The generated code was incorrect as can
be seen from disassembly of __atomic_load_4:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
out 0x3f, r18 ; restore the flag
movw r30, r24 ; copy parameter (address) to pointer register
ld r22, Z ; indirect load to return value registers
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
ret ; return
The interrupts are disabled to be immediately re-enabled, the load only takes
place after that.
Both up_irq_save and up_irq_restore are defined in inline assembly. Other
architectures (x86/486, Risc-V) mark this assembly with clobbers: memory.
Doing the same thing for AVR alleviates the problem:
in r18, 0x3f ; store interrupts enabled flag
cli ; disable interrupts
movw r30, r24 ; copy address
ld r22, Z ; load
ldd r23, Z+1
ldd r24, Z+2
ldd r25, Z+3
out 0x3f, r18 ; restore interrupts enabled flag
ret ; return
Besides compiling the code and checking the assembly, this was tested
with a custom stress application on AVR128DA28.
Assembly of up_irq_enable is marked in the same way with regards to clobbers.
This patch also removes two functions that are not called from anywhere
(up_irq_disabled, putsreg)
Signed-off-by: Kerogit <kr.git@kerogit.eu>
Changed copyright to apache copyright. Altered stm32_uid function to take uint32_t pointer instead of a twelve byte uint8_t array. Refined code in stm32_uid.c.
Fixed style and indentation.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
In singlewire mode the ops were only for non-dma usecases. But if rxdma is enabled we can use that.
For TXDMA it's not possible because we've to change pin direction immediately after transmission is done.
There is no more linking error for MPFS after the flagging is corrected in
drivers/timers/arch_alarm.c
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
For the RTL8211F PHY, configuration of RX/TXDLY was missing.
At least on my i.MX93 EVK, this is necessary for transmission
to work (RXDLY defaults to true on the PHY).
This commit brings support for RGMII internal delay configuration
(on or off for both directions) and enables it on the i.MX93 EVK
board. The introduced Kconfig is set to default to 'n', to avoid
breaking the functionality of other, out-of-tree boards based on
i.MX93, running the RTL8211F PHY, or to avoid introducing
unnecessary code on boards running other PHYs.
Configuration of internal delay on other PHYs is not
implemented, and results in a warning (but no error).
Signed-off-by: George Poulios <gpoulios@census-labs.com>
MUX_ENET1_TXC was missing from both the EVK board
definition and the IO muxing configuration function
of the ENET1 driver. As a result, transmission does
not work (unless the muxing is set by default in some
board? -not the case with EVK). This commit adds the
configuration and adds the definition to i.MX93 EVK.
WARN: other, out-of-tree i.MX93 boards need to define
MUX_ENET1_TXC accordingly, otherwise build will break.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Add up_perf_ functions for MPFS, which don't rely on alarm/oneshot interface.
Also add optimized up_udelay and up_ndelay functions, which use the MTIMER
directly to measure time; making them accurate and more multithreading friendly.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Bitfield CPHA has to be set to run SPI in mode 0. This is a default mode,
therefore it should be set during the peripheral initialization.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds a LPI2C driver for the mcx-nxxx chip, and the necessary board
definitions for the frdm-mcxn236 evaluation kit.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
FlexRAM peripheral was incorrectly clocked and turned during
M7 sleep. This patch fixes clock setting and ensure that clock
stays on during M7 for backdoor access from for example eDMA
Boards that run the i.MX9 bootloader at EL1 must not touch EL3-only
configuration. Add Kconfig guards so that:
* DDR training (IMX9_DDR_TRAINING)
* FIQ decode support (ARM64_DECODEFIQ)
are selected only when ARCH_ARM64_EXCEPTION_LEVEL == 3.
Code in arm64_chip_boot() is also guarded with ARCH_ARM64_EXCEPTION_LEVEL == 3
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
After `CONFIG_STACK_USAGE` enabled, no "*.su" file was generated, tools/showstack.sh output nothing.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
On rt10xx chips the MPU didn't got reset, which is needed for use
with bootloaders. Furthermore the TCM sizes where fixed now we use
kconfig symbol to set the size respectively. Also we mark ITCM as
RO/RO so we can't change data we executed from.
The up_saveusercontext function leverages USER_SAVE macro,
which is ordinarily used as a first half of the context switch.
This macro is therefore unsuitable to be used standalone,
it pops return address from the stack and does not return.
This patch adds missing instructions to do what would otherwise
be done by the second half of the context switch.
Tested by compiling and verifying the disassembly - the function
no longer falls through to the next function in the program memory,
push/pop instructions are balanced and stack contents preserved
Signed-off-by: Kerogit <kr.git@kerogit.eu>
This enables the use of the cryptographic accelerator within
the ESP32. The support algorithms are: SHA1, SHA256, SHA384
and SHA512.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
Fix case for CAN character driver in simulator when CANFD is disabled
and ch_edl field is not present in CAN header.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Interrupts should be disabled during the access to the user signature
area in internal flash memory, otherwise the system might be halted.
This applies also for read operation as this is performed with a
special flash commands on a special part of memory.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
