1. Rotate the video screen 90 degrees right.
2. Enable touchscreen for the LVGL configuration "lckfb-szpi-esp32s3:lvgl" and add lvgldemo autostart.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add touchscreen swap configuration for boards and enable it for defconfig that enables `FT5X06_SWAPXY`.
Refresh configurations to delete the deprecated `FT5X06_NPOLLWAITERS` and `FT5X06_SWAPXY`.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add support for mirror/swap coordinates.
There are some touchscreen drivers not support mirror or swap coordinates.
For example, drivers/input/ft5x06 does not support mirror.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
This commit makes it clear how to use the refresh.sh script to
update board configs showing differents usages cenarios.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts. For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Previous code was failing to disable error interrupts which
due to standard CAN retransmissions might trigger continusouly
(for example, with a disconnected CAN interface) flooding the
system and preventing other operations to continue.
Fixes: https://github.com/apache/nuttx/issues/16668
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
A descriptor ring length must be aligned to 128, one descriptor is 16B length,
so we can provide this condition with the appropriate number of descriptors
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Descriptor head is managed by HW and should not be modified by SW unless:
1. device is after a reset
2. device is before enabling TX or RX
Also set correct tail for RX which should point at the end of ring
(descriptor ring is zero-indexed).
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
Do not reset RX/TX rings when link status change.
This can break internal card state which is impossible to recovery.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
reset RX/TX rings **after** RX/TX are disabled to make sure the rings are
not used by hardware when software modify rings state.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
All implementations of gcov are sunk to the kernel implementation
1. Support three dump modes: serial port output, single file output, standard output
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Bringing the code coverage option when linking may cause gcc or g++ to automatically link the libgcov.a that comes with the toolchain.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Commit 83a119160 fixed SMP by removing call to uart_xmitchars from inside spinlock.
This only works for SMP, since uart_xmitchars has a lock only in SMP. In a single
core configuration the function can be called in parallel from the interrupt
handler and from the imx9_txint.
Fix this by filling the uart buffers already before enabling the
interrupt, this way it is not possible to get the function called in parallel
for the same device.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit adds the lowerhalf driver support for the I2C Slave.
While not currently ideal, it is compatible with the upperhalf i2c slave driver.
A workqueue can be used to delegate the isr work to the upperhalf driver.
But keep in mind wq introduces a lot of delay and in certain scenarios,
it is better to write your own better upperhalf driver.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
In file_read(), asynchronous reading is supported, so partial reads and the minread parameter are no longer needed.
Signed-off-by: zhongzhijie1 <zhongzhijie1@xiaomi.com>
In btuart_rxwork, There is no case for parsel HCI data of ISO type, but there are corresponding processes in the SIM and vendor driver code.
Signed-off-by: zhongzhijie1 <zhongzhijie1@xiaomi.com>
When the nread return value < 0, if the total length ntotal that has been read is > 0, the function returns ntotal; otherwise, it returns the nread error code.
Signed-off-by: zhongzhijie1 <zhongzhijie1@xiaomi.com>
Read as much data as possible initially, then process each packet individually. Defined the read buffer within the structure and added a rx_len variable to indicate the current read offset. After processing each complete packet, leftover data is moved to rxbuf[0] and rx_len is reduced by the length of the processed packet. The next packet process will start from rxbuf[0] after the read ends at new rxbuf[rx_len].
Signed-off-by: zhongzhijie1 <zhongzhijie1@xiaomi.com>
When initializing a memory block, the shadow area record of the first
memory block is used first.When uninitializing, unpoison is required, otherwise the memory will be marked incorrectly.
The following case will cause problems:
void *mem = malloc(1024);
struct mm_heap_s *a = mm_initialize("hello", mem, 1024);
int *b = mm_malloc(a, sizeof(int *));
*b = 100;
printf("Hello, World!! %d\n", *b);
mm_free(a, b);
mm_uninitialize(a);
free(mem);
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This product does not have MTE. MTE is only available for Arch or higher extensions of armv8-5+memory tags
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
