These archs only align the size of the stack, forgeting to do the
stack start addr alignment, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
The interrupt handler accesses the device as well as the driver's private
data. Use critical_section for mutual exclusion with drivers/usbdev, which
also protects the same data with critical_section.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
imx9_lpi2c_reset didn't quite work. It tried to toggle scl line as GPIO, but the line was not even muxed properly.
Instead, set the bus to relaxed mode, and drive address 0 to the bus. This toggles the clock, and also generates start and stop sequences on the bus.
"Relaxed mode" is a new feature on the LPI2C block used in imx93.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- In case of warm reboot, clear active and pending interrupts from GICv3
and also from the CPU interface.
- Fix default IGROUPMODR to the reset value (0)
- Move gic_wait_rwp calls to after modifying ICENABLER
- Improve some comments
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
When delivering a signal to a kernel task, or in CONFIG_BUILD_FLAT with MMU
enabled, the REG_SCTLR_EL1 needs to be stored for exception return.
Otherwise 0 is restored to the register at exception return, MMU is switched off
and the system crashes.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Align the writing style of arm cmake, and each compiler defines its own find library
function, otherwise use the default
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ
Signed-off-by: chao an <anchao.archer@bytedance.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Commit 83a119160 fixed SMP by removing call to uart_xmitchars from inside spinlock.
This only works for SMP, since uart_xmitchars has a lock only in SMP. In a single
core configuration the function can be called in parallel from the interrupt
handler and from the imx9_txint.
Fix this by filling the uart buffers already before enabling the
interrupt, this way it is not possible to get the function called in parallel
for the same device.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This product does not have MTE. MTE is only available for Arch or higher extensions of armv8-5+memory tags
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. Add hw_tags.c, which will call arm64_mte to implement tagging of memory blocks by operating registers
2. It has been able to run normally on the default NX memory allocator, excluding mempool and tlsf
3. On more complex configurations, memory tests such as memstress can run normally without system crashes
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
error: unpredictable STXR instruction, status is also a source
99 | "stxr %w0, %1, [%2] \n"
| ^
<inline asm>:5:10: note: instantiated into assembly here
5 | stxr w10, x10, [x9]
Using w0 to pass the result can cause the "status register is also a source" problem, resulting in unpredictable behavior.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The ARM64 instruction ADD has a 12-bit limit (0 - 4095) for immediate values, but here we try to use a symbolic address (.Linitparms) as an immediate value, which does not comply with the ARM64 instruction set rules.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
common/arm64_cache.c:305:38: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
A deadlock occurs for priv->lock when uart_xmitchars is called from
within imx9_txint. This is because uart_xmitchars does a callback to
imx9_txint and tries to acquire the lock again.
However, there is no reason to hold the lock over uart_xmitchars, as it
has its own lock for mutual exclusion. Only the UART device needs to
be protected, and priv->lock does that.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.
- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
select whether architecture specific up_perf_* functions are provided
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
For the RTL8211F PHY, configuration of RX/TXDLY was missing.
At least on my i.MX93 EVK, this is necessary for transmission
to work (RXDLY defaults to true on the PHY).
This commit brings support for RGMII internal delay configuration
(on or off for both directions) and enables it on the i.MX93 EVK
board. The introduced Kconfig is set to default to 'n', to avoid
breaking the functionality of other, out-of-tree boards based on
i.MX93, running the RTL8211F PHY, or to avoid introducing
unnecessary code on boards running other PHYs.
Configuration of internal delay on other PHYs is not
implemented, and results in a warning (but no error).
Signed-off-by: George Poulios <gpoulios@census-labs.com>
MUX_ENET1_TXC was missing from both the EVK board
definition and the IO muxing configuration function
of the ENET1 driver. As a result, transmission does
not work (unless the muxing is set by default in some
board? -not the case with EVK). This commit adds the
configuration and adds the definition to i.MX93 EVK.
WARN: other, out-of-tree i.MX93 boards need to define
MUX_ENET1_TXC accordingly, otherwise build will break.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Boards that run the i.MX9 bootloader at EL1 must not touch EL3-only
configuration. Add Kconfig guards so that:
* DDR training (IMX9_DDR_TRAINING)
* FIQ decode support (ARM64_DECODEFIQ)
are selected only when ARCH_ARM64_EXCEPTION_LEVEL == 3.
Code in arm64_chip_boot() is also guarded with ARCH_ARM64_EXCEPTION_LEVEL == 3
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
After `CONFIG_STACK_USAGE` enabled, no "*.su" file was generated, tools/showstack.sh output nothing.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
This implements an interrupt-based SPI driver for the BCM2711 SPI
interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0
since proprietary firmware does not initialize any other SPI interfaces,
and doing so will require reverse engineering.
- Add ELE command to initialize the ELE RNG context.
- Add ELE command to poll the readiness of the RNG
- Add ELE command to obtain random numbers.
- Replace AHAB_ prefixes with ELE_
- Cleanup header includes
- Added some explanatory comments on .../hardware/imx9_ele.h
Signed-off-by: Theodore Karatapanis <tkaratapanis@census-labs.com>
