The functions `hw_write_masked` and `hw_xor_bits` (as defined in
pico-sdk) were defined in NuttX twice.
Additionally these definitions were in conflict (one lacked the
`volatile` modifier).
Now these functions and their dependencies are defined in a new header
file.
Its name is based on the filename of the original definition in
pico-sdk:
src/rp2_common/hardware_base/include/hardware/address_mapped.h
This change should fix the potential issue of GPIO operations failing
due to compiler optimizations caused by the absence of `volatile`.
Signed-off-by: Lars Kruse <devel@sumpfralle.de>
Since the alignment of the signal context is affected by XCPTCONTEXT_SIZE in
different Kconfig, sometimes the stack pointer is not aligned to 8 bytes, this
is not what the software and compiler expect, for example, if va_list() obtains
wide data of type long long, the offset will be wrong, So in this commit, we set
stack-aligned the base offset so that the correct offset will be set during context
restoration.
1. test code:
| void signal_handler(int signo, siginfo_t *info, void *context) {
| long long ttt = 1024000;
| printf("%lld\n", ttt);
| }
|
| struct itimerspec its = { .it_value.tv_sec = 1,
| .it_value.tv_nsec = 0,
| .it_interval.tv_sec = 1,
| .it_interval.tv_nsec = 0
| };
|
| int main(int argc, FAR char *argv[])
| {
| struct sigevent evp;
| timer_t timer_id;
|
| memset(&evp, 0, sizeof(evp));
| evp.sigev_notify = SIGEV_SIGNAL | SIGEV_THREAD_ID;
| evp.sigev_signo = SIGALRM;
| evp.sigev_notify_thread_id = gettid();
|
| timer_create(CLOCK_REALTIME, &evp, &timer_id);
|
|
| struct sigaction sa;
| memset(&sa, 0, sizeof(sa));
| sa.sa_sigaction = signal_handler;
| sa.sa_flags = SA_SIGINFO;
| sigemptyset(&sa.sa_mask);
|
| sigaction(SIGALRM, &sa, NULL);
|
| timer_settime(timer_id, 0, &its, NULL);
|
| while (1)
| sleep(1);
|
| return 0;
| }
2. before this change:
| NuttShell (NSH) NuttX-12.10.0
| nsh> hello
| 4398046527890440
| 4398046527890472
| 4398046527890504
| 4398046527890536
3. after this change:
| NuttShell (NSH) NuttX-12.10.0
| nsh> hello
| 1024000
| 1024000
| 1024000
| 1024000
Signed-off-by: chao an <anchao.archer@bytedance.com>
The stack alignment operation in tricore and arm porting
only aligns the size of the stack, forget to align the start addr
of the stack, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
These archs only align the size of the stack, forgeting to do the
stack start addr alignment, this patch fixes it.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
The interrupt handler accesses the device as well as the driver's private
data. Use critical_section for mutual exclusion with drivers/usbdev, which
also protects the same data with critical_section.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This patch addresses several issues and adds enhancements to the WWDG
(Window Watchdog) implementation for the STM32H7 platform. The changes
include:
- Extend the definitions of WWDG_CFR_PCLK1 macros to support dividers
up to 128, and update the stm32_settimeout() function to consider this
extended range.
- Fix the "elapsed" calculations in the stm32_getstatus() function to
ensure correct time remaining calculations.
- Clear the EWIF (Early Wakeup Interrupt Flag) bit in the stm32_start()
function, as this bit might be set by hardware before the watchdog is
actually started.
- Initialize the WWDG clock in the RCC_APB3ENR register and set the
RCC_GCR_WW1RSC bit as per the STM32 reference manual to ensure proper
behavior when enabling the WWDG1.
Signed-off-by: Szymon Magrian <szymon.magrian@hexagon.com>
Fix bug in temperature sensor driver where direct casting of lower half
structure pointer could lead to incorrect memory access.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Fix bug in temperature sensor driver where direct casting of lower half
structure pointer could lead to incorrect memory access.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Give the user the full control over the USIC FIFO buffer even if USIC channel 0 is disabled.
When USICx_CHAN0 is not an UART but USICx_CHAN1 is, the user can set the desired FIFO buffer offsets in CHAN1 config.
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Port of https://github.com/apache/nuttx/pull/16848
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Fixes low and inconsistent bandwidth issues.
Adds new configuration options for buffer management.
Moves code around to make the implementation cleaner and easier to debug.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The following warning occurred if ARCH_CHIP_PIC32CZCA70 option was
selected. The variable is not used in case of PIC32CZ CA70 series.
CC: task/task_getgroup.c chip/sam_emac.c: In function ‘sam_emac_initialize’:
chip/sam_emac.c:4758:12: warning: unused variable ‘regval’ [-Wunused-variable]
4758 | uint32_t regval;
|
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
"tc397" is a chip name which is not appropriate to act as a board name.
the board supported here is actually "a2g-tc397-5v-tft".
The correct definition is : tricore is arch name, tc3xx is arch family
name, tc397 is chip name and the borad name is a2g-tc397-5v-tft
imx9_lpi2c_reset didn't quite work. It tried to toggle scl line as GPIO, but the line was not even muxed properly.
Instead, set the bus to relaxed mode, and drive address 0 to the bus. This toggles the clock, and also generates start and stop sequences on the bus.
"Relaxed mode" is a new feature on the LPI2C block used in imx93.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This removes the need to have all the DDR/clock configuration related
"LIBERODEFS" flags defined, when not building a standalone/coldboot
configuration
All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Introduce EXT1 wakeup functionality to the ESP32-S3 power management
subsystem. With this feature, the ESP32-S3 can wake up from PM_STANDBY
or PM_SLEEP when one or more RTC GPIOs trigger the EXT1 condition.
Changes include:
- Added EXT1 wakeup configuration and preparation logic in rtc code.
- Integrated EXT1 handling in pmstandby() and pmsleep().
- New board-level Kconfig options under ESP32-S3 DevKit menu:
- CONFIG_PM_EXT1_WAKEUP: enable EXT1 wakeup support
- CONFIG_PM_EXT1_WAKEUP_RTC_GPIO<n>: select RTC GPIOs as wake sources
- CONFIG_PM_EXT1_WAKEUP_TRIGGER_MODE: choose wakeup on HIGH or LOW level
- Fixing Kconfig style
- Fixing comments standard
- Adding PM documentation for esp32s3-devkit
Impact:
- No build impact unless CONFIG_PM_EXT1_WAKEUP is enabled.
- When enabled, ESP32-S3 can wake from low-power states via RTC GPIOs.
- No new public API introduced; controlled via board Kconfig.
Tested on ESP32-S3 DevKit:
- Configured GPIO4 and GPIO5 as EXT1 wake sources.
- Verified wakeup from light sleep and deep sleep on external signals.
- Wakeup reason correctly reported as EXT1.
Signed-off-by: Thiago Finelon <thiago.sfinelon@gmail.com>
- In case of warm reboot, clear active and pending interrupts from GICv3
and also from the CPU interface.
- Fix default IGROUPMODR to the reset value (0)
- Move gic_wait_rwp calls to after modifying ICENABLER
- Improve some comments
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Set the affinity of the task before activating it. There is no parameter
or other interface in "kthread_create" to set the affinity mask,
like in "pthread_create".
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This arch uses code relocation to SRAM through a XIP unit, so forcing segment
permissions manually in the linker script could create unforeseen issues.
A quick fix is setting the "--no-warn-rwx-segments" linker option just for
for the incriminated stage2 bootloader binary.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
fix nooptimiziation_function definition problem for tricore gnu compiler
arch/tricore:
move tricore_csa2addr and tricore_addr2csa definition from include/arch.h to include/irq.h to fix build error
Version 2.2.0 of the SDK unified some headers under a new path.
Now both the old and the new paths are searched during compilation.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Prior to this commit, it wasn't possible to load ELF modules from
the external PSRAM. There were two main issues about it: 1) copying
data using the instruction bus was being used instead of the data
bus (this, per si, isn't a problem, but requires special attention
regarding data alignment), and 2) the cache was not being properly
cleaned and flushed to properly access the loaded data using the
instruction bus.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
If both SPI Flash support (`CONFIG_ESP32S3_SPIFLASH`) and PSRAM
(`CONFIG_ESP32S3_SPIRAM`) are enabled, the PSRAM can only be
assigned to the user's heap (`CONFIG_ESP32S3_SPIRAM_USER_HEAP`).
Additionaly, `CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK` must be
set because the system will end up allocating tasks' stacks from
the external PSRAM. This has an impact when dealing with SPI flash
operations because the cache must be disabled and the running task
should not rely on any data from the PSRAM. To accomplish that, It
offloads the SPI flash operation to a work queue (which, by
definition, allocates its heap from the kernel heap).
The same (assigning the PSRAM to the user's heap) is valid when the
Wi-Fi is enabled because the lower-half driver requires data being
allocated from the internal memory (which can only be achieved by
allocating from the kernel heap when both the kernel and user heaps
exists).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
The interrupt handler accesses the device as well as the driver's private
data. Thus, must take the big kernel lock in SMP mode to protect them.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
In SMP mode one CPU can be executing the MMC interrupt while another CPU
disables (e.g. via watchdog timeout). As it is disabled the other CPU
assumes it's safe to start configuring the device after this.
This causes a leak in the driver's private data as well as a mutual
exclusion leak on the device itself.
Fix this by aborting any triggered interrupt by checking whether it's
even enabled.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Currently the irq handler checks many reserved bits, which is
a waste of resources:
1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
rest are reserved
Fix this by checking only the relevant bits.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
As emmcsd driver does not support separate WRCOMPLETE interrupt the
SDIOWAIT_WRCOMPLETE event shall not be waited.
The SDIOWAIT_TRANSFERDONE event indicates that both "transfer done"
and "write complete" events are completed.
