Commit graph

2031 commits

Author SHA1 Message Date
Stepan Pressl
637f15ff3c Make/Toolchain.defs: add the AR_EXTRACT command
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.

Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
2025-08-19 09:47:44 +08:00
Ville Juven
67b17cb4d7 mpfs/mpfs_usb.c: Fix interrupt handling in SMP mode
The interrupt handler accesses the device as well as the driver's private
data. Thus, must take the big kernel lock in SMP mode to protect them.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-18 20:27:20 +08:00
Ville Juven
72bba3b2ee mpfs_emmcsd/coremmc.c: Fix interrupt handling in SMP mode
In SMP mode one CPU can be executing the MMC interrupt while another CPU
disables (e.g. via watchdog timeout). As it is disabled the other CPU
assumes it's safe to start configuring the device after this.

This causes a leak in the driver's private data as well as a mutual
exclusion leak on the device itself.

Fix this by aborting any triggered interrupt by checking whether it's
even enabled.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-18 20:27:20 +08:00
Serg Podtynnyi
2437771de5 boards/risc-v/rp23xx-rv/common: update board reset via BOOTROM functions
Update board reset with BOOTROM functions calls
 - normal reboot
 - reboot to bootloader

normal reboot and reboot bootloader now possible from nsh

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-16 08:56:21 -03:00
Eero Nurkkala
581d667f72 risc-v/mpfs: usb: don't try nonexistent ep int flags
Currently the irq handler checks many reserved bits, which is
a waste of resources:

1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
   defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
   rest are reserved

Fix this by checking only the relevant bits.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-16 08:41:59 -03:00
Jukka Laitinen
85f6f4bca2 arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reserved IO area in protected build
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2025-08-15 09:18:34 -03:00
Jari Nippula
93c1e0c633 arch/risc-v/src/mpfs/mpfs_emmcsd: ignore WRCOMPLETE
As emmcsd driver does not support separate WRCOMPLETE interrupt the
SDIOWAIT_WRCOMPLETE event shall not be waited.
The SDIOWAIT_TRANSFERDONE event indicates that both "transfer done"
and "write complete" events are completed.
2025-08-15 02:23:23 +08:00
Jari Nippula
31f691e9ed arch/risc-v/src/mpfs/mpfs_coremmc: MPFS_FPGA_FIC0_CLK defined as config value 2025-08-15 02:23:23 +08:00
Jari Nippula
96298efac8 arch/risc-v/src/mpfs/mpfs_coremmc: clock, buswidth and fifo depth fixed
4bit bus width support and FIC0 clock is 125MHz
VR register fifo depth bitfields 5:4 instead of 3:2
2025-08-15 02:23:23 +08:00
Jari Nippula
5020572871 arch/risc-v/src/mpfs/mpfs_coremmc: Remove data line check from sendcmd
mpfs_sendcmd() shall not wait for data lines ready before
sending commands to the card. This prevents mmcsd driver
to poll card busy status prior to next activity after
a write operation.
2025-08-15 02:23:23 +08:00
Serg Podtynnyi
2e7f75f6e0 arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)
Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-11 08:56:27 +08:00
Eren Terzioglu
1c0e1698cd bugix/risc-v/esp32c6: Fix build error of LP_I2C
Fix build error of LP_I2C for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-08-05 08:00:12 -03:00
Jukka Laitinen
9cda3ce216 arch/*/*_sigdeliver.c: Fix a race condition is signal delivery for SMP
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.

After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-04 21:11:13 +08:00
Martin Vajnar
150854c6f2 ESP_PCNT: add high and low limit Kconfig options
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
2025-07-22 13:09:02 -03:00
Filipe Cavalcanti
3468c8e0cf arch/risc-v: change offset for SPI Flash on Espressif devices
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-22 10:55:08 -03:00
Eren Terzioglu
f07141244c arch/risc-v: Bugfix I2C Slave build error for esp32[-c3|-c6|-h2]
Fix build error for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:18:06 +08:00
Eren Terzioglu
8995226e0a arch/risc-v: Add LP I2C for esp32[-c6]
Add LP I2C peripheral support for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:18:06 +08:00
Eren Terzioglu
8e44c85a3a arch/risc-v: Add arch layer SHA accelerator support for esp32[-c3|-c6|-h2]
Add arch layer SHA accelerator support for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:13:06 +08:00
Eren Terzioglu
d8f241b29d Documentation/risc-v/esp32[c6]: Add LP_UART support docs
Add LPUART support doc for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-08 19:35:54 +08:00
Eren Terzioglu
1c48c0cba7 arch/risc-v/esp32[c6]: Add LP_UART support
Add LP_UART support for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-08 19:35:54 +08:00
Filipe Cavalcanti
06b37fe6aa arch/risc-v: set SCL timeout for esp_i2c.c
Adds proper timeout settings to SCL on ESP32C3|C6|H2.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-08 11:04:05 +08:00
Eren Terzioglu
3f65182699 arch/risc-v: Change DMA functions with common layer approach for esp32[-c3|-c6|-h2]
Change DMA functions with common layer functions for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-07 23:46:07 +08:00
Filipe Cavalcanti
e57d2a5247 arch/risc-v: update lower-half drivers for ESP32-C3|C6|H2 2025-06-30 22:40:26 +08:00
wangmingrong1
e97e33eadc toolchain: Support KASAN compilation above Clang18
1. When the Clang compiler turns on "-fsanitize=kernel-address", inlining, global variables, and stack detection are enabled by default and must be turned off manually.
2. -mllvm is the parameter passing method of Clang, and --param is the parameter passing method of GCC
After the modification, KASan compilation and operation will be supported for Clang 18 and above

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-06-26 20:31:19 +08:00
wushenhui
6a9a835d6f risc-v/mmu: Fix map_region() for incorrect page table setup when vaddr is unaligned
When the vaddr parameter passed to map_region() is not aligned to the page directory,
it causes incorrect address mapping for later regions.

For example, in the sv32 case, `PGPOOL` started at `0x80a00000` with a size of `1024*4096B`,
leading to page table errors for the range `0x80c00000~0x80e00000`.

This patch fixes the issue by ensuring map_region() correctly handles unaligned vaddr cases.

Signed-off-by: wushenhui <wushenhui@xiaomi.com>
2025-06-23 15:44:39 +08:00
Tiago Medicci Serrano
a98f7a1045 arch/risc-v: Fix debugging syscall info
This commit fixes an issue when `CONFIG_DEBUG_SYSCALL_INFO=y`: the
`cmd` variable doesn't exist (instead, `regs[REG_A0]` represents
the syscall command directly. Also, it fixes the parameter for
`up_dump_register`, as `tcb` is a pointer here. By applying these
fixes, debugging syscall info is now possible again.
2025-06-22 14:57:11 +08:00
Martin Vajnar
0c9931cc99 espressif[risc-v|xtensa]: Check events when reading PCNT counter value
Previously, if an event was generated in hardware after taking spin
lock it was not correctly accounted for in current reading cycle.

Now, we check for events and compensate count accordingly.

Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
2025-06-20 20:51:49 +08:00
Filipe Cavalcanti
2912b3347c arch/risc-v: decouple common source for Espressif's MCUBoot port
Decouples the NuttX build from the MCUBoot common source on RISC-V Espressif
devices. Allows using different branches for each.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-06-14 17:11:58 +08:00
Jukka Laitinen
5aa45e328e arch/riscv/ricv_exception.c: Dump the process name at exception in user space
This helps in debugging loaded elf files in CONFIG_BUILD_KERNEL. If a user space exception occurs,
one would beed the process name in order to debug the correct process/elf file.

Only dumping the pid and name of the crashed task/thread doesn't help, since different processes
may have helper threads with the same name.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-06-13 20:36:30 +08:00
Jukka Laitinen
dd07367f4e arch/riscv/Kconfig: Remove select "ARCH_PERF_EVENTS" from Kconfig
There is no more linking error for MPFS after the flagging is corrected in
drivers/timers/arch_alarm.c

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-06-06 17:31:10 +08:00
Jukka Laitinen
56ad0d6837 arch: Flag all definitions of up_perf_* functions with CONFIG_ARCH_HAVE_PERF_EVENTS
Use the flag CONFIG_ARCH_HAVE_PERF_EVENTS to detect whether the architecture specific code
provides the up_perf_* functions. Now it is mixed with CONFIG_ARCH_PERF_EVENTS, which should
select just whether the perf events (perf_*) are enabled for the configuration.

- drivers/timers/arch_alarm.c: Don't compile the up_perf_* functions here if the
  CONFIG_ARCH_HAVE_PERF_EVENTS is defined
- arch/*/*_perf.c: Change CONFIG_ARCH_PERF_EVENTS -> CONFIG_ARCH_HAVE_PERF_EVENTS to
  select whether architecture specific up_perf_* functions are provided

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-06-06 17:31:10 +08:00
Jukka Laitinen
0ac580cb7a arch/risc-v/mpfs: Add optimized perf timer functions for mpfs
Add up_perf_ functions for MPFS, which don't rely on alarm/oneshot interface.

Also add optimized up_udelay and up_ndelay functions, which use the MTIMER
directly to measure time; making them accurate and more multithreading friendly.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-06-04 20:48:03 -03:00
simbit18
ad93c6c399 arch/risc-v/src/qemu-rv/CMakeLists.txt: removed repeated addition of the file qemu_rv_userspace.c
9897ef3cdb/arch/risc-v/src/qemu-rv/CMakeLists.txt (L44)

aligned with the make.def file

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-06-03 10:03:49 -03:00
raiden00pl
194b635739 arch: unify Private Types banners
unify Private Types banners according to NuttX coding standard

Signed-off-by: raiden00pl <raiden00@railab.me>
2025-05-28 10:17:15 +08:00
wangzhi16
35a62b7d5e Revert "Reduce the size of tcb by four bytes."
This reverts commit 893c5e92c2.
2025-05-27 16:30:35 +08:00
Lars Kruse
3dc53adb28 arch | boards | drivers: fix whitespace issues for switch case statements 2025-05-23 10:48:41 +08:00
Lars Kruse
3ce85ca54e style: fix spelling in code comments and strings 2025-05-23 10:48:41 +08:00
Martin Vajnar
a3d0411c24 Select SENSORS_QENCODER as dependency for Quadrature Encoder mode of PCNT unit 2025-05-16 11:10:29 -03:00
Martin Vajnar
abac610d13 xtensa|espressif: Unify Quadrature Encoder handling among units 2025-05-16 11:10:29 -03:00
michal matias
e115c4364e arch/risc-v/src/common/espressif/esp_pcnt.c: counter accumulation fix
Even when enabled, the PCNT counter doesn't accumulate into the 32-bit value.
Instead, a value in range [PCNT_LOW_LIMIT, PCNT_HIGH_LIMIT] is always returned.
This is due to interrupt events associated with limit overflows are disabled on the periphery,
therefore the ISR responsible for the accumulation never gets called.

Fixed by enabling the associated interrupt events.

Signed-off-by: michal matias <mich4l.matias@gmail.com>
2025-05-16 10:36:00 +08:00
Eren Terzioglu
b7bbb56338 arch/risc-v: Add Dedicated GPIO support for esp32[c3|c6|h2]
Add Dedicated GPIO support for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-14 19:38:21 +02:00
Eren Terzioglu
466e63d554 arch/risc-v: Add SDM support for esp32[-c3|-c6|-h2]
Add SDM peripheral support for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-09 19:20:47 +08:00
Tiago Medicci Serrano
c22df41ca6 espressif: Add variable to override MCUboot version and URL
The version and the git repository of Espressif's MCUboot port can
be changed by setting the `MCUBOOT_VERSION` and `MCUBOOT_URL`
environment variables before running the `make bootloader` command.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-05-07 01:51:40 +08:00
Eren Terzioglu
5cc7046a7f arch/risc-v/espressif: Fix Serial IFLOW build issue
Serial IFLOW build error fixed for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-05 23:47:05 +08:00
Eren Terzioglu
929c6313ff arch/risc-v/espressif: Add RS485 support for esp32[c3|c6|h2]
Add RS485 support for Risc-V based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-05-05 23:47:05 +08:00
Jinliang Li
5ce0e93637 arch/risc-v: save/restore fpu registers always when CONFIG_ARCH_LAZYFPU is off
To fix a fpu illegal instruction exception due to fcsr have invalid
rounding-mode,  restore fcsr/f0~f31 with a random value from stack because fpu
context is not save into stack when mstatus.fs is clean(not dirty).

The number of save/restore fpu context operations is not equal.
In fact, CONFIG_ARCH_LAZYFPU is a performance optimization mechanism aimed at
minimizing the saving and restoring of FPU registers. In some cases, it
may only need to be saved once but must be restored multiple times.
Therefore, this optimization mechanism dictates that saving cannot be
done on the stack; it must be stored at a fixed location(e.g. task
control block buffer), as the stack requires push/pop operations to be
matched.

In case of that CONFIG_ARCH_LAZYFPU is off, save/restore FPU registers
always into stack to avoid the above issues.

Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
2025-04-27 13:08:29 +08:00
Leo Chung
5a1426d632 risc-v/esp32h2:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Leo Chung
931d80683d risc-v/esp32c3:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Leo Chung
d314329792 risc-v/esp32c6:Fix bootloader flash compiler error.
Add missing bootloader_enable_qio_mode() function in flash_qio_mode.c when
CONFIG_ESPRESSIF_FLASH_MODE_QIO option is enabled.

Signed-off-by: Leo Chung <gewalalb@gmail.com>
2025-04-23 16:16:47 +08:00
Tiago Medicci Serrano
c566cf51a2 risc-v/esp32c3: Fix getting the flash mappings by openocd-esp32
This adds new fields to the metadata section used by MCUBoot.
The openocd-esp32 project requires these fields to properly map the
flash segments and enable using SW breakpoints and flash through
openocd-esp32.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
2025-04-18 02:25:14 +08:00