add missing itm_syslog.h include for archs that use itm_syslog_initialize()
to fix compiler errors:
error: implicit declaration of function 'itm_syslog_initialize'
Issue reported by rentzboy in https://github.com/apache/nuttx/issues/16017
Signed-off-by: raiden00pl <raiden00@railab.me>
Add support for the STM32H5 ICACHE peripheral. The CortexM33 does not have typical embedded icache and dcache. Instead STM32H5 provides the ICACHE as a separate peripheral that needs to be configured. This commit adds the stm32h5 specific icache driver. This driver named functions like those in <nuttx/cache.h>. However since the CortexM33 does not have cache itself, ARCH_ICACHE is not enabled. Therefore these stm32h5 specific functions were developed.
Signed-off-by: kywwilson11 <kwilson@2g-eng.com>
I found an issue when using SPI with nbits=8: SPI reads return unreliable
results because SPI ignores nbits value and always performs 16-bit reads.
Signed-off-by: Daniel Martín Gómez <danielmartingomez@geotab.com>
ifdelay description (delay between frames) matches the DLYBCT field
(delay between consecutive transfers without removing chip select)
much better compared to stopdelay (delay between last CLK and CS
innactive). The option for stopdelay does not seem to be configurable
in SAMv7 peripheral.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This PR fixes the typos in the Code Comments of chip.h, allocateheap.c
and start.c. The typos were discovered here:
- https://github.com/apache/nuttx/pull/15921
Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
This commit improves the configuration of complementary PWM mode for
Tiva C-Series microcontrollers by moving the complementary flag
definition directly into each channel structure.
Changes made:
- Renamed 'complementary_generation' to 'complementary' for clarity.
- Moved complementary mode configuration into the static PWM
channel structures.
- Replaced runtime conditional checks with compile-time configuration
using '#ifdef CONFIG_TIVA_PWM_COMPLEMENTARY_Gx'.
- Improved readability and maintainability of the PWM driver.
These modifications ensure a more efficient initialization process,
reduce runtime conditionals, and align better with NuttX coding practices.
Signed-off-by: Sydeney Araujo <sydney.wagner39@gmail.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, switch the pin mode to I2C at the end of the i2c
initialization function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, add clock gating process and disable GPIO input
to the I2C reset function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
DTE (dead time enable) is the 17th bit in CMRx (channel mode) register.
Function pwm_set_polarity did however read and write this register as
16 bit large, therefore dead time generation was always disabled.
This fixes the issue, pwm_set_polarity now reads the register as 32
large.
Also set the initial value of CMRx correctly in pwm_setup().
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds configuration option for every fault input, that can be
latched (kept even after the input value is below the threshold) or
volatile (PWM is automatically enabled once the output polarity goes
back to the normal state).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART
An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
When the l1entry first add to shm, mssing l1entry add.
shm mmu flags should use udata flags.
l1entry record in shm[] and should not use ~SECTION_MASK
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
chip/sam_1wire.c:921:7: warning: implicit declaration of function 'sam_usart0_enableclk' [-Wimplicit-function-declaration]
921 | sam_usart0_enableclk();
The same warning applied for other uart/usart peripherals configured
as 1 wire.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds support to TIOCGICOUNT for STM32, this way a
userspace application can collect information about UART errors.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Fixes bug where stm32_phyinit will succeed even when no PHY is connected. This is because there is no check that a PHY is actually communicating and returning data.
Update include/nuttx/net/mii.h
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
This selects ARM_THUMB for ARMV7R per ARM document:
https://developer.arm.com/documentation/dui0471
Thanks to hujun260 for spotting this, now ostest works.
Why it helps is still to be clarified, the `arm_signal_handler.S`
might require this THUMB option.
To keep ARM_THUMB as option, this only selects it for
PROTECTED as per anchao's suggestion.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds up_allocate_heap() support for PROTECTED mode so that
kernel and user heap sizes match memory.ld linker script.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes task start syscall in PROTECTED mode, following that
of armv7-m so that hello and getprime programs can run smoothly.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds MPU and userspace handling in QEMU chips so that to
boot PROTECTED target qemu-armv7r:pnsh.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This copies struct mpu_region_s from armv7-m to fix PROTECTED mode
build error: `invalid use of undefined type 'struct mpu_region_s'`
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
