[Experimental]
This adds a driver for the SX126x (SX1261 and SX1262) LoRa chips.
All functions and definitions are coming directly from the DS SX1261-2 V2.1 datasheet.
Signed-off-by: Kevin Witteveen (MartiniMarter) <kevinwit1999@gmail.com>
This ioctl clears the active fault inputs. Some faults can be latched
(still active even if the source is not active anymore), so they have
to be cleared from the software. The argument is a pointer to unsigned
long bitmask variable. This bitmask specifies which faults are to be
cleared.
The ioctl also can fetch the faults active prior to the clear. These
faults are saved to the argument specifying which faults are to be
cleared. Therefore passing zero bitmask means the driver will only return
active faults and clear none. Passing NULL pointer means the driver
will clear all active and return none.
The implementation of this ioctl is per driver.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The documentation concerns the cyclictest in apps/benchmarks/cyclictest.
The documentation describes the usage of the NuttX device timer
in this benchmark, the app usage and an example with an output.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Some improvements are made to the following commits:
| commit f22b93b337
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Fri Jan 31 07:01:07 2025 +0800
|
| sched/spin_lock: rename raw_spin_lock to spin_lock_notrace
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
`boot_stage_puts` used by early asm calls arm64_lowputc() for each
character in a loop. During that loop it uses x1 as the pointer to
the next character to be printed. However, x1 is clobbered by
arm64_lowputc(), resulting in undefined behaviour (only the first
character of the string is guaranteed to be printed).
Fix this by using x19 instead.
Signed-off-by: George Poulios <gpoulios@census-labs.com>
Following the https://github.com/apache/nuttx/pull/14741, add the
`ARCH_HAVE_RAMFUNCS` config to ESP32-C6 and ESP32-H2 to suppress
the RWX memory region warning.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
Now, espressif qemu supports MCUboot, so we can switch the app
format.
The build was failing with the legacy app format because
_ext_ram_bss_end and _ext_ram_bss_start are not defined in the
legacy linker file.
Update the wireless symbols from ESP32_* to ESPRESSIF_* for using common layer.
Remove ESP32 specific WiFi files and edit build system to use common layer.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, switch the pin mode to I2C at the end of the i2c
initialization function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, add clock gating process and disable GPIO input
to the I2C reset function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Many STM32L4 boards are missing stm32_bringup.c. That confusion
was created when stm32_appinit.c was created. It introduced a new
way to do the board initialization without depending on NSH arch
specific initialization.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This commit disables optimization that alters ESP32C6 interrupt registers.
Without this optimization, the USB serial driver does not work properly.
This is a temporary workaround until a proper fix is found.
Signed-off-by: Felipe Moura de Oliveira <moura.fmo@gmail.com>
If st7789_wrram is called with count = 1, then the entire buffer should
be sent. However, in 3 wire mode, the driver has to send the buffer
row by row because of additional data flag. The number of rows (count)
can't be ST7789_YRES in this case, but only the number of rows in
the buffer (this is write size / row size , where row size is
ST7789_XRES * ST7789_BYTESPP). This also applies only if we want to
write size larger than row size, because st7789_putrun allows to
write just a part of a row.
This fixes the incorrect behavior of the display in 3 wire mode if
the display is split into more buffer writes (as in LCD driver for
example, FB driver did not face this issue).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Martin Krasula <krasula@atlas.cz>
DTE (dead time enable) is the 17th bit in CMRx (channel mode) register.
Function pwm_set_polarity did however read and write this register as
16 bit large, therefore dead time generation was always disabled.
This fixes the issue, pwm_set_polarity now reads the register as 32
large.
Also set the initial value of CMRx correctly in pwm_setup().
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit implements re-enabling the cache before the exception
handler for ESP32-S3 and removes unnecessary checks (cache should
always be re-enabled during an exception handler and disabled again
after processed, except for ESP32-S3 that implements no recoverable
exceptions).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This adds configuration option for every fault input, that can be
latched (kept even after the input value is below the threshold) or
volatile (PWM is automatically enabled once the output polarity goes
back to the normal state).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- Move PLIC interrupt enable and disable functions into mpfs_plic.c
- When enabling interrupts, always clear pending interrupt
- Remove race conditions between irq enable/disable by adding spinlock
- An interrupt may trigger on one hart in the middle of enabling the interrupts - then the interrupt
handler might call up_disable_irq.
A pending interrupt would trigger immediately when enabling the interrupt source,
but this is not expected. The interrupt source is level sensitive, so it should
only trigger if the source is active at the time when it is enabled. Not if it
was active sometime in the past.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
If CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is defined, the coremmc driver
uses SD card's dat0 line to detect whether the sd card is still busy.
This requires that the FPGA design using coremmc block wires dat0 line
to some fabric irq; and configures CONFIG_MPFS_COREMMC_WRCOMPLETE_IRQNUM
to point to that. Default for the irq number is 4. (MSS_INT_F2M_4)
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
We should not modify the input actions, casing when kernel build,
userspace call posix_spawn touch kernel address.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART
An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
Update the handling of tcp packets over sixlowpan. `tcp_ipv6_input()`
can update the dev->d_iob. Assigning ipv6 to IPv6BUF makes sure that
the correct buffer is used.
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
