Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Port of https://github.com/apache/nuttx/pull/16848
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
The following warning occurred if ARCH_CHIP_PIC32CZCA70 option was
selected. The variable is not used in case of PIC32CZ CA70 series.
CC: task/task_getgroup.c chip/sam_emac.c: In function ‘sam_emac_initialize’:
chip/sam_emac.c:4758:12: warning: unused variable ‘regval’ [-Wunused-variable]
4758 | uint32_t regval;
|
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This arch uses code relocation to SRAM through a XIP unit, so forcing segment
permissions manually in the linker script could create unforeseen issues.
A quick fix is setting the "--no-warn-rwx-segments" linker option just for
for the incriminated stage2 bootloader binary.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Version 2.2.0 of the SDK unified some headers under a new path.
Now both the old and the new paths are searched during compilation.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
Add capture source files to the makefile pipeline.
STM32H7_CAP to STM32H7_TIMX_CAP for clarity.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
Add documentation for changes made in #16809.
Add an example defconfig for a nsh build with the capture example.
Replace the STM32H7_CAP option with just CAPTURE as the guard for the
lower half driver.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
Enabling a higher channel of the internal ADC had the effect of
initializing the lower ones as well. Now that happens only if
actively requested.
Also, the functions for handling the internal ADC did not follow
the typical naming used by comparable modules for the same arch
and were renamed for coherence. Informational logging calls were
also made slightly more useful and discernible in case of having
multiple ADCs.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Add support for the RP2040's GPIO output override capabilities.
Implementation inspired by the uniqueid functions for the same arch.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
The strings "RPC2040" and "RP2040_IO_BANK0_GPIO0", presumably typos,
were used in place of respectively "RP2040" and "RP2040_IO_BANK0_GPIO".
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
This patch fixes an incorrect call to stm32_cap_initialize() in
stm32_bringup.c: the call was made without the channel parameter.
Instead of adding the channel in the call, the channel is selected by
stm32_cap_gpio() (first available channel).
This patch also fixes incorrect driver registration in
drivers/timers/capture.c: the driver was registered with the wrong
name (/dev/cap -> /dev/capture). Also added more error checking in
cap_register_multiple().
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
This PR add support to USBHOST on iMXRT1052 ARCX-Socket-Grid board
and add a USBDISK board config example.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This commit introduces a timer capture driver for the STM32H7 series
ported from the STM32 F series.
The main changes include:
- A new generic timer capture driver for STM32H7.
- A lower-half driver to integrate with the NuttX capture subsystem.
- Kconfig options to enable and configure capture for various timers.
- Pin definitions for TIM1-4 capture inputs on the nucleo-h743zi.
- An update to `cap_register_multiple` to handle multiple device registration.
- An update to `stm32_bringup` to register the capture drivers.
The current implementation is based on a driver originally for PWM input,
and as such, it calculates duty cycle and frequency. It is also limited
to a single capture channel per timer.
The original implementation's `stm32_cap_init` in
`arch/arm/src/stm32h7/stm32_capture.c` has been modified to accept a
channel number instead of using a hardcoded 0 through
`STM32_CAP_CHANNEL_COUNTER`.
This serves as a foundation for future development of more comprehensive
input capture capabilities on STM32H7 platforms.
Tested by polling and reading `/dev/cap0-4` with
`ioctl(fds[i], CAPIOC_FREQUENCE, freq)` while sending a square wave signal to
appropriate pins and checking frequency.
Also tested by bypassing upper half driver and setting up capture on
TIM4 channels 1-4 as explained in #16762.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Clear dma interrupt flags as before.
Change HTEF to HTF, fixes typo.
Remove ALL_FLAGS define. Clear CXFCR with all 1s like other instances do.
Handle half-transfer interrupt only if in circular mode.
Add ADC_HAVE_DMA guard around adc_rstart_dma. It is needed because priv->circular is guarded by ADC_HAVE_DMA.
Many iMXRT MCUs have internally two USB OTG controllers, however
NuttX currently only supports one USB controllers. This patch will
prepare the "house" to support both ports at same time.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- Committing initial code for DTS. Missing ISR. Works for PCLK1. Cannot get to work for LSE.
- Pushing everything. Working with LSE now.
- Many fixes. Fixed interrupt setting. Added data structures.
- Changed interrupt handling. Removed FARs. Added Kconfig options for selecting interrupts.
- Updated info and formatting.
- Formatting fixes.
- Formatting.
- Changed iten to regval.
- Removed Triggger
- Formatting fixes per Pull request.
- Changed private_types to have stm32_ prefix. Used depends on for DTS Kconfig Menu. Fixed formatting per PR.
- Fixed spacing of function prototypes.
- Fixed indent on line
- Added documentation for STM32H5 and Nucleo-H563ZI regarding DTS. Also added GPDMA support to STM32H5 documentation (previous PR). Made stm32_dts.c more modular. stm32_dts_activate is now much more readable. Added comments/descriptions to private functions. Lastly, added a nucleo-h563zi:dts configuration.
Set level high for unused interrupt trigger to avoid waking up from cold sleeping.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
1. -target should be in front, otherwise clang will not be able to find the corresponding libgcc.a
2. When using clang++ compiler to link, you also need to specify the corresponding arch, otherwise ld.lld will report an error due to arch mismatch.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
In the toolchain, ARCH_TOOLCHAIN_XXX is used to select the compiler to be used. If clang is selected here, subsequent errors will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Added logic to set hasdma to false. This is needed to enable or not enable interrupts on a per ADC basis. Made other minor formatting changes.
Fixed build issues with non ADC/DMA configurations.
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Previous code was failing to disable error interrupts which
due to standard CAN retransmissions might trigger continusouly
(for example, with a disconnected CAN interface) flooding the
system and preventing other operations to continue.
Fixes: https://github.com/apache/nuttx/issues/16668
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
This commit adds the lowerhalf driver support for the I2C Slave.
While not currently ideal, it is compatible with the upperhalf i2c slave driver.
A workqueue can be used to delegate the isr work to the upperhalf driver.
But keep in mind wq introduces a lot of delay and in certain scenarios,
it is better to write your own better upperhalf driver.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
