boards/Board.mk: update romfs image generation

Introduce support in CMake to ignore specific directories
added by `nuttx_add_subdirectory()`. This provides more
flexibility for build configuration and allows excluding
unwanted or optional components.

* Improves modularity of project configuration.

Signed-off-by: trns1997 <trns1997@gmail.com>

.codespellrc

@@ -8,6 +8,7 @@ exclude-file = .codespell-ignore-lines
 # Ignore complete files (e.g. legal text or other immutable material).
 skip =
   LICENSE,
+  */CODEOWNERS,
 
 # Ignore seemingly misspelled words.
 #   lowercase: case insensitive

.github/PULL_REQUEST_TEMPLATE.md

@@ -13,9 +13,21 @@
 
 ## Testing
 
-*Update this section with details on how did you verify the change,
+*This section should provide a detailed description of what you did
- what Host was used for build (OS, CPU, compiler, ..), what Target was
+to verify your changes work and do not break existing code.*
- used for verification (arch, board:config, ..), etc. Providing build
- and runtime logs from before and after change is highly appreciated.*
 
+*Please provide information about your host machine, the board(s) you
+tested your changes on, and how you tested. Logs should be included.*
 
+*For example, when changing something in the core OS functions, you
+may want to run the OSTest application to verify that there are no
+regressions. Changes to ADC code may warrant running the `adc`
+example. Adding a new uORB driver may require that you run
+`uorb_listener` to verify correct operation.*
+
+*Pure documentation changes can just be tested with `make html`
+(see docs) and verification of the correct format in your
+browser.*
+
+**_PRs without testing information will not be accepted. We will
+request test logs._**

.github/workflows/build.yml

@@ -17,8 +17,10 @@ on:
     paths-ignore:
       - 'AUTHORS'
       - 'CONTRIBUTING.md'
+      - '**/CODEOWNERS'
       - 'Documentation/**'
       - 'tools/ci/docker/linux/**'
+      - 'tools/codeowners/*'
   push:
     paths-ignore:
       - 'AUTHORS'
@@ -199,6 +201,51 @@ jobs:
           path: buildartifacts/
         continue-on-error: true
 
+  # Test the out-of-tree build
+  OOT-Build:
+    needs: Linux
+    runs-on: ubuntu-latest
+    env:
+      DOCKER_BUILDKIT: 1
+    steps:
+      - name: Download Source Artifact
+        uses: actions/download-artifact@v5
+        with:
+          name: source-bundle
+          path: .
+
+      - name: Extract sources
+        run: tar zxf sources.tar.gz
+
+      - name: Docker Login
+        uses: docker/login-action@v3
+        with:
+          registry: ghcr.io
+          username: ${{ github.actor }}
+          password: ${{ secrets.GITHUB_TOKEN }}
+
+      - name: Export NuttX Repo SHA
+        run: echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV
+
+      - name: Run Out-of-Tree Build Test
+        uses: ./sources/nuttx/.github/actions/ci-container
+        env:
+          BLOBDIR: /tools/blobs
+        with:
+          run: |
+            echo "::add-matcher::sources/nuttx/.github/gcc.json"
+            git config --global --add safe.directory /github/workspace/sources/nuttx
+            git config --global --add safe.directory /github/workspace/sources/apps
+            cd sources/nuttx
+            ./tools/ci/cibuild-oot.sh
+
+      - uses: actions/upload-artifact@v4
+        if: ${{ always() }}
+        with:
+          name: oot-build-artifacts
+          path: sources/apps/testing/cxx-oot-build
+        continue-on-error: true
+
   # Select the macOS Builds based on PR Arch Label
   macOS-Arch:
     uses: apache/nuttx/.github/workflows/arch.yml@master
@@ -243,7 +290,7 @@ jobs:
 
       # Released version of Cython has issues with Python 11. Set runner to use Python 3.10
       # https://github.com/cython/cython/issues/4500
-      - uses: actions/setup-python@v5
+      - uses: actions/setup-python@v6
         with:
           python-version: '3.10'
       - name: Run Builds
@@ -304,7 +351,7 @@ jobs:
             zlib-devel
             cmake
             ninja
-            python-pip 
+            python-pip
             vim
 
       - name: pip3 install
@@ -359,7 +406,7 @@ jobs:
       - uses: actions/checkout@v5
       # Set up Python environment and install kconfiglib
       - name: Set up Python and install kconfiglib
-        uses: actions/setup-python@v5
+        uses: actions/setup-python@v6
         with:
           python-version: '3.10'
       - name: Install kconfiglib

.github/workflows/doc.yml

@@ -36,7 +36,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v5
-      - uses: actions/setup-python@v5
+      - uses: actions/setup-python@v6
         with:
           python-version: '3.8'
       - name: Generate Documentation

.github/workflows/issue_labeler.yml

@@ -23,7 +23,7 @@ jobs:
       issues: write
     steps:
       - name: Add labels issues automatically based on their body.
-        uses: actions/github-script@v7
+        uses: actions/github-script@v8
         with:
           script: |
             const body = context.payload.issue.body;

CMakeLists.txt

@@ -53,6 +53,13 @@ if(POLICY CMP0169)
   cmake_policy(SET CMP0169 OLD)
 endif()
 
+# Find Python 3 interpreter
+
+find_package(Python3 REQUIRED COMPONENTS Interpreter)
+if(NOT Python3_Interpreter_FOUND)
+  message(FATAL_ERROR "Did NOT find Python interpreter.")
+endif()
+
 # Basic CMake configuration ##################################################
 
 set(CMAKE_CXX_EXTENSIONS OFF)
@@ -447,17 +454,67 @@ endif()
 # Setup platform options (this needs to happen after project(), once the
 # toolchain file has been processed)
 
-# Support custom Toolchain options by custom Boards
+# Support board Toolchain options
-if(CONFIG_ARCH_BOARD_CUSTOM)
+if(EXISTS ${NUTTX_BOARD_ABS_DIR}/cmake
-  if(EXISTS ${NUTTX_BOARD_ABS_DIR}/cmake
+   AND EXISTS ${NUTTX_BOARD_ABS_DIR}/cmake/Toolchain.cmake)
-     AND EXISTS ${NUTTX_BOARD_ABS_DIR}/cmake/Toolchain.cmake)
+  # must be added AFTER ToolchainFile and BEFORE platform
-    # must be added AFTER ToolchainFile and BEFORE platform
+  include(${NUTTX_BOARD_ABS_DIR}/cmake/Toolchain.cmake)
-    include(${NUTTX_BOARD_ABS_DIR}/cmake/Toolchain.cmake)
-  endif()
 endif()
 
 include(platform)
 
+if(CONFIG_ARCH_TOOLCHAIN_TASKING)
+  if(CONFIG_INTELHEX_BINARY)
+    add_link_options(-Wl-onuttx.hex:IHEX:4 --hex-format=s)
+  endif()
+
+  if(CONFIG_MOTOROLA_SREC)
+    add_link_options(-Wl-onuttx.srec:SREC:4)
+  endif()
+endif()
+
+if(MSVC)
+  add_compile_options(
+    -W2
+    -wd4116 # unnamed type definition in parentheses
+    -wd4146 # unary minus operator applied to unsigned type, result still
+            # unsigned
+    -wd4244 # 'argument' : conversion from 'type1' to 'type2', possible loss of
+            # data
+    -wd4305 # 'context' : truncation from 'type1' to 'type2'
+  )
+elseif(NOT CONFIG_ARCH_TOOLCHAIN_TASKING)
+  add_compile_options(
+    # system wide warnings
+    -Wall $<$<COMPILE_LANGUAGE:C>:-Wstrict-prototypes> -Wshadow -Wundef
+    # system wide options
+    $<$<COMPILE_LANGUAGE:ASM>:-D__ASSEMBLY__>)
+endif()
+
+if(CONFIG_NDEBUG)
+  add_compile_options(-DNDEBUG)
+endif()
+
+# Cmake build provide absolute paths to compile files. If __FILE__ macros are
+# used in the source code(ASSERT), the binary will contain many invalid paths.
+# This saves some memory, stops exposing build systems locations in binaries,
+# make failure logs more deterministic and most importantly makes builds more
+# failure logs more deterministic and most importantly makes builds more
+# deterministic. Debuggers usually have a path mapping feature to ensure the
+# files are still found.
+if(NOT MSVC)
+  if(CONFIG_OUTPUT_STRIP_PATHS)
+    add_compile_options(-fmacro-prefix-map=${NUTTX_DIR}=)
+    add_compile_options(-fmacro-prefix-map=${NUTTX_APPS_DIR}=)
+    add_compile_options(-fmacro-prefix-map=${NUTTX_BOARD_ABS_DIR}=)
+    add_compile_options(-fmacro-prefix-map=${NUTTX_CHIP_ABS_DIR}=)
+  endif()
+endif()
+
+add_definitions(-D__NuttX__)
+
+add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-D__ASSEMBLY__>)
+
 # Setup main nuttx target ####################################################
 
 add_executable(nuttx)
@@ -515,48 +572,6 @@ else()
     nuttx PRIVATE $<GENEX_EVAL:$<TARGET_PROPERTY:nuttx,NUTTX_COMPILE_OPTIONS>>)
 endif()
 
-if(MSVC)
-  add_compile_options(
-    -W2
-    -wd4116 # unnamed type definition in parentheses
-    -wd4146 # unary minus operator applied to unsigned type, result still
-            # unsigned
-    -wd4244 # 'argument' : conversion from 'type1' to 'type2', possible loss of
-            # data
-    -wd4305 # 'context' : truncation from 'type1' to 'type2'
-  )
-elseif(NOT CONFIG_ARCH_TOOLCHAIN_TASKING)
-  add_compile_options(
-    # system wide warnings
-    -Wall $<$<COMPILE_LANGUAGE:C>:-Wstrict-prototypes> -Wshadow -Wundef
-    # system wide options
-    $<$<COMPILE_LANGUAGE:ASM>:-D__ASSEMBLY__>)
-endif()
-
-if(CONFIG_NDEBUG)
-  add_compile_options(-DNDEBUG)
-endif()
-
-# Cmake build provide absolute paths to compile files. If __FILE__ macros are
-# used in the source code(ASSERT), the binary will contain many invalid paths.
-# This saves some memory, stops exposing build systems locations in binaries,
-# make failure logs more deterministic and most importantly makes builds more
-# failure logs more deterministic and most importantly makes builds more
-# deterministic. Debuggers usually have a path mapping feature to ensure the
-# files are still found.
-if(NOT MSVC)
-  if(CONFIG_OUTPUT_STRIP_PATHS)
-    add_compile_options(-fmacro-prefix-map=${NUTTX_DIR}=)
-    add_compile_options(-fmacro-prefix-map=${NUTTX_APPS_DIR}=)
-    add_compile_options(-fmacro-prefix-map=${NUTTX_BOARD_ABS_DIR}=)
-    add_compile_options(-fmacro-prefix-map=${NUTTX_CHIP_ABS_DIR}=)
-  endif()
-endif()
-
-add_definitions(-D__NuttX__)
-
-add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-D__ASSEMBLY__>)
-
 set_property(
   TARGET nuttx
   APPEND
@@ -625,7 +640,7 @@ process_all_directory_romfs()
 get_property(ldscript GLOBAL PROPERTY LD_SCRIPT)
 
 # Pre-compile linker script
-if(NOT CONFIG_ARCH_SIM AND NOT CONFIG_ARCH_TOOLCHAIN_TASKING)
+if(NOT CONFIG_ARCH_SIM)
   get_filename_component(LD_SCRIPT_NAME ${ldscript} NAME)
   set(LD_SCRIPT_TMP "${CMAKE_BINARY_DIR}/${LD_SCRIPT_NAME}.tmp")
 

Documentation/ReleaseNotes/NuttX-12.11.0

@@ -0,0 +1,390 @@
+NuttX-12.11.0
+------------
+
+What's New In This Release
+Major Changes to Core OS
+Sched
+* [#16554](https://github.com/apache/nuttx/pull/16554) sched: assert: Print Stack pointer value when not within the stack
+* [#16673](https://github.com/apache/nuttx/pull/16673) sched: Fix smp scheduling
+* [#16919](https://github.com/apache/nuttx/pull/16919) sched/init/nx_bringup.c: Add support for CONFIG_INIT_NONE in a flat build
+* [#16927](https://github.com/apache/nuttx/pull/16927) sched/signal: Old signal action need save sa_user
+* [#16481](https://github.com/apache/nuttx/pull/16481) sched/wdog: Replace periodical timer with the wd_start_next.
+* [#16545](https://github.com/apache/nuttx/pull/16545) sched/wqueue: Fix windows compilation errors.
+* [#16593](https://github.com/apache/nuttx/pull/16593) sched/wqueue: Fix windows compilation errors.
+MM
+* [#16617](https://github.com/apache/nuttx/pull/16617) mm: add CONFIG_MM_NODE_GUARDSIZE option
+* [#16653](https://github.com/apache/nuttx/pull/16653) mm/Kasan: Fixed some bugs
+libc
+* [#16568](https://github.com/apache/nuttx/pull/16568) libc: Change atomic_fetch_cxx to macro
+* [#16768](https://github.com/apache/nuttx/pull/16768) libc: fix assert "Free memory from the wrong heap" with flat mode and…
+* [#16713](https://github.com/apache/nuttx/pull/16713) libc/idr: Fix Use-After-Free during idr_destroy()
+* [#16675](https://github.com/apache/nuttx/pull/16675) libc/mcount: add armv6m mcount implementation
+* [#16811](https://github.com/apache/nuttx/pull/16811) libs/libc/netdb: Optimize the DNS timeout calculation logic
+* [#16932](https://github.com/apache/nuttx/pull/16932) libs/libc/semaphore:  allow nxsem_init to negative value
+* [#16614](https://github.com/apache/nuttx/pull/16614) libbuiltin/gcov: Upgrade gcov function
+* [#16786](https://github.com/apache/nuttx/pull/16786) Revert "libs/libc/stdlib/lib_exit.c: fix multiple definition of __dso…
+Tools
+* [#16563](https://github.com/apache/nuttx/pull/16563) tools: Modify refresh.sh to support update all configs from a board
+* [#16650](https://github.com/apache/nuttx/pull/16650) tools/checkpatch.sh: add -x option to auto-format Python files.
+* [#16912](https://github.com/apache/nuttx/pull/16912) tools/checkpatch.sh: check git commit format
+* [#16724](https://github.com/apache/nuttx/pull/16724) tools/espressif: Add risc-v compiler info dump for Espressif devices
+* [#16763](https://github.com/apache/nuttx/pull/16763) tools/nix: Add Nix flake for reproducible dev environment
+* [#16924](https://github.com/apache/nuttx/pull/16924) tools/nix: move nix flakes to tools/
+* [#16831](https://github.com/apache/nuttx/pull/16831) tools/nix: split flake into root and Documentation
+* [#16759](https://github.com/apache/nuttx/pull/16759) tools/nxstyle.c: Updating white list to xedge example
+* [#16855](https://github.com/apache/nuttx/pull/16855) tools/rp{2040,23xx}: Ensure that picotool is found or built
+* [#16667](https://github.com/apache/nuttx/pull/16667) tools/process_config.sh: Fix sed errors
+* [#16546](https://github.com/apache/nuttx/pull/16546) tools/testbuild.ps1: Windows fix the redirect error stream
+* [#16711](https://github.com/apache/nuttx/pull/16711) toolchain/arm: Fix crash caused by clang compiling with -mfpu=fpv5-d16 and -march=armv8.1-m.main+mve.fp+fp.dp
+* [#16709](https://github.com/apache/nuttx/pull/16709) toolchain/arm: Fix link parameter error
+* [#16720](https://github.com/apache/nuttx/pull/16720) toolchain/armclang: Fix armclang config
+
+Build System
+Improvements
+* [#16880](https://github.com/apache/nuttx/pull/16880) arch: Add Cmake build support for raspberrypi-4b board & bcm2711 chip
+* [#16475](https://github.com/apache/nuttx/pull/16475) arch/arm/src/mcx-nxxx/CMakeLists.txt: Aligned Cmake with Make
+* [#16579](https://github.com/apache/nuttx/pull/16579) arch/arm/src/mcx-nxxx/CMakeLists.txt: Aligned Cmake with Make
+* [#16647](https://github.com/apache/nuttx/pull/16647) arch/arm64/fvp-v8r: support cmake compile
+* [#16581](https://github.com/apache/nuttx/pull/16581) arch/risc-v/src/qemu-rv/CMakeLists.txt: removed repeated addition of …
+* [#16477](https://github.com/apache/nuttx/pull/16477) arch/risc-v/src/qemu-rv/CMakeLists.txt: removed repeated addition of the file qemu_rv_userspace.c
+* [#16794](https://github.com/apache/nuttx/pull/16794) arm: CMake build for the i.MX RT series implemented.
+* [#16627](https://github.com/apache/nuttx/pull/16627) Arm32 v8m support cmake clang compile
+* [#16922](https://github.com/apache/nuttx/pull/16922) boards/arm/imxrt: CMake added imxrt1020-evk imxrt1050-evk boards
+* [#16918](https://github.com/apache/nuttx/pull/16918) boards/arm/imxrt: CMake added imxrt1060-evk imxrt1064-evk imxrt1170-evk boards
+* [#16639](https://github.com/apache/nuttx/pull/16639) cmake/arm64:   support clang compile
+* [#16547](https://github.com/apache/nuttx/pull/16547) cmake(bugfix):fix VERSION genarator strip error in CMake build
+* [#16594](https://github.com/apache/nuttx/pull/16594) cmake(bugfix):fix VERSION genarator strip error in CMake build
+* [#16751](https://github.com/apache/nuttx/pull/16751) cmake(bugfix):add default c++ search path
+* [#16897](https://github.com/apache/nuttx/pull/16897) Cmake: add defconfig preprocess capability in Cmake build environment(recursively expand #include)
+* [#16721](https://github.com/apache/nuttx/pull/16721) cmake: enhance the function of cmake nuttx_wildcard_sources
+* [#16867](https://github.com/apache/nuttx/pull/16867) drivers/analog/CMakeLists.txt: Aligned Cmake with Make
+* [#16870](https://github.com/apache/nuttx/pull/16870) drivers/audio/CMakeLists.txt: Aligned Cmake with Make
+* [#16873](https://github.com/apache/nuttx/pull/16873) drivers/ioexpander/CMakeLists.txt: Aligned Cmake with Make
+* [#16871](https://github.com/apache/nuttx/pull/16871) drivers/leds/CMakeLists.txt: Aligned Cmake with Make
+* [#16913](https://github.com/apache/nuttx/pull/16913) drivers/net/CMakeLists.txt: Aligned Cmake with Make
+* [#16620](https://github.com/apache/nuttx/pull/16620) drivers/segger/CMakeLists.txt: Aligned Cmake with Make
+* [#16633](https://github.com/apache/nuttx/pull/16633) drivers/segger/CMakeLists.txt: Aligned Cmake with Make
+* [#16616](https://github.com/apache/nuttx/pull/16616) drivers/sensors/CMakeLists.txt: Aligned Cmake with Make
+* [#16634](https://github.com/apache/nuttx/pull/16634) drivers/sensors/CMakeLists.txt: Aligned Cmake with Make
+* [#16737](https://github.com/apache/nuttx/pull/16737) toolchain/arm64/cmake: Corrected the writing of arm64 cmake search library
+* [#16849](https://github.com/apache/nuttx/pull/16849) Make/Toolchain.defs: add the AR_EXTRACT command
+
+Architectural Support
+Improvements
+ARM
+* [#16806](https://github.com/apache/nuttx/pull/16806) arch/*/*_sigdeliver.c: Fix a race condition is signal delivery for SMP
+* [#16657](https://github.com/apache/nuttx/pull/16657) arch/arm: Add gic lock for GICD_ICFGR RMW operations.
+* [#16881](https://github.com/apache/nuttx/pull/16881) arch/arm: Add missing barriers.h
+* [#16669](https://github.com/apache/nuttx/pull/16669) arch/arm/*/stm32_fdcan_sock.c: prevent interrupt flood on errors.
+* [#16611](https://github.com/apache/nuttx/pull/16611) arch/arm/armv7-a: Support hardware debugpoint to  enhance gdbstub
+* [#16752](https://github.com/apache/nuttx/pull/16752) arch/arm/cxd56xx: Fix bug that causes wake-up by unused gpio interrupt
+* [#16797](https://github.com/apache/nuttx/pull/16797) arch/arm/imxrt: Initial modification to support two USB Controllers
+* [#16478](https://github.com/apache/nuttx/pull/16478) arch/arm/imxrt: Serial add RXDMA support for singlewire mode
+* [#16703](https://github.com/apache/nuttx/pull/16703) arch/arm/rp23xx: Fix gpio  for RP2350B
+* [#16704](https://github.com/apache/nuttx/pull/16704) arch/arm/rp23xx: spi unset peripheral before  to modify Spi parameters
+* [#16837](https://github.com/apache/nuttx/pull/16837) arch/arm/rp2040: Fix typos in ADC and GPIO macro names
+* [#16840](https://github.com/apache/nuttx/pull/16840) arch/arm/rp2040: Implement GPIO output override functionality
+* [#16886](https://github.com/apache/nuttx/pull/16886) arch/arm/rp2040: Silence "LOAD segment with RWX permissions" linker warnings
+* [#16876](https://github.com/apache/nuttx/pull/16876) arch/arm/rp2040: Support pico-sdk 2.2.0
+* [#16842](https://github.com/apache/nuttx/pull/16842) arch/arm/rp2040: Support non-sequential ADC channels and standardize internal function names
+* [#16783](https://github.com/apache/nuttx/pull/16783) arch/arm/samv7: add support for pin to pin compatible pic32cz ca70 series and its evaluation kit
+* [#16901](https://github.com/apache/nuttx/pull/16901) arch/arm/samv7: add support for progmem in PIC32CZ CA70 series
+* [#16907](https://github.com/apache/nuttx/pull/16907) arch/arm/samv7: fix compile warning
+* [#16522](https://github.com/apache/nuttx/pull/16522) arch/arm/samv7: init perf events if enabled
+* [#16572](https://github.com/apache/nuttx/pull/16572) arch/arm/samv7: set correct SPI mode during init
+* [#16465](https://github.com/apache/nuttx/pull/16465) arch/arm/samv7: set correct SPI mode during init
+* [#16541](https://github.com/apache/nuttx/pull/16541) arch/arm/stm32: add STM32 I2C Slave support f…
+* [#16532](https://github.com/apache/nuttx/pull/16532) arch/arm/stm32: add support for ADC trigger from TRGO event
+* [#16534](https://github.com/apache/nuttx/pull/16534) arch/arm/stm32: add support for batch DMA transfer
+* [#16680](https://github.com/apache/nuttx/pull/16680) arch/arm/stm32{h5|h7|l4}/adc: move ADC_MAX_SAMPLES to Kconfig
+* [#16530](https://github.com/apache/nuttx/pull/16530) arch/arm/stm32f0l0g0: add TIMER trigger for ADC
+* [#16514](https://github.com/apache/nuttx/pull/16514) arch/arm/stm32f0l0g0: fix compilation when TIM6/TIM7 is missing
+* [#16589](https://github.com/apache/nuttx/pull/16589) arch/arm/stm32f0l0g0: fix compilation when TIM6/TIM7 is missing
+* [#16810](https://github.com/apache/nuttx/pull/16810) arch/arm/stm32f0l0g0: Fix I2C IRQ numbers
+* [#16543](https://github.com/apache/nuttx/pull/16543) arch/arm/stm32f0l0g0: Improve STM32G0 peripheral config granularity
+* [#16670](https://github.com/apache/nuttx/pull/16670) arch/arm/stm32f0l0g0: move ADC_MAX_SAMPLES to Kconfig
+* [#16513](https://github.com/apache/nuttx/pull/16513) arch/arm/stm32f0l0g0: remove references to CONFIG_STM32F0L0G0_FORCEPOWER
+* [#16557](https://github.com/apache/nuttx/pull/16557) arch/arm/stm32f0l0g0: STM32G0 DMA and ADC Support
+* [#16497](https://github.com/apache/nuttx/pull/16497) arch/arm/stm32f0l0g0: UID support for F0, L0 and C0
+* [#16517](https://github.com/apache/nuttx/pull/16517) arch/arm/stm32f7: Add missing RCC include
+* [#16909](https://github.com/apache/nuttx/pull/16909) arch/arm/stm32f7: Fix "unused variable" warning
+* [#16860](https://github.com/apache/nuttx/pull/16860) arch/arm/stm32f7: Fix I2C4 SDA pin assignment
+* [#16827](https://github.com/apache/nuttx/pull/16827) arch/arm/stm32h7: Fix timer capture upper half driver registration
+* [#16809](https://github.com/apache/nuttx/pull/16809) arch/arm/stm32h7: Port timer capture driver from stm32
+* [#16705](https://github.com/apache/nuttx/pull/16705) arch/arm/stm32h7: support for /dev/random device
+* [#16706](https://github.com/apache/nuttx/pull/16706) arch/arm/STM32H5: Add DMA and ADC DMA support
+* [#16776](https://github.com/apache/nuttx/pull/16776) arch/arm/stm32h5: Add DMA Support to STM32H5 Serial Driver
+* [#16708](https://github.com/apache/nuttx/pull/16708) arch/arm/STM32H5: Add oversampling and resolution support for ADC
+* [#16746](https://github.com/apache/nuttx/pull/16746) arch/arm/stm32h5: Initial Driver for STM32H5 Digital Temperature Sensor (DTS)
+* [#16818](https://github.com/apache/nuttx/pull/16818) arch/arm/stm32h5: Fix STM32H5 FDCAN Driver and Add Test Files
+* [#16803](https://github.com/apache/nuttx/pull/16803) arch/arm/stm32h5: Use double-buffer for ADC DMA in Circular Mode
+* [#16923](https://github.com/apache/nuttx/pull/16923) arch/arm/xmc4 : fix serial buffer size for unused channel
+ARM64
+* [#16612](https://github.com/apache/nuttx/pull/16612) arch/arm64: enable arm64 hardware breakpoints
+* [#16846](https://github.com/apache/nuttx/pull/16846) arch/arm64: Fix signal delivery in EL1 when MMU is enabled
+* [#16826](https://github.com/apache/nuttx/pull/16826) arch/arm64: imx9 add pci dma space and pci outbound space
+* [#16884](https://github.com/apache/nuttx/pull/16884) arch/arm64/gicv3: Improve initialization in warm reboot case
+* [#16743](https://github.com/apache/nuttx/pull/16743) arch/arm64/imx9: add support for imx95
+* [#16727](https://github.com/apache/nuttx/pull/16727) arch/arm64/imx9: eDMA5 Allow sharing with Linux
+* [#16844](https://github.com/apache/nuttx/pull/16844) arch/arm64/imx9: Fix first trace
+* [#16900](https://github.com/apache/nuttx/pull/16900) arch/arm64/imx9: Fix bus reset
+* [#16719](https://github.com/apache/nuttx/pull/16719) arch/arm64/zynq-mpsoc: fix race condition in txint handler
+AVR
+* [#16687](https://github.com/apache/nuttx/pull/16687) arch/avr: do not copy const variables to RAM
+* [#16498](https://github.com/apache/nuttx/pull/16498) arch/avr: fix atomic load functions from arch_atomic.c
+* [#16586](https://github.com/apache/nuttx/pull/16586) arch/avr: fix atomic load functions from arch_atomic.c
+RISC-V
+* [#16692](https://github.com/apache/nuttx/pull/16692) arch/[risc-v/xtensa]: Add SHA accelerator support for esp32[-s2|-s3|-c3|-c6|-h2]
+* [#16694](https://github.com/apache/nuttx/pull/16694) arch/risc-v: Add LP_I2C support for esp32[-c6]
+* [#16683](https://github.com/apache/nuttx/pull/16683) arch/risc-v: Add LPUART support for esp32[-c6]
+* [#16685](https://github.com/apache/nuttx/pull/16685) arch/risc-v: Change DMA functions with common layer for esp32[-c3|-c6|-h2]
+* [#16565](https://github.com/apache/nuttx/pull/16565) arch/risc-v: Fix `rv-virt:nsbi[|64]` defconfigs
+* [#16676](https://github.com/apache/nuttx/pull/16676) arch/risc-v: fix I2C timeout and board compilation requirements
+* [#16921](https://github.com/apache/nuttx/pull/16921) arch/risc-v: Refactor Wi-Fi driver for ESP32-C3|C6
+* [#16485](https://github.com/apache/nuttx/pull/16485) arch/risc-v/mpfs: Add optimized perf timer functions
+* [#16850](https://github.com/apache/nuttx/pull/16850) arch/risc-v/mpfs: fixes for coremmc and emmcsd
+* [#16851](https://github.com/apache/nuttx/pull/16851) arch/risc-v/mpfs: SMP interrupt handling fixes
+* [#16903](https://github.com/apache/nuttx/pull/16903) arch/risc-v/mpfs/mpfs_clockconfig.c: Flag out code only used in b…
+* [#16529](https://github.com/apache/nuttx/pull/16529) arch/risc-v/ricv_exception.c: Dump the process name at exception in user space
+* [#16424](https://github.com/apache/nuttx/pull/16424) arch/risc-v/rp23xx-riscv: Add rp23xx(rp2350)  (Pico 2 board)  RISC-V support
+SIM
+* [#16742](https://github.com/apache/nuttx/pull/16742) arch/sim: avoid host-call being interrupted before getting errno
+TRICORE
+* [#16885](https://github.com/apache/nuttx/pull/16885) arch/tricore: add up_trigger_irq
+* [#16910](https://github.com/apache/nuttx/pull/16910) arch/tricore: fix ld unrecognized option '-g3'
+* [#16917](https://github.com/apache/nuttx/pull/16917) arch/tricore/tricore_irq.c: add up_affinity_irq
+X86_64
+* [#16787](https://github.com/apache/nuttx/pull/16787) arch/x86_64: Allow specifying alternative compilers via CROSSDEV environment variable
+XTENSA
+* [#16804](https://github.com/apache/nuttx/pull/16804) arch/xtensa: Fix a race condition in xtensa_sig_deliver for SMP
+* [#16750](https://github.com/apache/nuttx/pull/16750) arch/xtensa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
+* [#16686](https://github.com/apache/nuttx/pull/16686) arch/xtensa: Fix dedicated GPIO build error for esp32[-s2|-s3]
+* [#16672](https://github.com/apache/nuttx/pull/16672) arch/xtensa: support more than 32 cpu interrupts
+* [#16744](https://github.com/apache/nuttx/pull/16744) arch/xtensa/esp32: fix esp32(s3)_async_op() asynchronous operation race issue
+* [#16883](https://github.com/apache/nuttx/pull/16883) arch/xtensa/esp32: fix some compilation warnings
+* [#16882](https://github.com/apache/nuttx/pull/16882) arch/xtensa/esp32: fix the issue of erasing a wide range of flash sectors
+* [#16894](https://github.com/apache/nuttx/pull/16894) arch/xtensa/esp32,esp32s3: Start the "spiflash_op" thread with corret affinity
+* [#16878](https://github.com/apache/nuttx/pull/16878) arch/xtensa/esp32s3: Add EXT1 wakeup support in power management
+* [#16756](https://github.com/apache/nuttx/pull/16756) arch/xtensa/esp32s3: Fix bug related to the PSRAM-allocated task stack
+* [#16566](https://github.com/apache/nuttx/pull/16566) arch/xtensa/esp32s3: Fix Esp32S3 LCD FB resolution.
+* [#16603](https://github.com/apache/nuttx/pull/16603) arch/xtensa/esp32s3: Remove LCD Warnings.
+* [#16607](https://github.com/apache/nuttx/pull/16607) arch/xtensa/esp32s3: Remove LCD Warnings.
+* [#16856](https://github.com/apache/nuttx/pull/16856) arch/xtensa/esp32s2: Remove duplicated lines to fix warning
+
+Driver Support
+New Driver Support
+* [#16836](https://github.com/apache/nuttx/pull/16836) drivers/analog/ads7046: Add support for ADS7046 ADC
+* [#16714](https://github.com/apache/nuttx/pull/16714) drivers/input: Create Single Button Multi Actions
+* [#16902](https://github.com/apache/nuttx/pull/16902) drivers/ioexpander: Add support for pcal6416
+* [#16934](https://github.com/apache/nuttx/pull/16934) drivers/ioexpander/aw9523b: New driver for AW9523B i/o expander
+* [#16217](https://github.com/apache/nuttx/pull/16217) drivers/leds: Add support for KTD2052
+* [#16660](https://github.com/apache/nuttx/pull/16660) drivers/net: add IGB network card support
+* [#16623](https://github.com/apache/nuttx/pull/16623) drivers/net: add support for the NCV7410 10BASE-T1S SPI MAC-PHY
+* [#16605](https://github.com/apache/nuttx/pull/16605) drivers/sensors: add Quectel L86-XXX GNSS uORB sensor driver
+* [#16838](https://github.com/apache/nuttx/pull/16838) drivers/sensors/tmp112: Add support for TMP112 temperature sensor
+Improvements
+* [#16715](https://github.com/apache/nuttx/pull/16715) drivers/analog/ads1115.h: Add ioctl for conversion trigger
+* [#16875](https://github.com/apache/nuttx/pull/16875) drivers/can/kvaser_pci: configure number of passes in interrupt handler
+* [#16738](https://github.com/apache/nuttx/pull/16738) drivers/fs:Always use register_mtddriver() to register the MTD device (patch2)
+* [#16914](https://github.com/apache/nuttx/pull/16914) drivers/i2s/i2schar: Implement ioctl commands and blocking read/write operations
+* [#16745](https://github.com/apache/nuttx/pull/16745) drivers/ioexpander/icjx.c: reconfigure icjx after undervoltage
+* [#16729](https://github.com/apache/nuttx/pull/16729) drivers/misc/optee: Cache coherency when MMU is disabled
+* [#16734](https://github.com/apache/nuttx/pull/16734) drivers/misc/optee: expand RPC suppport for IMX9
+* [#16800](https://github.com/apache/nuttx/pull/16800) drivers/misc/optee_smc: Explicitly yield during NW interrupts
+* [#16801](https://github.com/apache/nuttx/pull/16801) drivers/misc/optee_smc: Fix sched_yield() on flat builds
+* [#16473](https://github.com/apache/nuttx/pull/16473) drivers/mtd: fix compile warning
+* [#16577](https://github.com/apache/nuttx/pull/16577) drivers/mtd: fix compile warning
+* [#16789](https://github.com/apache/nuttx/pull/16789) drivers/mtd: introduce nvblk
+* [#16642](https://github.com/apache/nuttx/pull/16642) drivers/mtd/ftl/bch: Add direct writing method for FTL
+* [#16906](https://github.com/apache/nuttx/pull/16906) drivers/net: ksz9477 fixes
+* [#16899](https://github.com/apache/nuttx/pull/16899) drivers/net: Remove NCV7410 driver and corresponding board support
+* [#16661](https://github.com/apache/nuttx/pull/16661) drivers/net: various fixes for e1000 and igc
+* [#16649](https://github.com/apache/nuttx/pull/16649) drivers/net/Kconfig: Move NET_IGC_TXDESC and NET_IGC_RXDESC to NET_IG…
+* [#16526](https://github.com/apache/nuttx/pull/16526) drivers/optee: fix compile break
+* [#16767](https://github.com/apache/nuttx/pull/16767) drivers/pci: epc add dma heap
+* [#16753](https://github.com/apache/nuttx/pull/16753) drivers/segger: Add a kconfig to override Segger SystemView target sources version
+* [#16510](https://github.com/apache/nuttx/pull/16510) drivers/segger: Change SEGGER_RTT_LOCK into rspinlock
+* [#16512](https://github.com/apache/nuttx/pull/16512) drivers/segger: define a macro using a configuration variable
+* [#16805](https://github.com/apache/nuttx/pull/16805) drivers/sensor: Add flags for GNSS satellite
+* [#16764](https://github.com/apache/nuttx/pull/16764) drivers/sensors/l86xxx: Fix driver registration crashes
+* [#16701](https://github.com/apache/nuttx/pull/16701) drivers/sensors/l86xxx: Fix Kconfig options and dependencies
+* [#16821](https://github.com/apache/nuttx/pull/16821) drivers/sensors/l86xxx: Mutex fixes & performance improvements
+* [#16778](https://github.com/apache/nuttx/pull/16778) drivers/sensors/l86xxx: Use uORB GNSS lower-half
+* [#16717](https://github.com/apache/nuttx/pull/16717) drivers/sensors/nau7802: Added frequency control
+* [#16466](https://github.com/apache/nuttx/pull/16466) drivers/serial: fix race conditions
+* [#16573](https://github.com/apache/nuttx/pull/16573) drivers/serial: fix race conditions
+* [#16820](https://github.com/apache/nuttx/pull/16820) drivers/syslog/syslog_channel.c: fix incompatible-pointer-types compile errors
+* [#16677](https://github.com/apache/nuttx/pull/16677) drivers/touchscreen: Add support for mirror/swap
+* [#16788](https://github.com/apache/nuttx/pull/16788) drivers/video: add sched_note_mark at fb_remove_paninfo and fb_notify_vsync
+
+Board Support
+New Board Support
+* [#16443](https://github.com/apache/nuttx/pull/16443) boards/avr/atmega: Added Elegoo Mega2560r3 board
+* [#16781](https://github.com/apache/nuttx/pull/16781) boards/imxrt: Add support to ARCX Socket Grid board
+* [#16558](https://github.com/apache/nuttx/pull/16558) boards/xtensa/esp32s3: add new esp32s3-8048S043 board
+Improvements
+* [#16792](https://github.com/apache/nuttx/pull/16792) boards/arm: Fix Kconfig style
+* [#16663](https://github.com/apache/nuttx/pull/16663) boards/arm/lpc17xx_40xx/lincoln60: Correct defconfig for THTTPD_CGIINBUFFERSIZ spelling
+* [#16833](https://github.com/apache/nuttx/pull/16833) boards/arm/qemu: Change config name of input tool
+* [#16931](https://github.com/apache/nuttx/pull/16931) boards/arm/rp23xx/common: update board reset via BOOTROM functions
+* [#16707](https://github.com/apache/nuttx/pull/16707) boards/arm/stm32f401rc-rs485: Add support to HX711 ADC
+* [#16779](https://github.com/apache/nuttx/pull/16779) boards/arm/stm32f401rc-rs485: Add support to MAX31855 and MAX6675
+* [#16780](https://github.com/apache/nuttx/pull/16780) boards/arm/stm32f4discovery: Add support to HX711 ADC
+* [#16857](https://github.com/apache/nuttx/pull/16857) board/esp: Revert mtdblock registeration
+* [#16866](https://github.com/apache/nuttx/pull/16866) boards/esp32s3: Add SPI slave device support
+* [#16725](https://github.com/apache/nuttx/pull/16725) boards/espressif: add support for SDMMC over SPI for ESP32-C3|C6|H2
+* [#16812](https://github.com/apache/nuttx/pull/16812) boards/imxrt: Fix issues and add USBHOST support to arcx-socket-grid
+* [#16824](https://github.com/apache/nuttx/pull/16824) boards/imxrt/arcx-socket-grid: Remove debug symbols
+* [#16535](https://github.com/apache/nuttx/pull/16535) boards/nucleo-f446re: fix adc example
+* [#16592](https://github.com/apache/nuttx/pull/16592) boards/nucleo-f446re: fix adc example
+* [#16665](https://github.com/apache/nuttx/pull/16665) boards/qemu-armv8a: Add `xedge` example program and documentation
+* [#16659](https://github.com/apache/nuttx/pull/16659) boards/qemu-intel64/qemu.ld: add .lbss, .ldata and .lrodata
+* [#16848](https://github.com/apache/nuttx/pull/16848) boards/risc-v/rp23xx-rv/common: update board reset via BOOTROM functions
+* [#16646](https://github.com/apache/nuttx/pull/16646) boards/riscv-v/esp32c6: Add the NCV7410 10BASE-T1S SPI MAC-PHY support
+* [#16898](https://github.com/apache/nuttx/pull/16898) boards/tricore:  rename tc397 chip board name
+* [#16505](https://github.com/apache/nuttx/pull/16505) boards/xtensa/esp32: Add BLE config to esp32-sparrow
+* [#16602](https://github.com/apache/nuttx/pull/16602) boards/xtensa: support SDMMC over SPI on ESP32|S2|S3
+* [#16638](https://github.com/apache/nuttx/pull/16638) boards/xtensa/esp32s3/esp32s3-box: Fix ILI9342C color inversion
+* [#16681](https://github.com/apache/nuttx/pull/16681) boards/weact-stm32h743 Add sdcard support
+* [#16785](https://github.com/apache/nuttx/pull/16785) boards/weact-stm32h743: Add support to ST7735 display
+
+File System
+ Improvements
+* [#16722](https://github.com/apache/nuttx/pull/16722) fs/block_proxy: fix the issue of the refs count for filep being zeroed out by utilizing dup2
+* [#16938](https://github.com/apache/nuttx/pull/16938) fs/fat: Fix wrong alloc used in fat_zero_cluster()
+* [#16536](https://github.com/apache/nuttx/pull/16536) fs/fcntl: using ioctl to implement FIOGCLEX/FIOCLEX/FIONCLEX
+* [#16832](https://github.com/apache/nuttx/pull/16832) fs/lock: Allow driver lock
+* [#16598](https://github.com/apache/nuttx/pull/16598) fs/procfs: fix output format of fd info
+* [#16518](https://github.com/apache/nuttx/pull/16518) fs/smartfs: Fix a fatal bug about sector writing after seek
+* [#16590](https://github.com/apache/nuttx/pull/16590) fs/smartfs: Fix a fatal bug about sector writing after seek
+* [#16490](https://github.com/apache/nuttx/pull/16490) fs/vfs: check if all `iov_base` are accessible
+* [#16584](https://github.com/apache/nuttx/pull/16584) fs/vfs: check if all iov_base are accessible
+* [#16609](https://github.com/apache/nuttx/pull/16609) fs/vfs: clear filep when call file_open/file_mq_open to avoid random value[bug fix]
+* [#16538](https://github.com/apache/nuttx/pull/16538) fs/vfs/fs_close.c: avoid double free if CONFIG_FS_NOTIFY is set
+* [#16455](https://github.com/apache/nuttx/pull/16455) fs/vfs/fs_rename: fix directory move operation.
+
+Networking
+Improvements
+* [#16926](https://github.com/apache/nuttx/pull/16926) include/net/if.h: Add mechanism for MMD access with SIOCxMIIREG ioctls
+* [#16628](https://github.com/apache/nuttx/pull/16628) net: Enable TCP/IP backlog by default
+* [#16684](https://github.com/apache/nuttx/pull/16684) net/arp: avoid unnecessary ARP requests
+* [#16905](https://github.com/apache/nuttx/pull/16905) net/can: fixes and cleanups
+* [#16682](https://github.com/apache/nuttx/pull/16682) net/local: correct shutdown state when use UDP mode (To fix issue: https://github.com/apache/nuttx/issues/16555)
+* [#16494](https://github.com/apache/nuttx/pull/16494) net/utils: avoid unalign access g_tcp_connections_buffer
+* [#16585](https://github.com/apache/nuttx/pull/16585) net/utils: avoid unalign access g_tcp_connections_buffer
+* [#16599](https://github.com/apache/nuttx/pull/16599) netdb/lib_dnsquery.c: prevent file descriptor leakage
+* [#16606](https://github.com/apache/nuttx/pull/16606) netdb/lib_dnsquery.c: In the IPv6 or IPv4 dns_query_callback() block,…
+
+Unsorted contributions
+* [#16644](https://github.com/apache/nuttx/pull/16644) espressif: update lower-half drivers
+* [#16467](https://github.com/apache/nuttx/pull/16467) audio/comp: fix build warning caused by invalid return value
+* [#16469](https://github.com/apache/nuttx/pull/16469) mcx-nxxx: Add LPI2C driver for mcx-nxxx architecture
+* [#16474](https://github.com/apache/nuttx/pull/16474) syslog/rpmsg: disable force put char to lower putc
+* [#16479](https://github.com/apache/nuttx/pull/16479) sensors/nau7802: Fix format warning
+* [#16482](https://github.com/apache/nuttx/pull/16482) Fix i.MX93 ENET1 (EMAC) TXC muxing and RGMII-ID setting
+* [#16483](https://github.com/apache/nuttx/pull/16483) Segger sysview improvements
+* [#16486](https://github.com/apache/nuttx/pull/16486) add spin_lock_irqsave_nopreempt rspin_lock_irqsave_noprempt implement.
+* [#16487](https://github.com/apache/nuttx/pull/16487) Fix arch perf events ifdef in alarm
+* [#16489](https://github.com/apache/nuttx/pull/16489) Added support obtaining the unique id for the stm32f0l0g0 family
+* [#16491](https://github.com/apache/nuttx/pull/16491) espressif[risc-v|xtensa]: Check events when reading PCNT counter value
+* [#16492](https://github.com/apache/nuttx/pull/16492) add FDCAN support for STM32C0
+* [#16493](https://github.com/apache/nuttx/pull/16493) RFC 5424 implementation for SYSLOG
+* [#16495](https://github.com/apache/nuttx/pull/16495) minor stream improvement
+* [#16496](https://github.com/apache/nuttx/pull/16496) improve libc/stream subsystem
+* [#16500](https://github.com/apache/nuttx/pull/16500) Add ADC support for STM32G0 (along with oversampling)
+* [#16508](https://github.com/apache/nuttx/pull/16508) riscv qemu-rv: fix kernel mapping by enabling CONFIG_MM_KMAP in knsh
+* [#16509](https://github.com/apache/nuttx/pull/16509) Update the ELF guides
+* [#16511](https://github.com/apache/nuttx/pull/16511) nuttx/spinlock: Define empty macro for spin_unlock
+* [#16519](https://github.com/apache/nuttx/pull/16519) imx9/smp: Add SMP support for imx93
+* [#16527](https://github.com/apache/nuttx/pull/16527) nxgdb/fs: fix exception when failed to parse symbol
+* [#16533](https://github.com/apache/nuttx/pull/16533) Update MCUBoot build process for Espressif devices
+* [#16540](https://github.com/apache/nuttx/pull/16540) qemu/armv8a: fastboot tcp defconfig + documentation.
+* [#16549](https://github.com/apache/nuttx/pull/16549) Minor improve to stream
+* [#16550](https://github.com/apache/nuttx/pull/16550) gitignore: add more vim swap files
+* [#16552](https://github.com/apache/nuttx/pull/16552) spinlock: Better recursive spinlock implementation.
+* [#16556](https://github.com/apache/nuttx/pull/16556) risc-v/mmu: Fix map_region() for incorrect page table setup when vadd…
+* [#16562](https://github.com/apache/nuttx/pull/16562) esp32s3: update config and doc for fastboot
+* [#16567](https://github.com/apache/nuttx/pull/16567) Move assemble soure files out off gnu folder
+* [#16569](https://github.com/apache/nuttx/pull/16569) Refine vfs source file layout
+* [#16571](https://github.com/apache/nuttx/pull/16571) remove warnings
+* [#16574](https://github.com/apache/nuttx/pull/16574) audio/comp: fix build warning caused by invalid return value
+* [#16578](https://github.com/apache/nuttx/pull/16578) syslog/rpmsg: disable force put char to lower putc
+* [#16580](https://github.com/apache/nuttx/pull/16580) mcx-nxxx: Add LPI2C driver for mcx-nxxx architecture
+* [#16582](https://github.com/apache/nuttx/pull/16582) sensors/nau7802: Fix format warning
+* [#16583](https://github.com/apache/nuttx/pull/16583) Fix i.MX93 ENET1 (EMAC) TXC muxing and RGMII-ID setting
+* [#16588](https://github.com/apache/nuttx/pull/16588) riscv qemu-rv: fix kernel mapping by enabling CONFIG_MM_KMAP in knsh …
+* [#16591](https://github.com/apache/nuttx/pull/16591) Update MCUBoot build process for Espressif devices
+* [#16595](https://github.com/apache/nuttx/pull/16595) risc-v/mmu: Fix map_region() for incorrect page table setup when vadd…
+* [#16596](https://github.com/apache/nuttx/pull/16596) Fix arch perf events ifdef in alarm 
+* [#16597](https://github.com/apache/nuttx/pull/16597) fix framebuffer config resolution.
+* [#16604](https://github.com/apache/nuttx/pull/16604) [ESP32S3] Add LCD defconfig
+* [#16615](https://github.com/apache/nuttx/pull/16615) debug/0 address: Add 0 address access panic configuration
+* [#16618](https://github.com/apache/nuttx/pull/16618) Enhanced Kasan
+* [#16619](https://github.com/apache/nuttx/pull/16619) arm64/v8r: support clang compilation
+* [#16629](https://github.com/apache/nuttx/pull/16629) bugfix: share kernel thread group should not dup files from caller group
+* [#16635](https://github.com/apache/nuttx/pull/16635) Add a header file as a dependency
+* [#16651](https://github.com/apache/nuttx/pull/16651) Refactored the btuart_rxwork function to improve data reception stability.
+* [#16654](https://github.com/apache/nuttx/pull/16654) imx9/lpuart: Fix race condition / regression in imx9_txint
+* [#16671](https://github.com/apache/nuttx/pull/16671) sem/trywait/atomic: Fix the try wait abort by interrupted caused false failure report.
+* [#16674](https://github.com/apache/nuttx/pull/16674) xtensa/espressif: Change LEDC implementation to common one
+* [#16690](https://github.com/apache/nuttx/pull/16690) coredump: Fix missing loglevel to logmask conversion
+* [#16700](https://github.com/apache/nuttx/pull/16700) sensors/bmi160,270: Fix a bug sensor_time is truncated
+* [#16718](https://github.com/apache/nuttx/pull/16718) arm64/qemu: decouple qemu board from chip
+* [#16735](https://github.com/apache/nuttx/pull/16735) espressif: fix MCUBoot OTA on Espressif devices.
+* [#16754](https://github.com/apache/nuttx/pull/16754) espressif: PCNT: add high and low limit Kconfig options
+* [#16765](https://github.com/apache/nuttx/pull/16765) nucleo-h743zi: Add ADC2 support and expand ADC channel list
+* [#16769](https://github.com/apache/nuttx/pull/16769) esp32s3_extraheaps.c: add a missing include for xtensa_imm_initialize
+* [#16771](https://github.com/apache/nuttx/pull/16771) crypto/cryptosoft: fix aadlen used uninitialized warning
+* [#16773](https://github.com/apache/nuttx/pull/16773) add esp32s3-devkit:mbedtls kconfig
+* [#16798](https://github.com/apache/nuttx/pull/16798) arm64: porting mu drv and scmi from arm imx9
+* [#16807](https://github.com/apache/nuttx/pull/16807) bugix/risc-v/esp32c6: Fix build error of LP_I2C
+* [#16813](https://github.com/apache/nuttx/pull/16813) Fix compilation errors with c++
+* [#16819](https://github.com/apache/nuttx/pull/16819) Increase buffer sizes for uORB devices
+* [#16830](https://github.com/apache/nuttx/pull/16830) h743zi/capture: add doc, defconfig & update make pipeline
+* [#16839](https://github.com/apache/nuttx/pull/16839) crypto/hmac: Fix typo in function implementation names
+* [#16843](https://github.com/apache/nuttx/pull/16843) pci: epf test default a function
+* [#16845](https://github.com/apache/nuttx/pull/16845) sys/socket.h: wrap the outer layer of struct sockaddr_storage with aligned(SS_ALIGNSIZE)
+* [#16852](https://github.com/apache/nuttx/pull/16852) risc-v/mpfs: usb: don't try nonexistent ep int flags
+* [#16853](https://github.com/apache/nuttx/pull/16853) Mpfs map mtime in userspace
+* [#16874](https://github.com/apache/nuttx/pull/16874) Add missing PSE52 interfaces
+* [#16879](https://github.com/apache/nuttx/pull/16879) include/nuttx/compiler.h:
+
+Compatibility Concerns
+* [#16499](https://github.com/apache/nuttx/pull/16499) [BREAKING] fs/vfs: Separate file descriptors from file descriptions
+
+This PR is a rework of the NuttX file descriptor implementation. The goal is two-fold:
+
+Improve POSIX compliance. The old implementation tied file description
+to inode only, not the file struct. POSIX however dictates otherwise.
+Fix a bug with descriptor duplication (dup2() and dup3()). There is
+an existing race condition with this POSIX API that currently results
+in a kernel side crash.
+The crash occurs when a partially open / closed file descriptor is
+duplicated. The reason for the crash is that even if the descriptor is
+closed, the file might still be in use by the kernel (due to e.g. ongoing
+write to file). The open file data is changed by file_dup3() and this
+causes a crash in the device / drivers themselves as they lose access to
+the inode and private data.
+
+The fix is done by separating struct file into file and file descriptor
+structs. The file struct can live on even if the descriptor is closed,
+fixing the crash. This also fixes the POSIX issue, as two descriptors
+can now point to the same file.
+
+The implementation of this PR is based on the modifications made in #16361.
+Thank you @pussuw
+
+DEPENDS ON: apache/nuttx-apps#3091
+
+IMPACT
+
+Remove the FS_REFCOUNT config because reference counting is a very necessary feature
+that is required in many scenarios to ensure stability.
+Rename the functions fs_getfilep, fs_putfilep, and fs_reffilep to file_get, file_put,
+and file_ref respectively, to unify the naming convention to file_xxx, such as file_open,
+ file_ioctl, etc.
+Introduce a new fd (file descriptor) structure. If multiple file descriptors (fds) are in
+ a dup relationship, they can share the same file entity to implement the dup functionality.
+Modify the functions nx_close_from_tcb, nx_open_from_tcb, nx_dup2_from_tcb,
+and nx_dup3_from_tcb to fdlist_open, fdlist_close, fdlist_dup2, and fdlist_dup3 respectively,
+ to uniformly operate on file descriptors using fdlist.

Documentation/applications/boot/nxboot/index.rst

@@ -277,8 +277,8 @@ Enabling ``CONFIG_BOOT_NXBOOT`` option provides following NXboot API.
 
 .. c:function:: int nxboot_get_confirm(void)
 
-  Confirms the image currently located in primary partition and marks
+  Obtains the information if currently running image is confirmed (and
-  its copy in update partition as a recovery.
+  thus stable) or not.
 
   :return: 1 means confirmed, 0 not confirmed, -1 and sets errno on failure.
 

Documentation/applications/examples/bmp280/index.rst

@@ -2,4 +2,15 @@
 ``bmp280`` BMP280 Barometer sensor example
 ==========================================
 
-BMP280 Barometer sensor example.
+This example is made for testing the BMP280 barometer sensor. It works by
+reading a single measurement from the device (assuming it is registered at
+``/dev/uorb/sensor_baro0``) and prints the results to the screen. The program is
+run without any command line arguments.
+
+Here is an example of the console output:
+
+.. code-block:: console
+
+   nsh> bmp280
+   Absolute pressure [hPa] = 983.099976
+   Temperature [C] = 24.129999

Documentation/applications/examples/calib_udelay/index.rst

@@ -2,4 +2,51 @@
 ``calib_udelay`` Calibration tool for udelay
 =============================================
 
-Calibration tool for udelay.
+This tool is used for calibrating the configuration option
+``CONFIG_BOARD_LOOPSPERMSEC``. This option is used by NuttX to perform
+busy-waiting (i.e., spinning in a loop) when a very basic busy-wait sleep is
+needed in board logic. This is also sometimes used when the timer-based sleep
+functions do not have a low enough resolution for shorter timings (i.e. system
+tick every 1ms but you want to sleep for 100us).
+
+When porting NuttX a new board, this example program is very useful to get a
+calibrated value for ``CONFIG_BOARD_LOOPSPERMSEC``.
+
+.. note::
+
+   If you are testing any drivers and have unexpected issues with them, make
+   sure that this configuration option has been calibrated. It can cause
+   bad/incorrect timings in drivers if not calibrated.
+
+Here is the example output from running the application:
+
+.. code-block:: console
+
+   nsh> calib_udelay
+
+   Calibrating timer for main calibration...
+   Performing main calibration for udelay.This will take approx. 17.280 seconds.
+   Calibration slope for udelay:
+     Y = m*X + b, where
+       X is loop iterations,
+       Y is time in nanoseconds,
+       b is base overhead,
+       m is nanoseconds per loop iteration.
+
+     m = 5.33333333 nsec/iter
+     b = -199999.99999995 nsec
+
+     Correlation coefficient, R² = 1.0000
+
+   Without overhead, 0.18750000 iterations per nanosecond and 187500.00 iterations per millis.
+
+   Recommended setting for CONFIG_BOARD_LOOPSPERMSEC:
+      CONFIG_BOARD_LOOPSPERMSEC=187500
+
+You can simply copy paste the value from the console output and use it as the
+value for your board by setting it in the Kconfig menu.
+
+The program is run without any arguments. Configuration options for how the
+program runs (taking more measurements, etc.) can be seen in its Kconfig menu.
+Press ``h`` with the configuration option highlighted under your cursor to read
+the help text about what each option does.

Documentation/applications/netutils/ntpclient/index.rst

@@ -2,5 +2,174 @@
 ``ntpclient`` NTP client
 ========================
 
-This is a fragmentary NTP client. It neither well-tested nor
+The NTP (Network Time Protocol) client is a network utility that synchronizes
-mature nor complete at this point in time.
+the system clock with time servers over the Internet. This implementation
+provides a minimal but functional NTP client for NuttX.
+
+What is NTP?
+============
+
+The Network Time Protocol (NTP) is a networking protocol designed to
+synchronize clocks of computer systems over packet-switched, variable-latency
+data networks. NTP is one of the oldest Internet protocols still in use,
+originally designed by David L. Mills of the University of Delaware.
+
+Key features of NTP:
+
+- **High Precision**: NTP can achieve sub-millisecond accuracy on local area
+  networks and typically 10-100 millisecond accuracy over the Internet
+- **Robust Algorithm**: Uses sophisticated algorithms to filter out network
+  jitter and select the best time sources
+- **Hierarchical Structure**: Uses a stratum system where stratum 0 devices
+  are atomic clocks, stratum 1 servers sync with stratum 0, and so on
+- **Fault Tolerance**: Can handle multiple time sources and automatically
+  switch between them
+
+NTP Protocol Overview
+=====================
+
+NTP uses UDP port 123 and follows a client-server model. The protocol
+exchanges timestamps to calculate:
+
+- **Offset**: The difference between the client's clock and the server's clock
+- **Delay**: The round-trip network delay
+- **Dispersion**: The maximum error due to clock frequency tolerance
+
+The NTP packet format (version 3) includes:
+
+- **Leap Indicator**: Warns of an impending leap second
+- **Version Number**: NTP version (3 in this implementation)
+- **Mode**: Client, server, broadcast, etc.
+- **Stratum**: Clock level (0-15)
+- **Poll Interval**: Maximum interval between successive messages
+- **Precision**: Clock precision
+- **Root Delay/Dispersion**: Total delay and dispersion to the reference clock
+- **Reference Identifier**: Identifies the reference source
+- **Reference Timestamp**: Time when the system clock was last set
+- **Originate Timestamp**: Time when the request departed the client
+- **Receive Timestamp**: Time when the request arrived at the server
+- **Transmit Timestamp**: Time when the reply departed the server
+
+Implementation Details
+======================
+
+The NuttX NTP client implementation consists of several key components:
+
+Source Code Structure
+---------------------
+
+**ntpclient.c** - Main implementation file containing:
+
+- **Daemon Management**: Functions to start, stop, and manage the NTP daemon
+- **Time Synchronization**: Core algorithms for calculating clock offset and delay
+- **Network Communication**: UDP socket handling and NTP packet exchange
+- **Sample Collection**: Gathering multiple time samples for statistical filtering
+
+**ntpv3.h** - NTP version 3 packet format definitions:
+
+- **ntp_datagram_s**: Complete NTP packet structure
+- **ntp_timestamp_s**: 64-bit NTP timestamp format
+- **Protocol Constants**: NTP version, modes, and stratum definitions
+
+Key Functions
+-------------
+
+- **ntpc_start_with_list()**: Starts the NTP daemon with a list of servers
+- **ntpc_start()**: Starts the NTP daemon with default configuration
+- **ntpc_stop()**: Stops the running NTP daemon
+- **ntpc_status()**: Retrieves current synchronization status and samples
+- **ntpc_daemon()**: Main daemon loop that:
+
+  - Connects to configured NTP servers
+  - Sends NTP requests and processes responses
+  - Calculates clock offset and delay
+  - Applies time corrections to the system clock
+  - Continues polling at configured intervals
+
+- **ntpc_get_ntp_sample()**: Performs a single NTP transaction:
+
+  - Creates UDP socket to NTP server
+  - Sends NTP request packet with current timestamp
+  - Receives and validates NTP response
+  - Calculates offset and delay using NTP algorithms
+
+- **ntpc_calculate_offset()**: Implements the NTP clock filter algorithm
+
+  - Uses four timestamps, calculates offset and delay
+  - Applies statistical filtering to reduce jitter
+
+- **ntpc_settime()**: Applies time correction to system clock:
+
+  - Uses calculated offset to adjust system time
+  - Handles both positive and negative time adjustments
+  - Maintains monotonic clock consistency
+
+Configuration Options
+=====================
+
+The NTP client can be configured through Kconfig options:
+
+- **CONFIG_NETUTILS_NTPCLIENT_SERVER**: List of NTP server hostnames
+- **CONFIG_NETUTILS_NTPCLIENT_PORTNO**: NTP server port (default: 123)
+- **CONFIG_NETUTILS_NTPCLIENT_STACKSIZE**: Daemon task stack size
+- **CONFIG_NETUTILS_NTPCLIENT_SERVERPRIO**: Daemon task priority
+- **CONFIG_NETUTILS_NTPCLIENT_STAY_ON**: Keep polling continuously
+- **CONFIG_NETUTILS_NTPCLIENT_POLLDELAYSEC**: Polling interval in seconds
+- **CONFIG_NETUTILS_NTPCLIENT_NUM_SAMPLES**: Number of samples for filtering
+- **CONFIG_NETUTILS_NTPCLIENT_TIMEOUT_MS**: Network timeout in milliseconds
+
+Usage
+=====
+
+The NTP client is typically used through the system commands:
+
+.. note:: The NTP client functionality requires enabling the :code:`SYSTEM_NTPC` option in your configuration.
+    Make sure to select this option in menuconfig or your Kconfig fragment before building.
+
+- **ntpcstart**: Start the NTP daemon
+- **ntpcstop**: Stop the NTP daemon
+- **ntpcstatus**: Display synchronization status
+
+Example workflow:
+
+1. Configure network connectivity
+2. Start NTP client: ``ntpcstart``
+3. Check status: ``ntpcstatus``
+4. Verify time: ``date`` command
+5. Stop when needed: ``ntpcstop``
+
+The client will automatically:
+- Connect to configured NTP servers
+- Exchange time information
+- Calculate and apply clock corrections
+- Continue periodic synchronization
+
+Limitations
+===========
+
+This is a minimal NTP client implementation with some limitations:
+
+- **No Authentication**: Does not support NTP authentication (MD5/SHA1)
+- **Basic Filtering**: Uses simple statistical filtering, not full NTP algorithms
+- **Single Reference**: Does not implement full NTP reference clock selection
+- **No Leap Seconds**: Does not handle leap second announcements
+- **Limited Error Handling**: Basic error recovery and retry mechanisms
+
+Despite these limitations, the implementation provides sufficient accuracy
+for most embedded applications requiring network time synchronization.
+
+Dependencies
+============
+
+The NTP client requires:
+
+- **CONFIG_NET**: Network support
+- **CONFIG_NET_UDP**: UDP protocol support
+- **CONFIG_NET_SOCKOPTS**: Socket options support
+- **CONFIG_LIBC_NETDB**: DNS resolution (recommended)
+- **CONFIG_HAVE_LONG_LONG**: 64-bit integer support
+
+For best results, ensure:
+- Stable network connectivity
+- Access to reliable NTP servers
+- Sufficient system resources for daemon operation

Documentation/applications/system/ntpc/index.rst

@@ -1,3 +1,106 @@
 ============================
 ``ntpc`` NTP Daemon Commands
 ============================
+
+This example demonstrates how to use the NTP client to synchronize system time
+and retrieve the current time and date. It uses the Network Time Protocol (NTP)
+to provide accurate time synchronization.
+
+Description
+-----------
+
+The ntpc example:
+
+- Uses the NTP client library to synchronize system time
+
+- Connects to NTP servers (default: pool.ntp.org)
+
+- Starts the NTP client in the background for continuous synchronization
+
+- Provides commands to check status and stop the NTP client
+
+- Allows management of the NTP client through command line options
+
+Note: This example assumes that network connectivity is already established.
+
+The NTP (Network Time Protocol) is a sophisticated protocol that provides
+high-precision time synchronization and is the standard for network time services.
+
+Configuration
+-------------
+
+This example requires the following NuttX configuration options:
+
+- CONFIG_NET: Enable networking support
+- CONFIG_NET_UDP: Enable UDP support
+- CONFIG_NETUTILS_NTPCLIENT: Enable NTP client support
+- CONFIG_SYSTEM_NTPC: Enable this example
+
+Additional configuration options:
+- CONFIG_NETUTILS_NTPCLIENT_SERVER: NTP server hostname (default: "pool.ntp.org")
+
+Usage
+-----
+
+1. Configure your NuttX build with networking support
+2. Ensure network connectivity is established (e.g., via NSH network commands)
+3. Build and flash the image to your target board
+4. Run the commands:
+   - ``ntpcstart``, ``ntpcstop``, ``ntpcstatus``
+
+**Available Commands:**
+
+- ``ntpcstart`` - Start NTP client in background
+
+- ``ntpcstop`` - Stop the NTP client
+
+- ``ntpcstatus`` - Display NTP client status information
+
+Expected Output
+---------------
+
+**Start NTP client (ntpcstart):**
+::
+
+   Starting NTP client...
+   Using NTP servers: pool.ntp.org
+   NTP client started successfully (task ID: 123)
+   NTP client is now running in the background
+
+**Stop NTP client (ntpcstop):**
+::
+
+   Stopping NTP client...
+   Stopped the NTP daemon
+
+**Show NTP status (ntpcstatus):**
+::
+
+    The number of last samples: 3
+    [0] srv <ip> offset -0.033502142 delay 0.249973549
+    [1] srv <ip> offset -0.020698070 delay 0.029928000
+    [2] srv <ip> offset -0.015448935 delay 0.019815119
+
+**Verify using date command:**
+
+Given network connectivity is available, executing `date` should
+give the proper time and date.
+::
+
+    nsh> ntpcstart
+    Starting NTP client...
+    Using NTP servers: 0.pool.ntp.org;1.pool.ntp.org;2.pool.ntp.org
+    NTP client started successfully (task ID: 10)
+    NTP client is now running in the background
+    nsh> date
+    Fri, Sep 05 18:49:37 2025
+
+Notes
+-----
+
+- This example requires internet connectivity
+- Network must be configured and connected before running this example
+- NTP servers must be accessible (default: pool.ntp.org)
+- UDP port 123 (NTP) must not be blocked by firewalls
+- The example includes error handling for network failures
+- NTP provides more accurate time synchronization than simple time protocols

Documentation/applications/testing/cxx-oot-build/index.rst

@@ -0,0 +1,75 @@
+========================================
+``cxx-oot-build`` Out-of-Tree Build Test
+========================================
+
+The ``cxx-oot-build`` test automates building an **Out-of-Tree (OOT)** NuttX
+project using a NuttX export tarball. Its primary purpose is to validate that
+NuttX can be built outside of the main source tree and to prevent regressions
+in the build process for C++ projects.
+
+**Important:** This test uses a specialized defconfig that is **not functional**
+for running actual applications. It is intended purely for CI/build
+verification. Functional OOT projects should be configured according to
+the instructions in :ref:`cpp_cmake`.
+
+The test script is located at:
+
+- ``tools/ci/cibuild-oot.sh``
+
+### Out-of-Tree App Content
+
+The source content for this OOT test can be found in:
+
+- ``apps/testing/cxx-oot-build``
+
+Its structure provides a basic skeleton for building a C++ NuttX application:
+
+.. code-block:: text
+
+    testing/cxx-oot-build
+    ├── CMakeLists.txt
+    ├── include
+    │   └── HelloWorld.hpp
+    └── src
+        ├── HelloWorld.cpp
+        └── main.cpp
+
+This minimal structure includes:
+
+- `CMakeLists.txt` - Build instructions for the OOT C++ project  
+- `include/HelloWorld.hpp` - Example header file  
+- `src/HelloWorld.cpp` - Example class implementation  
+- `src/main.cpp` - Entry point for the test application  
+
+### How to Run the Test
+
+Execute the test script from the NuttX CI tools directory:
+
+    cd ${NUTTX_PATH}/tools/ci
+    ./cibuild-oot.sh
+
+The script performs the following steps:
+
+1. Configures NuttX for the ``cxx-oot-build`` board profile
+2. Builds an export tarball of NuttX
+3. Prepares the Out-of-Tree project by extracting the tarball
+4. Builds the OOT project using CMake
+5. Verifies that the output binaries ``oot`` and ``oot.bin`` exist
+
+### Expected Output
+
+On success, you should see:
+
+    ✅ SUCCESS: OOT build completed. Output:
+    -rwxrwxr-x 1 <user> <group> 94K <date> /path/to/oot
+    -rwxrwxr-x 1 <user> <group> 46K <date> /path/to/oot.bin
+
+If any step fails, the script will exit immediately with an error message.
+
+### Notes
+
+- No additional configuration options are required for this test. The
+  ``cxx-oot-build`` defconfig is preconfigured to build correctly but is
+  **not suitable for running applications**.
+- For functional OOT builds, please follow the procedure documented in
+  :doc:`here </guides/cpp_cmake>`.

Documentation/components/net/index.rst

@@ -12,6 +12,7 @@ Network Support
   nat.rst
   netdev.rst
   netdriver.rst
+  mdio.rst
   netguardsize.rst
   netlink.rst
   slip.rst

Documentation/components/net/mdio.rst

@@ -0,0 +1,73 @@
+.. _mdio_bus:
+
+.. include:: /substitutions.rst
+
+=================
+MDIO Bus Driver
+=================
+
+The NuttX MDIO bus driver provides a standardized interface for communicating with Ethernet PHY (Physical Layer) transceivers.
+It employs a classic upper-half/lower-half architecture to abstract hardware-specific logic from the generic MDIO protocol,
+which is currently compliant with Clause 22 of the IEEE 802.3 standard.
+The primary implementation of the upper-half can be found in ``drivers/net/mdio.c``.
+
+Driver Architecture
+===================
+
+The MDIO driver framework serves as an intermediary layer between a network device driver and the physical bus.
+The intended operational model is ``netdev -> phydev -> mdio``, where the network device communicates with a dedicated PHY driver,
+which in turn uses the MDIO bus driver for low-level hardware access.
+Direct interaction between the network device and the MDIO bus is discouraged.
+
+Upper-Half Implementation
+-------------------------
+
+The upper-half driver contains the core logic for the MDIO bus, including bus locking mechanisms to ensure safe transactions.
+It exposes a generic API for managing the bus lifecycle and is capable of handling multiple, independent MDIO bus instances concurrently.
+This abstracts implementation details from both the PHY driver and the underlying hardware-specific code.
+
+Lower-Half Implementation
+-------------------------
+
+A lower-half MDIO driver serves as a thin layer that maps the generic operations defined by the upper-half to hardware-specific register manipulations.
+It is not intended to contain complex logic, but rather to provide a direct translation for bus operations.
+
+Implementing a Lower-Half Driver
+================================
+
+Integrating MDIO support for new hardware requires the implementation of a lower-half driver.
+The contract between the upper and lower halves is defined in ``include/nuttx/net/mdio.h`` and is centered around two key structures.
+
+Key Data Structures
+-------------------
+
+1.  ``struct mdio_ops_s``: A structure containing function pointers that the lower-half driver must implement to perform hardware-level operations.
+    *   ``read``: Performs a Clause 22 MDIO read operation.
+    *   ``write``: Performs a Clause 22 MDIO write operation.
+    *   ``reset``: An optional function to execute a hardware-specific PHY reset.
+
+2.  ``struct mdio_lowerhalf_s``: The container for the lower-half instance, which holds a pointer to the ``mdio_ops_s`` vtable 
+    and an optional private data pointer for the driver's internal state.
+
+Registration and Unregistration
+-------------------------------
+
+The board-level initialization logic is responsible for instantiating the lower-half driver and registering it with the upper-half via the ``mdio_register()`` function.
+Each call to this function with a distinct lower-half driver creates a new, unique bus handle, allowing the system to manage several MDIO buses concurrently.
+
+.. code-block:: c
+
+    FAR struct mdio_dev_s *mdio_register(FAR struct mdio_lowerhalf_s *lower);
+
+This function accepts the lower-half instance and returns an opaque handle (``FAR struct mdio_dev_s *``),
+which is subsequently used by the PHY driver to interact with the bus.
+
+When a bus instance is no longer required, it should be deallocated by calling the ``mdio_unregister()`` function to ensure proper cleanup of resources.
+
+.. code-block:: c
+
+    int mdio_unregister(FAR struct mdio_dev_s *dev);
+
+This function takes the handle returned by ``mdio_register()`` and releases the associated bus instance.
+
+A (mostly) complete reference implementation for a lower-half driver is available in ``arch/arm/src/stm32h7/stm32_mdio.c``.

Documentation/contributing/making-changes.rst

@@ -265,6 +265,21 @@ squash before submitting the Pull Request:
    happy, they may suggest squashing and merging again to make a single commit. In this case you would repeat steps
    1 through 6.
 
+   .. note::
+
+      NuttX uses a ``CODEOWNERS`` file to help track which users are "experts"
+      on certain NuttX subsystems. Sometimes, this will result in certain
+      reviewers being automatically requested to review your PR if you have
+      modified a file they are marked as a "code owner" for. This is just to
+      help contributors get more relevant reviews from someone who knows the
+      subject area.
+
+      If you've created a new file, let's say for a driver, you can add yourself
+      as a code owner for that file by modifying ``.github/CODEOWNERS``. Read
+      the `GitHub documentation for CODEOWNERS
+      <https://docs.github.com/en/repositories/managing-your-repositorys-settings-and-features/customizing-your-repository/about-code-owners>`_
+      for more information.
+
 How to Include the Suggestions on Your Pull Request?
 ====================================================
 

Documentation/debugging/stackcheck.rst

@@ -6,14 +6,19 @@ Overview
 --------
 
 Currently NuttX supports three types of stack overflow detection:
-    1. Stack Overflow Software Check
+    1. Stack Overflow Software Check During Function Call
-    2. Stack Overflow Hardware Check
+    2. Stack Overflow Software Check During Context Switching
-    3. Stack Canary Check
+    3. Stack Overflow Hardware Check
+    4. Stack Canary Check
 
-The software stack detection includes two implementation ideas:
+The software stack detection during function call includes two implementation ideas:
     1. Implemented by coloring the stack memory
     2. Implemented by comparing the sp and sl registers
 
+The software stack detection during context switching includes two implementation ideas:
+    1. Implemented by coloring the stack memory
+    2. Implemented by checking the bottom memory of the stack and the sp register
+
 Support
 -------
 
@@ -21,8 +26,8 @@ Software and hardware stack overflow detection implementation,
 currently only implemented on ARM Cortex-M (32-bit) series chips
 Stack Canary Check is available on all platforms
 
-Stack Overflow Software Check
+Stack Overflow Software Check During Function Call
------------------------------
+--------------------------------------------------
 
 1. Memory Coloring Implementation Principle
     1. Before using the stack, Thread will refresh the stack area to 0xdeadbeef
@@ -44,6 +49,16 @@ Stack Overflow Software Check
     Usage:
         Enable CONFIG_ARMV8M_STACKCHECK or CONFIG_ARMV7M_STACKCHECK
 
+Stack Overflow Software Check During Context Switching
+------------------------------------------------------
+
+1. Determine by detecting the number of bytes specified at the bottom of the stack.
+2. Check if the sp register is out of bounds.
+
+Usage:
+    Enable CONFIG_STACKCHECK_SOFTWARE
+    You can set the detection length by STACKCHECK_MARGIN
+
 Stack Overflow Hardware Check
 -----------------------------
 

Documentation/guides/cpp_cmake.rst

@@ -29,18 +29,27 @@ Preparation
 
 #. Base NuttX compilation changes
 
-    For this example, load the configuration 'stm32f4discovery:testlibcxx' for building
+    For this example, load the configuration 'stm32f4discovery:nsh' for building (Linux host)
 
     .. code-block:: console
 
        $ cd nuttx
-       $ ./tools/configure.sh stm32f4discovery:testlibcxx
+       $ ./tools/configure.sh -l stm32f4discovery:nsh
+
+    See :ref:`quickstart/compiling_make:Initialize Configuration` for more information about configure.sh tool.
 
     In menuconfig, the main points to be changed on a typical NuttX configuration are the following:
 
-    * Set RTOS Features -> Tasks and Scheduling -> Application entry point to 'hellocpp_main'
+    * RTOS Features -> Tasks and Scheduling -> Application entry point to 'main'
+    * Library Routines -> Have C++ compiler
+    * Library Routines -> Have C++ initialization -> C++ Library -> Toolchain C++ support (you can also choose the basic version or the LLVM one)
+    * Library Routines -> Have C++ initialization -> C++ Library -> C++ low level library select -> GNU low level libsupc++
+    * Library Routines -> Language standard -> choose the version you want - for this example we will use "c++17"
+    * Library Routines -> Enable Exception Support -> to enable to support C++ exceptions - for this example we will select it
+    * Library Routines -> Enable RTTI Support -> to enable to support C++ RTTI features (like dynamic_cast()/typeid()) - for this example we will not enable it
 
-    * Build NuttX and generate the export 
+
+    Build NuttX and generate the export
 
     .. code-block:: console
 
@@ -57,14 +66,12 @@ Creating the project
 
        hellocpp/
        hellocpp/CMakeLists.txt
-       hellocpp/cmake/stm32f4discovery.cmake
+       hellocpp/nuttx-export-12.10.0/
-       hellocpp/nuttx-export-10.0.1/
+       hellocpp/main.cpp
-       hellocpp/src/CMakeLists.txt
+       hellocpp/HelloWorld.h
-       hellocpp/src/main.cpp
+       hellocpp/HelloWorld.cpp
-       hellocpp/src/HelloWorld.h
-       hellocpp/src/HelloWorld.cpp
 
-    The directory 'nuttx-export-10.0.1' is the unzipped content from the file created during
+    The directory 'nuttx-export-12.10.0' is the unzipped content from the file created during
     make export procedure done before.
 
 #. File contents
@@ -73,7 +80,7 @@ Creating the project
 
 .. code-block:: cmake
 
-    cmake_minimum_required(VERSION 3.2...3.15)
+    cmake_minimum_required(VERSION 3.12...3.31)
 
     project(HelloCpp
             VERSION 1.0
@@ -82,159 +89,63 @@ Creating the project
 
     set(CMAKE_CXX_STANDARD 17)
     set(CMAKE_CXX_STANDARD_REQUIRED ON)
-    # set(CMAKE_CXX_EXTENSIONS OFF)
-    set(CMAKE_C_STANDARD 99)
-
-    set(NUTTX_PATH "${CMAKE_SOURCE_DIR}/nuttx-export-10.0.1")
-
-    include(cmake/stm32f4discovery.cmake)
-
-    set(AC_COMMON_FLAGS "${AC_COMMON_FLAGS} -Wall -Wshadow -Wundef -fno-strict-aliasing -Os")
-    set(AC_COMMON_FLAGS "${AC_COMMON_FLAGS} -D_DEBUG -D_LIBCPP_BUILD_STATIC -D_LIBCPP_NO_EXCEPTIONS ")
-    set(AC_COMMON_FLAGS "${AC_COMMON_FLAGS} -fno-exceptions -fcheck-new -fno-rtti -pedantic ")
-    set(AC_COMMON_FLAGS "${AC_COMMON_FLAGS} -nostdinc++")
-
-    set(AC_DEFINES "${AC_DEFINES} -DCONFIG_WCHAR_BUILTIN")
-
-    include_directories(
-            src
-            ${NUTTX_PATH}/include
-            ${NUTTX_PATH}/include/libcxx
-            ${NUTTX_PATH}/arch/chip
-    )
-
-    set(EXE_NAME hellocpp)
-    set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${AC_HW_FLAGS} ${AC_DEFINES}")
-    set(CMAKE_CXX_FLAGS     "${AC_HW_FLAGS} ${AC_DEFINES} ${AC_COMMON_FLAGS} ${AC_CXX_EXTRA_FLAGS}")
-    if (PARAM_DEBUG)
-        set(CMAKE_CXX_FLAGS     "${CMAKE_CXX_FLAGS} -g")
-    endif()
-    
-    set(CMAKE_SKIP_RPATH ON)
-    set(CMAKE_CXX_LINK_EXECUTABLE "${CMAKE_LINKER} ${AC_LINKER_FLAGS} -o ${EXE_NAME}.elf <OBJECTS> <LINK_LIBRARIES>")
-    set(BUILD_SHARED_LIBS OFF)
-    add_subdirectory(src)
-
-* hellocpp/cmake/stm32f4discovery.cmake
-
-.. code-block:: cmake
-    
-    set(CMAKE_SYSTEM_NAME Generic)
-    set(CMAKE_SYSTEM_PROCESSOR arm)
-
-    set(MCU_LINKER_SCRIPT "${NUTTX_PATH}/scripts/ld.script")
-
-    set(COMPILER_PREFIX arm-none-eabi-)
-
-    # cmake-format: off
-    set(CMAKE_C_COMPILER    ${COMPILER_PREFIX}gcc)
-    set(CMAKE_CXX_COMPILER  ${COMPILER_PREFIX}g++)
-    set(CMAKE_AR            ${COMPILER_PREFIX}ar)
-    set(CMAKE_RANLIB        ${COMPILER_PREFIX}ranlib)
-    set(CMAKE_LINKER        ${COMPILER_PREFIX}ld)
-    set(CMAKE_ASM_COMPILER  ${COMPILER_PREFIX}gcc)
-    set(CMAKE_OBJCOPY       ${COMPILER_PREFIX}objcopy)
-    set(CMAKE_OBJDUMP       ${COMPILER_PREFIX}objdump)
-    set(CMAKE_SIZE          ${COMPILER_PREFIX}size)
-
-    set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
-    set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
-    set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
-    set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
-
-    set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
-
-    set(AC_HW_FLAGS         "-mcpu=cortex-m4 -mthumb -mfloat-abi=soft ")
-    set(AC_HW_FLAGS         "${AC_HW_FLAGS} -isystem ${NUTTX_PATH}/include")
-    set(AC_HW_FLAGS         "${AC_HW_FLAGS} -pipe")
-
-    set(AC_LINKER_FLAGS     "--entry=__start -nostdlib -T${MCU_LINKER_SCRIPT}")
-
-* hellocpp/src/CMakeLists.txt
-
-.. code-block:: cmake
-   
-    set(HEADER_FILES
-            HelloWorld.h
-    )
 
     set(SOURCE_FILES
-            HelloWorld.cpp
+            ${CMAKE_CURRENT_SOURCE_DIR}/HelloWorld.cpp
+            ${CMAKE_CURRENT_SOURCE_DIR}/main.cpp
     )
 
-    link_directories(${EXE_NAME} ${NUTTX_PATH}/libs)
+    set(EXE_NAME "hello")
-
+    add_executable(${EXE_NAME} ${SOURCE_FILES})
-    add_executable(${EXE_NAME} ${SOURCE_FILES} main.cpp ${HEADER_FILES})
 
     add_custom_command(
             TARGET ${EXE_NAME}
             POST_BUILD
-            COMMAND ${CMAKE_OBJCOPY} ARGS -S -O binary ${CMAKE_BINARY_DIR}/${EXE_NAME}.elf ${CMAKE_BINARY_DIR}/${EXE_NAME}.bin
+            COMMAND ${CMAKE_OBJCOPY} ARGS -S -O binary ${CMAKE_BINARY_DIR}/${EXE_NAME} ${CMAKE_BINARY_DIR}/${EXE_NAME}.bin
-    )
 
-    target_link_libraries(${EXE_NAME} --start-group)
 
-    target_link_libraries(${EXE_NAME} sched)
+* hellocpp/main.cpp
-    target_link_libraries(${EXE_NAME} drivers)
-    target_link_libraries(${EXE_NAME} boards)
-    target_link_libraries(${EXE_NAME} c)
-    target_link_libraries(${EXE_NAME} mm)
-    target_link_libraries(${EXE_NAME} arch)
-    target_link_libraries(${EXE_NAME} xx)
-    target_link_libraries(${EXE_NAME} apps)
-    target_link_libraries(${EXE_NAME} fs)
-    target_link_libraries(${EXE_NAME} binfmt)
-    target_link_libraries(${EXE_NAME} board)
-    target_link_libraries(${EXE_NAME} gcc)
-    target_link_libraries(${EXE_NAME} supc++)
-
-    target_link_libraries(${EXE_NAME} --end-group)
-
-* hellocpp/src/main.cpp
 
 .. code-block:: c++
 
+    #include <memory>
+
     #include "HelloWorld.h"
-    #include <nuttx/config.h>
 
-    extern "C"
+    extern "C" int main(int, char*[])
     {
-            int hellocpp_main(void)
+        auto pHelloWorld = std::make_shared<CHelloWorld>();
-            {
+        pHelloWorld->HelloWorld();
 
-                    CHelloWorld *pHelloWorld = new CHelloWorld();
+        CHelloWorld helloWorld;
-                    pHelloWorld->HelloWorld();
+        helloWorld.HelloWorld();
 
-                    CHelloWorld helloWorld;
+        return 0;
-                    helloWorld.HelloWorld();
-
-                    delete pHelloWorld;
-                    return 0;
-            }
     }
 
-* hellocpp/src/HelloWorld.h
+
+* hellocpp/HelloWorld.h
 
 .. code-block:: c++
 
-    #ifndef HELLOWORLD_H_
+    #ifndef HELLOWORLD_H
-    #define HELLOWORLD_H_
+    #define HELLOWORLD_H
-
-    #include "nuttx/config.h"
 
     class CHelloWorld
     {
-            public:
+    public:
-                    CHelloWorld();
+        CHelloWorld();
-                    ~CHelloWorld();
+        ~CHelloWorld() = default;
-                    bool HelloWorld(void);
+
-            private:
+        bool HelloWorld();
-                    int mSecret;
+
+    private:
+        int mSecret;
     };
 
     #endif
 
-* hellocpp/src/HelloWorld.cpp
+* hellocpp/HelloWorld.cpp
 
 .. code-block:: c++
 
@@ -243,30 +154,32 @@ Creating the project
 
     #include "HelloWorld.h"
 
-    CHelloWorld::CHelloWorld() {
+    CHelloWorld::CHelloWorld()
-            mSecret = 42;
+    {
-            std::printf("Constructor: mSecret=%d\n",mSecret);
+        mSecret = 42;
+        std::printf("Constructor: mSecret=%d\n",mSecret);
     }
 
-    CHelloWorld::~CHelloWorld() {
 
+    bool CHelloWorld::HelloWorld()
+    {
+        std::printf("HelloWorld: mSecret=%d\n",mSecret);
+
+        std::string sentence = "Hello";
+        std::printf("TEST=%s\n",sentence.c_str());
+
+        if (mSecret == 42)
+        {
+            std::printf("CHelloWorld: HelloWorld: Hello, world!\n");
+            return true;
+        }
+        else
+        {
+            std::printf("CHelloWorld: HelloWorld: CONSTRUCTION FAILED!\n");
+            return false;
+        }
     }
 
-    bool CHelloWorld::HelloWorld(void) {
-            std::printf("HelloWorld: mSecret=%d\n",mSecret);
-
-            std::string sentence = "Hello";
-            std::printf("TEST=%s\n",sentence.c_str());
-
-            if (mSecret == 42) {
-                    std::printf("CHelloWorld: HelloWorld: Hello, world!\n");
-                    return true;
-            }
-            else {
-                    std::printf("CHelloWorld: HelloWorld: CONSTRUCTION FAILED!\n");
-                    return false;
-            }
-    }
 
 Building
 ========
@@ -277,7 +190,7 @@ To launch build, you use the cmake procedure:
 
     $ mkdir build
     $ cd build
-    $ cmake ..
+    $ cmake .. -DCMAKE_TOOLCHAIN_FILE=../nuttx-export-12.10.0/scripts/toolchain.cmake
     $ make
 
-And finally a bin file will be created to be loaded on the board.
+Two binaries are generated: an elf one - useful for debug purpose - and a binary one to be flashed on the board

Documentation/platforms/arm/imxrt/boards/arcx-socket-grid/index.rst

@@ -90,3 +90,14 @@ Configures the NuttShell (nsh) located at examples/nsh.  This NSH
 configuration is focused on low level, command-line driver testing.
 Built-in applications are supported, but none are enabled.  This
 configuration does not support a network.
+
+usbdisk
+-------
+
+This board profile allows to use USB Thumb driver connected to USB port.
+Typically the device will be recognized and created at /dev/sda. The
+user could mount it this way::
+
+    nsh> mount -t vfat /dev/sda /mnt
+
+Note: It is assumed that the USB Flash drive was formatted as FAT32.

Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst

@@ -140,6 +140,20 @@ This configuration configures ADC1_IN3 and ADC1_IN10, which can be
 accessed at the CN9 A0 and A1 pins respectively. Modify
 nucleo-h563zi/src/stm32_adc.c to enable more channels.
 
+adc_watchdog:
+--------------
+
+Test Procedure:
+
+1. Build and flash NuttX with the above Kconfig. Register /dev/adc0 via the board init.
+2. Start continuous conversions (DMA circular enabled) and run the adc example to sanity-check normal operation.
+3. Tie both CH3 and CH10 to GND → verified no AWD interrupts and ADC continues normally.
+4. Tie either CH3 or CH10 to 3.3 V with AWD1 set to “all channels” → ISR fires as expected; conversions continue; AWD1 IRQ is disabled by the ISR.
+5. Switch to single-channel AWD1.
+6. Select CH3: drive CH3 above the window → ISR fires; drive CH10 above the window → no ISR.
+7. Select CH10: mirror the above.
+8. Re-enable the watchdog interrupt using the driver IOCTL; confirm subsequent out-of-window events retrigger the ISR.
+
 usbnsh:
 --------
 

Documentation/platforms/arm/stm32h7/boards/weact-stm32h750/index.rst

@@ -0,0 +1,275 @@
+===============
+weact-stm32h750
+===============
+
+.. tags:: chip:stm32, chip:stm32h7, chip:stm32h750
+
+This page discusses issues unique to NuttX configurations for the
+WeAct STM32H750 board.
+
+Board information
+=================
+
+This board was release by WeAct Studio in 2020 and developed based on
+STM32H750VB microcontroller. The STM32H750VB is a Cortex-M7 core with 128KBytes
+Flash memory and 1MByte SRAM.
+
+The board features:
+  - USB-C power supply
+  - SWD connector
+  - Crystal for HS 25MHz
+  - Crystal for RTC 32.768KHz
+  - 1 user LED
+  - 1 MicroSD connector supporting 1 or 4-bit bus
+  - 1 USB 2.0 Host/Device
+  - 2 SPI Flash
+  - 1 OLED display
+  - 1 Camera
+
+Board documentation: https://github.com/WeActStudio/MiniSTM32H7xx
+
+BOARD-LED
+=========
+
+The WeAct STM32H750 has 1 software controllable LED.
+
+  ==== =====
+  LED  PINS
+  ==== =====
+  E3   PE3
+  ==== =====
+
+UART/USART
+==========
+
+The WeAct STM32H750 uses the USART1 for serial debug messages.
+
+USART1
+------
+
+  ====== =====
+  USART1 PINS
+  ====== =====
+  TX     PB14
+  RX     PB15 
+  ====== =====
+
+
+SDMMC
+======
+
+The WeAct STM32H750 has one SDCard slot connected as below:
+
+  ========== =====
+  SDMMC1     PINS
+  ========== =====
+  SDMMC_D0   PC8
+  SDMMC_D1   PC9
+  SDMMC_D2   PC10
+  SDMMC_D3   PC11
+  SDMMC_DK   PC12
+  ========== =====
+
+  =============== =====
+  GPIO            PINS
+  =============== =====
+  SDCARD_DETECTED PD4
+  =============== =====
+
+==============
+
+Each weact-stm32h750 configuration is maintained in a sub-directory and
+can be selected as follows::
+
+  ./tools/configure.sh weact-stm32h750:<subdir>
+
+Where <subdir> is one of the following:
+
+Flashing
+========
+
+This board can be flashed/programmed via DFU or SWD. The DFU is an alternative
+when you don't have a SWD programmer, but SWD offers more than flashing: you can
+use it for code debugging with GDB. So it is recommended that you have a SWD
+tool on your workbench.
+
+DFU
+---
+
+First put the board in DFU mode: press and hold Boot0 (B0) button and click and release the reset (NR) button with the board powered over USB cable. Other alternative is just removing the USB cable, then press and hold the B0 button and connect the USB while still holding that button.
+
+You can confirm the board is in DFU mode using dmesg::
+
+     $ sudo dmesg     
+     [ 1219.182108] usb 3-5: New USB device found, idVendor=0483, idProduct=df11, bcdDevice= 2.00
+     [ 1219.182120] usb 3-5: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+     [ 1219.182122] usb 3-5: Product: DFU in FS Mode
+     [ 1219.182124] usb 3-5: Manufacturer: STMicroelectronics
+     [ 1219.182125] usb 3-5: SerialNumber: 200000500000
+
+You need to have dfu-util installed in your computer::
+
+     $ sudo apt install dfu-util
+
+Now list the DFU unities::
+
+     $ sudo dfu-util -l
+     dfu-util 0.11
+     Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
+     Copyright 2010-2021 Tormod Volden and Stefan Schmidt
+     This program is Free Software and has ABSOLUTELY NO WARRANTY
+     Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
+     Found DFU: [0483:df11] ver=0200, devnum=5, cfg=1, intf=0, path="3-5", alt=1, name="@Option Bytes   /0x5200201C/01*128 e", serial="200000500000"
+     Found DFU: [0483:df11] ver=0200, devnum=5, cfg=1, intf=0, path="3-5", alt=0, name="@Internal Flash   /0x08000000/16*128Kg", serial="200000500000"
+
+Finally flash the compiled nuttx.bin::
+
+     $ sudo dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D nuttx.bin
+     dfu-util: Warning: Invalid DFU suffix signature
+     dfu-util: A valid DFU suffix will be required in a future dfu-util release
+     Opening DFU capable USB device...
+     Device ID 0483:df11
+     Device DFU version 011a
+     Claiming USB DFU Interface...
+     Setting Alternate Interface #0 ...
+     Determining device status...
+     DFU state(2) = dfuIDLE, status(0) = No error condition is present
+     DFU mode device DFU version 011a
+     Device returned transfer size 1024
+     DfuSe interface name: "Internal Flash   "
+     Downloading element to address = 0x08000000, size = 141324
+     Erase      [=========================] 100%       141324 bytes
+     Erase    done.
+     Download   [=========================] 100%       141324 bytes
+     Download done.
+     File downloaded successfully
+     Submitting leave request...
+     dfu-util: Error during download get_status
+
+You can ignore that get_status error and restart the board to get nsh> working over serial or USB (depending on selected config: nsh or usbnsh).
+
+SWD
+---
+
+Another option to flash/program your board is via SWD interface. In this case you will need a SWD programmer compatible with OpenOCD like STLink-V2 or other.
+
+Install openocd on your computer::
+
+     $ sudo apt install openocd
+
+Connect the SWD wires from STLink-V2 (or other programmer) this way:
+
+============== ===============
+SWD Programmer Weact-STM32H750
+============== ===============
+SWDIO          DIO
+GND            GND
+SWCLK          CLK
+============== ===============
+
+Then run this command in the same directory where your nuttx.bin is located::
+
+     $ openocd -f interface/stlink.cfg -f target/stm32h7x.cfg -c "init" -c "reset halt" -c "flash write_image erase nuttx.bin 0x08000000" -c "reset run"
+     Open On-Chip Debugger 0.11.0+dev-gcf314db1f-dirty (2025-05-17-16:09)
+     Licensed under GNU GPL v2
+     Info : 49 4 adapter.c:111 adapter_init(): clock speed 1800 kHz
+     Info : 67 7 stlink_usb.c:1438 stlink_usb_version(): STLINK V2J17S4 (API v2) VID:PID 0483:3748
+     Info : 69 8 stlink_usb.c:1474 stlink_usb_check_voltage(): Target voltage: 3.268800
+     Info : 82 112 cortex_m.c:2325 cortex_m_examine(): [stm32h7x.cpu0] Cortex-M7 r1p1 processor detected
+     Info : 127 120 cortex_m.c:2440 cortex_m_examine(): [stm32h7x.cpu0] target has 8 breakpoints, 4 watchpoints
+     User : 128 120 target.c:777 target_examine_one(): [stm32h7x.cpu0] Target successfully examined.
+     Info : 193 165 gdb_server.c:4825 gdb_target_start(): starting gdb server for stm32h7x.cpu0 on 3333
+     Info : 194 165 server.c:359 add_service(): Listening on port 3333 for gdb connections
+     The core #0 listens on 3333.
+     ICEman is ready to use.
+     User : 259 196 armv7m.c:740 armv7m_arch_state(): target halted due to debug-request, current mode: Thread
+     xPSR: 0x01000000 pc: 0x080013bc msp: 0x24001e28
+     Info : 266 197 stm32h7x.c:791 stm32x_probe(): Device: STM32H74x/75x
+     Info : 270 197 stm32h7x.c:819 stm32x_probe(): flash size probed value 2048k
+     Info : 271 197 stm32h7x.c:849 stm32x_probe(): STM32H7 flash has dual banks
+     Info : 272 197 stm32h7x.c:869 stm32x_probe(): Bank (0) size is 1024 kb, base address is 0x08000000
+     Info : 273 197 core.c:876 flash_write_unlock_verify(): Padding image section 0 at 0x0802280c with 20 bytes (bank write end alignment)
+     Warn : 275 198 core.c:552 flash_iterate_address_range_inner(): Adding extra erase range, 0x08022820 .. 0x0803ffff
+     User : 2674 4879 options.c:63 configuration_output_handler(): auto erase enabled
+     wrote 141344 bytes from file nuttx.bin in 4.682974s (29.475 KiB/s)
+     User : 2675 4879 options.c:63 configuration_output_handler():
+     Info : 2714 4889 server.c:359 add_service(): Listening on port 6666 for tcl connections
+     Info : 2715 4889 server.c:359 add_service(): Listening on port 4444 for telnet connections
+
+After you get the message "wrote xxxxxx bytes from file nuttx.bin" you can press Ctrl+C (``^C``) to finish the application. Now you can reset the board and get access to the NSH terminal.
+
+==============
+
+Configuration Directories
+-------------------------
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a serial console on UART1.
+
+usbnsh
+------
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a serial console over USB.
+
+After flashing and reboot your board you should see in your dmesg logs::
+
+       [ 2638.948089] usb 1-1.4: new full-speed USB device number 16 using xhci_hcd
+       [ 2639.054432] usb 1-1.4: New USB device found, idVendor=0525, idProduct=a4a7, bcdDevice= 1.01
+       [ 2639.054437] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+       [ 2639.054438] usb 1-1.4: Product: CDC/ACM Serial
+       [ 2639.054440] usb 1-1.4: Manufacturer: NuttX
+       [ 2639.054441] usb 1-1.4: SerialNumber: 0
+       [ 2639.074861] cdc_acm 1-1.4:1.0: ttyACM0: USB ACM device
+       [ 2639.074886] usbcore: registered new interface driver cdc_acm
+       [ 2639.074887] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
+
+You may need to press **ENTER** 3 times before the NSH shows up.
+
+sdcard
+------
+
+Configures the NuttShell (nsh) and enables SD card support. The board has an onboard microSD slot that should be
+automatically registered as the block device /dev/mmcsd0 when an SD card is present.
+
+The SD card can then be mounted by the NSH commands::
+
+    nsh> mount -t vfat /dev/mmcsd0 /mnt
+    nsh> mount
+    nsh> echo "Hello World!!" > /mnt/test_file.txt
+    nhs> ls /mnt/
+    test_file.txt
+    nsh> cat /mnt/test_file.txt
+    Hello World!!
+
+st7735
+------
+
+This config enables the ST7735 0.96" Display (80*160) on weact-stm32h750 board::
+
+     nsh> fb
+     VideoInfo:
+           fmt: 11
+          xres: 80
+          yres: 160
+       nplanes: 1                                               
+     PlaneInfo (plane 0):                                       
+         fbmem: 0x38000d50                                      
+         fblen: 25600                                           
+        stride: 160                                             
+       display: 0                                               
+           bpp: 16                                              
+     Mapped FB: 0x38000d50                                      
+      0: (  0,  0) ( 80,160)                                    
+      1: (  7, 14) ( 66,132)                                    
+      2: ( 14, 28) ( 52,104)                                    
+      3: ( 21, 42) ( 38, 76)                                    
+      4: ( 28, 56) ( 24, 48)                                    
+      5: ( 35, 70) ( 10, 20)                                    
+     Test finished                                              
+     nsh> 
+
+

Documentation/platforms/arm64/bcm2711/index.rst

@@ -26,7 +26,7 @@ Supported Peripherals
 ======================== =======
 Peripheral               Support
 ======================== =======
-I2C                      Partial (able to read, that's it)
+I2C                      Full interrupt-based support, all interfaces work and tested.
 UART                     Mini UART yes, PL011 no
 GPIO                     Partial
 PWM                      No

Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt

@@ -1,110 +0,0 @@
-Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-1. The buildroot package can be used to build an M16C toolchain.  The toolchain
-   buildroot can be downloaded from buildroot in the NuttX GIT.  Insructions
-   for building the toolchain are provided below.
-
-   However, the target cannot be built because the GNU m16c-nuttx-elf-ld link fails with
-   the following message:
-
-     m32c-nuttx-elf-ld: BFD (GNU Binutils) 2.19 assertion fail /home/Owner/projects/nuttx/buildroot/toolchain_build_m32c/binutils-2.19/bfd/elf32-m32c.c:482
-
-   Where the reference line is:
-
-     /* If the symbol is out of range for a 16-bit address,
-        we must have allocated a plt entry.  */
-     BFD_ASSERT (*plt_offset != (bfd_vma) -1);
-
-   No workaround is known at this time.  This is a show stopper for M16C.
-
-2. A supported version of the M16C toolchain is available here:
-
-     http://www.kpitgnutools.com/index.php
-
-   This download is free but requires registration.  Unfortunately, this v0901 of
-   this toolchain shows the same behavior:
-
-   c:\Hew3\Tools\KPIT Cummins\GNUM16CM32C-ELF\v0901\m32c-elf\bin\m32c-elf-ld.exe: BFD (GNU Binutils) 2.19-GNUM16CM32C_v0901 assertion fail /home/kpit/fsfsrc/binutils-2.19/bfd/elf32-m32c.c:482
-
-It is possible that this error message may be telling me -- a very roundabout way --
-that I have exceeded the FLASH region, but I think that unlikely (it is difficult
-to know if the link does not complete gracefully).
-
-BUILDING THE R8C/M16C/M32C GNU TOOLCHAIN USING BUILDROOT
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-NOTE:  See the toolchain issues above -- you may not want to waste your time.
-
-1. CD to the correct directory.
-
-   Change to the directory just above the NuttX installation.  If <nuttx-dir> is
-   where NuttX is installed, then cd to <nuttx-dir>/..
-
-2. Get and Install the buildroot Module
-
-   a. Using a release tarball:
-
-     cd <nuttx-dir>/..
-     Download the appropriate buildroot package.
-     unpack the buildroot package
-     rename the directory to buildroot
-
-   b. Using GIT
-
-     Check out the buildroot module. GIT checkout instructions:
-
-        git clone https://patacongo@bitbucket.org/nuttx/buildroot.git buildroot
-
-     Make the archive directory:
-
-       mkdir archive
-
-     The <nuttx-dir>/../buildroot is where the toolchain is built;
-     The <nuttx-dir>/../archive directory is where toolchain sources will be downloaded.
-
-3. Make sure that NuttX is configured
-
-     cd <nuttx-dir>
-     tools/configure.sh <nuttx-configuration>
-
-4. Configure and Make the buildroot
-
-     cd <buildroot-dir>
-     cp boards/m32c-defconfig-4.2.4 .config
-     make oldconfig
-     make
-
-   This will download the large source packages for the toolchain and build the toolchain.
-   The resulting binaries will be under buildroot/build_m32c.  There will also be a
-   large build directory called toolchain_build_m32c; this directory can be removed once
-   the build completes successfully.
-
-Cygwin GCC BUILD NOTES
-^^^^^^^^^^^^^^^^^^^^^^
-   On Cygwin, the buildroot 'make' command will fail with an error like:
-
-   "...
-      build/genchecksum cc1-dummy > cc1-checksum.c
-      opening cc1-dummy: No such file or directory
-   ..."
-
-   This is caused because on Cygwin, host executables will be generated with the extension .exe
-   and, apparently, the make variable "exeext" is set incorrectly.  A work around after the
-   above occurs is:
-
-      cd toolchain_build_m32c/gcc-4.2.4-initial/gcc	# Go to the directory where error occurred
-      mv cc1-dummy.exe cc1-dummy			# Rename the executable without .exe
-      rm cc1-checksum.c					# Get rid of the bad generated file
-
-   Then resume the buildroot make:
-
-      cd -						# Back to the buildroot make directory
-      make						# Restart the build
-
-   GCC is built twice.  First a initial, "bootstrap" GCC is produced in
-   toolchain_build_m32c/gcc-4.2.4-initial, then the final GCC is produced in
-   toolchain_build_m32c/gcc-4.2.4-final.  The above error will occur twice:  Once for
-   the initial GCC build (see above) and once for the final GCC build. For the final GCC
-   build, the workaround is the same except that the directory will be
-   toolchain_build_m32c/gcc-4.2.4-final/gcc.

Documentation/platforms/renesas/m16c/boards/skp16c26/index.rst

@@ -2,5 +2,136 @@
 SKP16C26
 ========
 
-.. include:: README.txt
+.. tags:: arch:renesas
-   :literal:
+
+1. The buildroot package can be used to build an M16C toolchain. The toolchain
+   buildroot can be downloaded from buildroot in the NuttX GIT. Instructions for
+   building the toolchain are provided below.
+
+   However, the target cannot be built because the GNU m16c-nuttx-elf-ld link
+   fails with the following message:
+
+   .. code:: console
+
+      m32c-nuttx-elf-ld: BFD (GNU Binutils) 2.19 assertion fail /home/Owner/projects/nuttx/buildroot/toolchain_build_m32c/binutils-2.19/bfd/elf32-m32c.c:482
+
+   Where the reference line is:
+
+   .. code:: c
+
+      /* If the symbol is out of range for a 16-bit address,
+         we must have allocated a plt entry.  */
+      BFD_ASSERT (*plt_offset != (bfd_vma) -1);
+
+   No workaround is known at this time. This is a show stopper for M16C.
+
+2. A supported version of the M16C toolchain is available here:
+
+   http://www.kpitgnutools.com/index.php
+
+   This download is free but requires registration. Unfortunately, this v0901 of
+   this toolchain shows the same behavior:
+
+   .. code:: console
+
+      c:\Hew3\Tools\KPIT Cummins\GNUM16CM32C-ELF\v0901\m32c-elf\bin\m32c-elf-ld.exe: BFD (GNU Binutils) 2.19-GNUM16CM32C_v0901 assertion fail /home/kpit/fsfsrc/binutils-2.19/bfd/elf32-m32c.c:482
+
+   It is possible that this error message may be telling me -- a very roundabout way --
+   that I have exceeded the FLASH region, but I think that unlikely (it is difficult
+   to know if the link does not complete gracefully).
+
+Building the R8C/M16C/M32C GNU Toolchain Using Buildroot
+========================================================
+
+.. warning::
+
+   See the toolchain issues above -- you may not want to waste your time.
+
+1. CD to the correct directory.
+
+   Change to the directory just above the NuttX installation.  If <nuttx-dir> is
+   where NuttX is installed, then cd to <nuttx-dir>/..
+
+2. Get and Install the buildroot Module
+
+   a. Using a release tarball:
+
+      .. code:: console
+
+         $ cd <nuttx-dir>/..
+
+      Download the appropriate buildroot package.
+      unpack the buildroot package
+      rename the directory to buildroot
+
+   b. Using GIT
+
+     Check out the buildroot module. GIT checkout instructions:
+
+     .. code:: console
+
+        $ git clone https://patacongo@bitbucket.org/nuttx/buildroot.git buildroot
+
+     Make the archive directory:
+
+     .. code:: console
+
+        $ mkdir archive
+
+     The ``<nuttx-dir>/../buildroot`` is where the toolchain is built;
+     The ``<nuttx-dir>/../archive`` directory is where toolchain sources will be downloaded.
+
+3. Make sure that NuttX is configured
+
+   .. code:: console
+
+     $ cd <nuttx-dir>
+     $ tools/configure.sh <nuttx-configuration>
+
+4. Configure and Make the buildroot
+
+   .. code:: console
+
+      $ cd <buildroot-dir>
+      $ cp boards/m32c-defconfig-4.2.4 .config
+      $ make oldconfig
+      $ make
+
+   This will download the large source packages for the toolchain and build the toolchain.
+   The resulting binaries will be under buildroot/build_m32c.  There will also be a
+   large build directory called toolchain_build_m32c; this directory can be removed once
+   the build completes successfully.
+
+Cygwin GCC BUILD NOTES
+======================
+
+On Cygwin, the buildroot 'make' command will fail with an error like:
+
+.. code:: console
+
+   build/genchecksum cc1-dummy > cc1-checksum.c
+   opening cc1-dummy: No such file or directory
+
+This is caused because on Cygwin, host executables will be generated with the
+extension .exe and, apparently, the make variable "exeext" is set incorrectly. A
+workaround after the above occurs is:
+
+.. code:: console
+
+   $ cd toolchain_build_m32c/gcc-4.2.4-initial/gcc	# Go to the directory where error occurred
+   $ mv cc1-dummy.exe cc1-dummy			# Rename the executable without .exe
+   $ rm cc1-checksum.c					# Get rid of the bad generated file
+
+Then resume the buildroot make:
+
+.. code:: console
+
+   $ cd -						# Back to the buildroot make directory
+   $ make						# Restart the build
+
+GCC is built twice. First an initial "bootstrap" GCC is produced in
+toolchain_build_m32c/gcc-4.2.4-initial, then the final GCC is produced in
+toolchain_build_m32c/gcc-4.2.4-final. The above error will occur twice: Once for
+the initial GCC build (see above) and once for the final GCC build. For the
+final GCC build, the workaround is the same except that the directory will be
+toolchain_build_m32c/gcc-4.2.4-final/gcc.

Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/README.txt

@@ -1,419 +0,0 @@
-README
-======
-
-This README file discusses the port of NuttX to “GR-ROSE” board produced by Gadget Renesas.This board features the RX65N (R5F565NEHDFP 100pin QFP)
-
-Contents
-========
-
-  - Board Features
-  - Status/Open Issues
-  - Serial Console
-  - LEDs
-  - Networking
-  - Contents
-  - RTC
-  - USB Device
-  - RSPI
-  - RIIC
-  - DTC
-  - USB Host
-  - USB Host Hub
-  - Debugging
-
-Board Features
-==============
-- Micro controller - RX65N (R5F565NEHDFP 100pin QFP) RXv2 core [34 CoreMark/mA]
-- ROM/RAM - 2MB/640KB
-- Operating Frequency	- 120MHz(12MHz 10 Multiplication)
-- RTC Clock - 32.768kHz
-- Sensors - Temperature(inside MCU)
-- ROS I/F	- Ethernet, USB(rosserial)
-- Serial Servo I/F -	TTL x 4, RS-485 x 1
-- Analog I/F	- ADC(12bit) x 6, DAC x 1
-- Wireless - IEEE 802.11b/g/n
-- PMOD I/F - 1 (I2C, SPI, UART)
-- External power supply - USB VBUS or 4.5V～18V
-- Supply to external - 3.3V, 5V
-
-See the RX65N GRROSE website for further information about this board:
-
-  - http://gadget.renesas.com/en/product/rose.html
-
-Serial Console
-==============
-RX65N GRROSE supports 12 serial ports (SCI0 - SCI12), however only 5 ports can be tested(SCI0, SCI1, SCI2,
-SCI5 & SCI6).
-
-Please find the pin configurations for SCI0, SCI1, SCI2, SCI5 & SCI6
-
-SCI0 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function
------------
-  P21   RXD0
-  P20   TXD0
-------------
-
-SCI1 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function
------------
-  P30   RXD1
-  P26   TXD1
-------------
-
-SCI2 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function
------------
-  P12   RXD2
-  P13   TXD2
-------------
-
-SCI3 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function    (connected to WiFi module)
------------
-  P25   RXD3
-  P23   TXD3
-------------
-
-SCI5 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function
------------
-  PC2   RXD5
-  PC3   TXD5
-------------
-
-SCI6 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function
------------
-  P33   RXD6
-  P32   TXD6
-------------
-
-SCI8 Pin Configuration :
-
------------
-RX65N GRROSE
-  Function   (Half duplication mode with RS485 driver)
------------
-  PC6   RXD8
-  PC7   TXD8
-  PC5   Direction (L=TX, H=RX)
-
-Serial Connection Configuration
---------------------------
-1. GRROSE board needs to be connected to PC terminal, using USB to Serial Chip.
-2. Connect TX of USB to serial chip to RX of SCIX(0,1,2,5,6)
-3. Connect RX of USB to serial chip to TX of SCIX(0,1,2,5,6)
-4. Connect GND to GND pin.
-5. Configure Teraterm to 115200 baud.
-
-LEDs
-====
-
-  The RX65N GRROSE board has 2 LED's, 1 Power LED(LED3) and 2 User LED's(LED1, LED2),which are enabled through software.
-
-  If enabled the LED is simply turned on when the board boots
-  successfully, and is blinking on panic / assertion failed.
-
-Networking
-==========
-
-Ethernet Connections
------------
-
-  ------        ---------
-  RX65N
-  GRROSE        Ethernet
-  Pin           Function
-  ------        ---------
-  PA4           ET0_MDC
-  PA3           ET0_MDIO
-  PB2           REF50CK0
-  PB7           RMII0_CRS_DV
-  PB1           RMII0_RXD0
-  PB0           RMII0_RXD1
-  PB3           RMII0_RX_ER
-  PB5           RMII0_ETXD0
-  PB6           RMII0_ETXD1
-  PB4           RMII0_TXD_EN
-  PA5           ET0_LINKSTA
-  PA6_ET_RST    ETHER reset
-  ------         ---------
-NuttX Configurations
----------------
-The following configurations, need to be enabled for network.
-
-CONFIG_RX65N_EMAC=y    : Enable the EMAC Peripheral for RX65N
-CONFIG_RX65N_EMAC0=y   : Enable the EMAC Peripheral for RX65N
-CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register on LAN8720A
-CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18  : Needed for LAN8720A
-CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08  : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14   : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04   : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : "    " " " "     "
-CONFIG_RX65N_EMAC0_RMII=y
-CONFIG_RX65N_EMAC0_PHYADDR=0 : LAN8720A PHY is at address 1
-
-CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed
-CONFIG_SCHED_HPWORK=y    :  High Priority Work queue support
-CONFIG_SCHED_LPWORK=y    :  Low Priority Work queue support
-
-Using the network with NSH
---------------------------
-The IP address is configured using DHCP, using the below mentioned configurations :
-
-The IP address is configured using DHCP, using the below mentioned configurations :
-
-CONFIG_NETUTILS_DHCPC=y
-CONFIG_NETUTILS_DHCPD=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NETINIT_DHCPC=y
-
-nsh> ifconfig
-  eth0    HWaddr 00:e0:de:ad:be:ef at UP
-          IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
-
-You can use ping to test for connectivity to the host (Careful,
-Window firewalls usually block ping-related ICMP traffic).  On the
-target side, you can:
-
-  nsh> ping 10.75.24.250
-  PING 10.75.24.250 56 bytes of data
-  56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
-  10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
-
-On the host side, you should also be able to ping the RX65N-GRROSE:
-
-  $ ping 10.75.24.53
-
-Configure UDP blaster application as mentioned below :
-
-CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801  (10.75.24.1) ------> Gateway IP
-CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
-CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
-
-RSPI
------------
-
-For GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only brought out as
-Pin number 2 and 3 in CN4 is used for MOSIB and MISOB respectively.
-
-USB Host
-=============
-For the RX65N RSK2MB board, to be used as USB Device, the following Jumper settings need to be done
-
-J7     Short Pin 1 & Pin 2
-J16    Short Pin 2 & Pin 3
-
-USB Device
-=============
-For the RX65N RSK2MB board, to be used as USB Device, the following Jumper settings need to be done
-
-J7     Short Pin 2 & Pin 3
-J16    Short Pin 1 & Pin 2
-
-RTC
-==========
-
-NuttX Configurations
----------------
-The configurations listed in Renesas_RX65N_NuttX_RTC_Design.doc need to be enabled.
-
-RTC Testing
-------------------
-The test cases mentioned in Renesas_RX65N_RTC_Test_Cases.xls are to be executed
-as part of RTC testing.
-
-The following configurations are to be enabled as part of testing RTC examples.
-CONFIG_EXAMPLES_ALARM
-CONFIG_EXAMPLES_PERIODIC
-CONFIG_EXAMPLES_CARRY
-
-USB Device Configurations
---------------------------
-The following configurations need to be enabled for USB Device
-
-CONFIG_USBDEV
-CONFIG_CDCACM
-CONFIG_STDIO_BUFFER_SIZE=64
-CONFIG_STDIO_LINEBUFFER
-
-USB Device Testing
-------------------------
-The following testing is executed as part of USB Device testing on RX65N target for GRROSE board
-
-echo "This is a test for USB Device" > /dev/ttyACM0
-
-xd 0 0x20000 > /dev/ttyACM0
-
-The output of the commands mentioned above should be seen on the USB Device COM port on teraterm
-
-RSPI Configurations
---------------------------
-The following configurations need to be enabled for RSPI
-
-CONFIG_SYSTEM_SPITOOL=y
-
-RSPI Testing
-------------------------
-The following testing is executed as part of RSPI testing on RX65N target for GRROSE board
-
-On GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only brought out.
-
-Following command can be used for testing RSPI communication to slave device.
-spi exch -b 0 -x 4 aabbccdd
-where b is bus number and x is Number of word to exchange.
-
-RIIC Configurations
---------------------------
-The following configurations need to be enabled for RIIC
-
-CONFIG_SYSTEM_I2CTOOL=y
-
-RIIC Testing
-------------------------
-
-On GRROSE board, none of the RIIC channel pins are brought out in the board so not tested for communication.
-
-DTC Configurations
---------------------------
-The following configurations need to be enabled for DTC.
-
-CONFIG_SYSTEM_SPITOOL=y
-
-DTC Testing
-------------------------
-
-DTC has been tested using RSPI driver.
-
-USB Host Configurations
---------------------------
-The following configurations need to be enabled for USB Host Mode driver to
-support USB HID Keyboard class and MSC Class.
-
-CONFIG_USBHOST=y
-CONFIG_USBHOST_HIDKBD=y
-CONFIG_FS_FAT=y
-CONFIG_EXAMPLES_HIDKBD=y
-
-USB Host Driver Testing
-------------------------
-The Following Class Drivers were tested as mentioned below :
-
-- USB HID Keyboard Class
-On the NuttX Console "hidkbd" application was executed
-
-nsh> hidkbd
-The characters typed from the keyboard were executed correctly.
-
-- USB MSC Class
-
-The MSC device is enumerated as sda in /dev directory.
-
-The block device is mounted using the command as mentioned below :
-
-mount -t vfat /dev/sda /mnt
-
-The MSC device is mounted in /dev directory
-
-The copy command is executed to test the Read/Write functionality
-
-cp /mnt/<file.txt> /mnt/file_copy.txt
-
-USB Host Hub Configurations
---------------------------
-The following configurations need to be enabled for USB Host Mode driver to
-support USB HID Keyboard class and MSC Class.
-
-CONFIG_RX65N_USBHOST=y
-CONFIG_USBHOST_HUB=y
-CONFIG_USBHOST_ASYNCH=y
-CONFIG_USBHOST=y
-CONFIG_USBHOST_HIDKBD=y
-CONFIG_FS_FAT=y
-CONFIG_EXAMPLES_HIDKBD=y
-
-USB Host Hub Driver Testing
-------------------------
-The Following Class Drivers were tested as mentioned below :
-
-- USB HID Keyboard Class
-On the NuttX Console "hidkbd" application was executed
-
-nsh> hidkbd
-The characters typed from the keyboard were executed correctly.
-
-- USB MSC Class
-The MSC device is enumerated as sda in /dev directory.
-
-The block device is mounted using the command as mentioned below :
-
-mount -t vfat /dev/sda /mnt
-
-The MSC device is mounted in /dev directory
-
-The copy command is executed to test the Read/Write functionality
-
-cp /mnt/<file.txt> /mnt/file_copy.txt
-
-Debugging
-==========
-
-1. NuttX needs to be compiled in Cygwin.
-
-The following Configuration needs to be set, in order to do source level debugging.
-
-CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration).
-
-2. Download & Install Renesas e2studio IDE.
-3. Load the project(NuttX built on Cygwin) as Makefile project with existing code
-4. Right click on the project, and select Debug Configurations.
-5. The binary(NuttX) needs to be loaded using E1/E2 Emulator.
-6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used)
-7. Select Connection type as FINE.
-8. Load and run the binary.
-
-Flashing NuttX
-===============
-Alternatively, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin
-
-Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP).
-
-1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated.
-2. Add the following lines in tools/Unix.mk file :
-ifeq ($(CONFIG_MOTOROLA_SREC),y)
-	@echo "CP: nuttx.mot"
-	$(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns nuttx.mot
-endif
-3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format->
-   Select Motorola SREC format.
-4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
-5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool.

Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/ROMFS.txt

@@ -1,89 +0,0 @@
-README
-======
-
-  Overview
-  --------
-  This directory contains logic to support a custom ROMFS system-init script
-  and start-up script.  These scripts are used by by the NSH when it starts
-  provided that CONFIG_ETC_ROMFS=y.  These scripts provide a ROMFS volume
-  that will be mounted at /etc and will look like this at run-time:
-
-    NuttShell (NSH) NuttX-8.2
-    nsh> ls -Rl /etc
-    /etc:
-     dr-xr-xr-x       0 .
-     -r--r--r--      20 group
-     dr-xr-xr-x       0 init.d/
-     -r--r--r--      35 passwd
-    /etc/init.d:
-     dr-xr-xr-x       0 ..
-     -r--r--r--     110 rcS
-     -r--r--r--     110 rc.sysinit
-    nsh>
-
-  /etc/init.d/rc.sysinit is system init script; /etc/init.d/rcS is the start-up
-  script; /etc/passwd is a the password file.  It supports a single user:
-
-    USERNAME:  admin
-    PASSWORD:  Administrator
-
-    nsh> cat /etc/passwd
-    admin:8Tv+Hbmr3pLVb5HHZgd26D:0:0:/
-
-  The encrypted passwords in the provided passwd file are only valid if the
-  TEA key is set to:  012345678 9abcdef0 012345678 9abcdef0.  Changes to either
-  the key or the password word will require regeneration of the nsh_romfimg.h
-  header file.
-
-  The format of the password file is:
-
-    user:x:uid:gid:home
-
-  Where:
-    user:  User name
-    x:     Encrypted password
-    uid:   User ID (0 for now)
-    gid:   Group ID (0 for now)
-    home:  Login directory (/ for now)
-
-  /etc/group is a group file.  It is not currently used.
-
-    nsh> cat /etc/group
-    root:*:0:root,admin
-
-  The format of the group file is:
-
-    group:x:gid:users
-
-  Where:
-    group:  The group name
-    x:      Group password
-    gid:    Group ID
-    users:  A comma separated list of members of the group
-
-  /etc/init.d/rcS should have the following contents :
-  vi rcS
-  echo "This is NuttX"
-
-  Updating the ROMFS File System
-  ------------------------------
-  The content on the nsh_romfsimg.h header file is generated from a sample
-  directory structure.  That directory structure is contained in the etc/ directory and can be modified per the following steps:
-
-    1. Change directory to etc/:
-
-       cd etc/
-
-    2. Make modifications as desired.
-
-    3. Create the new ROMFS image.
-
-       genromfs -f romfs_img -d etc -V SimEtcVol
-
-    4. Convert the ROMFS image to a C header file
-
-        xxd -i romfs_img >nsh_romfsimg.h
-
-    5. Edit nsh_romfsimg.h, mark both data definitions as 'const' so that
-       that will be stored in FLASH.
-

Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/index.rst

@@ -2,8 +2,576 @@
 RX65N GRROSE
 ============
 
-.. include:: README.txt
+.. tags:: arch:renesas
-   :literal:
 
-.. include:: ROMFS.txt
+This documentation discusses the port of NuttX to “GR-ROSE” board produced by
-   :literal:
+Gadget Renesas. This board features the RX65N (R5F565NEHDFP 100pin QFP).
+
+Board Features
+==============
+
+- Micro controller - RX65N (R5F565NEHDFP 100pin QFP) RXv2 core [34 CoreMark/mA]
+- ROM/RAM - 2MB/640KB
+- Operating Frequency	- 120MHz(12MHz 10 Multiplication)
+- RTC Clock - 32.768kHz
+- Sensors - Temperature(inside MCU)
+- ROS I/F	- Ethernet, USB(rosserial)
+- Serial Servo I/F -	TTL x 4, RS-485 x 1
+- Analog I/F	- ADC(12bit) x 6, DAC x 1
+- Wireless - IEEE 802.11b/g/n
+- PMOD I/F - 1 (I2C, SPI, UART)
+- External power supply - USB VBUS or 4.5V～18V
+- Supply to external - 3.3V, 5V
+
+See the RX65N GRROSE website for further information about this board:
+http://gadget.renesas.com/en/product/rose.html
+
+Serial Console
+==============
+
+RX65N GRROSE supports 12 serial ports (SCI0 - SCI12), however only 5 ports can be tested(SCI0, SCI1, SCI2,
+SCI5 & SCI6).
+
+Please find the pin configurations for SCI0, SCI1, SCI2, SCI5 & SCI6
+
+SCI0 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+P21 RXD0
+P20 TXD0
+=== ========
+
+SCI1 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+P30 RXD1
+P26 TXD1
+=== ========
+
+SCI2 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+P12 RXD2
+P13 TXD2
+=== ========
+
+SCI3 Pin Configuration (connected to WiFi module):
+
+=== ========
+Pin Function
+=== ========
+P25 RXD3
+P23 TXD3
+=== ========
+
+SCI5 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+PC2 RXD5
+PC3 TXD5
+=== ========
+
+SCI6 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+P33 RXD6
+P32 TXD6
+=== ========
+
+SCI8 Pin Configuration (Half duplication mode with RS485 driver):
+
+=== ==========================
+Pin Function
+=== ==========================
+PC6 RXD8
+PC7 TXD8
+PC5 Direction (L=TX, H=RX)
+=== ==========================
+
+Serial Connection Configuration
+-------------------------------
+
+1. GRROSE board needs to be connected to PC terminal, using USB to Serial Chip.
+2. Connect TX of USB to serial chip to RX of SCIX(0,1,2,5,6)
+3. Connect RX of USB to serial chip to TX of SCIX(0,1,2,5,6)
+4. Connect GND to GND pin.
+5. Configure Teraterm to 115200 baud.
+
+LEDs
+====
+
+The RX65N GRROSE board has 2 LED's, 1 Power LED(LED3) and 2 User LED's(LED1,
+LED2),which are enabled through software.
+
+If enabled the LED is simply turned on when the board boots successfully, and is
+blinking on panic / assertion failed.
+
+Networking
+==========
+
+Ethernet Connections
+--------------------
+
+========== ============
+Pin        Function
+========== ============
+PA4        ET0_MDC
+PA3        ET0_MDIO
+PB2        REF50CK0
+PB7        RMII0_CRS_DV
+PB1        RMII0_RXD0
+PB0        RMII0_RXD1
+PB3        RMII0_RX_ER
+PB5        RMII0_ETXD0
+PB6        RMII0_ETXD1
+PB4        RMII0_TXD_EN
+PA5        ET0_LINKSTA
+PA6_ET_RST ETHER reset
+========== ============
+
+NuttX Configurations
+====================
+
+The following configurations need to be enabled for network.
+
+* ``CONFIG_RX65N_EMAC=y``: Enable the EMAC Peripheral for RX65N
+* ``CONFIG_RX65N_EMAC0=y``: Enable the EMAC Peripheral for RX65N
+* ``CONFIG_RX65N_EMAC0_PHYSR=30``: Address of PHY status register on LAN8720A
+* ``CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18``: Needed for LAN8720A
+* ``CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08``
+* ``CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14``
+* ``CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04``
+* ``CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y``
+* ``CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c``
+* ``CONFIG_RX65N_EMAC0_RMII=y``
+* ``CONFIG_RX65N_EMAC0_PHYADDR=0``: LAN8720A PHY is at address 1
+
+* ``CONFIG_SCHED_WORKQUEUE=y``: Work queue support is needed
+* ``CONFIG_SCHED_HPWORK=y``: High Priority Work queue support
+* ``CONFIG_SCHED_LPWORK=y``: Low Priority Work queue support
+
+Using the network with NSH
+--------------------------
+
+The IP address is configured using DHCP, using the below mentioned configurations:
+
+* ``CONFIG_NETUTILS_DHCPC=y``
+* ``CONFIG_NETUTILS_DHCPD=y``
+* ``CONFIG_NSH_DHCPC=y``
+* ``CONFIG_NETINIT_DHCPC=y``
+
+.. code:: console
+
+   nsh> ifconfig
+     eth0    HWaddr 00:e0:de:ad:be:ef at UP
+             IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
+
+You can use ping to test for connectivity to the host (Careful, Window firewalls
+usually block ping-related ICMP traffic). On the target side, you can:
+
+.. code:: console
+
+   nsh> ping 10.75.24.250
+   PING 10.75.24.250 56 bytes of data
+   56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
+   10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
+
+On the host side, you should also be able to ping the RX65N-GRROSE:
+
+.. code:: console
+
+   $ ping 10.75.24.53
+
+Configure UDP blaster application as mentioned below:
+
+.. code:: text
+
+   CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801  (10.75.24.1) ------> Gateway IP
+   CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
+   CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
+
+RSPI
+----
+
+For GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only
+brought out as Pin number 2 and 3 in CN4 is used for MOSIB and MISOB
+respectively.
+
+USB Host
+========
+
+For the RX65N RSK2MB board, to be used as USB Device, the following Jumper
+settings need to be done:
+
+* J7: Short Pin 1 & Pin 2
+* J16: Short Pin 2 & Pin 3
+
+USB Device
+==========
+
+For the RX65N RSK2MB board, to be used as USB Device, the following Jumper
+settings need to be done:
+
+* J7: Short Pin 2 & Pin 3
+* J16: Short Pin 1 & Pin 2
+
+RTC
+===
+
+RTC Testing
+-----------
+
+The test cases mentioned in Renesas_RX65N_RTC_Test_Cases.xls are to be executed
+as part of RTC testing.
+
+The following configurations are to be enabled as part of testing RTC examples.
+
+* ``CONFIG_EXAMPLES_ALARM``
+* ``CONFIG_EXAMPLES_PERIODIC``
+* ``CONFIG_EXAMPLES_CARRY``
+
+USB Device Configurations
+--------------------------
+
+The following configurations need to be enabled for USB Device
+
+* ``CONFIG_USBDEV``
+* ``CONFIG_CDCACM``
+* ``CONFIG_STDIO_BUFFER_SIZE=64``
+* ``CONFIG_STDIO_LINEBUFFER``
+
+USB Device Testing
+------------------------
+
+The following testing is executed as part of USB Device testing on RX65N target
+for GRROSE board:
+
+.. code:: console
+
+   $ echo "This is a test for USB Device" > /dev/ttyACM0
+   $ xd 0 0x20000 > /dev/ttyACM0
+
+The output of the commands mentioned above should be seen on the USB Device COM
+port on teraterm
+
+RSPI Configurations
+-------------------
+
+The following configurations need to be enabled for RSPI
+
+* ``CONFIG_SYSTEM_SPITOOL=y``
+
+RSPI Testing
+------------
+
+The following testing is executed as part of RSPI testing on RX65N target for
+GRROSE board
+
+On GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only
+brought out.
+
+The following command can be used for testing RSPI communication to the slave
+device:
+
+.. code:: console
+
+   $ spi exch -b 0 -x 4 aabbccdd
+
+where b is bus number and x is number of words to exchange.
+
+RIIC Configurations
+-------------------
+
+The following configurations need to be enabled for RIIC
+
+* ``CONFIG_SYSTEM_I2CTOOL=y``
+
+RIIC Testing
+------------
+
+On GRROSE board, none of the RIIC channel pins are brought out in the board so
+not tested for communication.
+
+DTC Configurations
+------------------
+
+The following configurations need to be enabled for DTC.
+
+* ``CONFIG_SYSTEM_SPITOOL=y``
+
+DTC Testing
+-----------
+
+DTC has been tested using RSPI driver.
+
+USB Host Configurations
+-----------------------
+
+The following configurations need to be enabled for USB Host Mode driver to
+support USB HID Keyboard class and MSC Class.
+
+* ``CONFIG_USBHOST=y``
+* ``CONFIG_USBHOST_HIDKBD=y``
+* ``CONFIG_FS_FAT=y``
+* ``CONFIG_EXAMPLES_HIDKBD=y``
+
+USB Host Driver Testing
+------------------------
+
+The Following Class Drivers were tested as mentioned below:
+
+- USB HID Keyboard Class
+
+On the NuttX Console "hidkbd" application was executed
+
+.. code:: console
+
+   nsh> hidkbd
+
+The characters typed from the keyboard were executed correctly.
+
+- USB MSC Class
+
+The MSC device is enumerated as ``sda`` in ``/dev`` directory.
+
+The block device is mounted using the command as mentioned below:
+
+.. code:: console
+
+   $ mount -t vfat /dev/sda /mnt
+
+The MSC device is mounted in ``/dev`` directory
+
+The copy command is executed to test the Read/Write functionality
+
+.. code:: console
+
+   $ cp /mnt/<file.txt> /mnt/file_copy.txt
+
+USB Host Hub Configurations
+---------------------------
+
+The following configurations need to be enabled for USB Host Mode driver to
+support USB HID Keyboard class and MSC Class.
+
+* ``CONFIG_RX65N_USBHOST=y``
+* ``CONFIG_USBHOST_HUB=y``
+* ``CONFIG_USBHOST_ASYNCH=y``
+* ``CONFIG_USBHOST=y``
+* ``CONFIG_USBHOST_HIDKBD=y``
+* ``CONFIG_FS_FAT=y``
+* ``CONFIG_EXAMPLES_HIDKBD=y``
+
+USB Host Hub Driver Testing
+---------------------------
+
+The Following Class Drivers were tested as mentioned below :
+
+- USB HID Keyboard Class
+
+On the NuttX Console "hidkbd" application was executed
+
+.. code:: console
+
+   nsh> hidkbd
+
+The characters typed from the keyboard were executed correctly.
+
+- USB MSC Class
+
+The MSC device is enumerated as ``sda`` in ``/dev`` directory.
+
+The block device is mounted using the command as mentioned below:
+
+.. code:: console
+
+   $ mount -t vfat /dev/sda /mnt
+
+The MSC device is mounted in ``/dev`` directory
+
+The copy command is executed to test the Read/Write functionality
+
+.. code:: console
+
+   $ cp /mnt/<file.txt> /mnt/file_copy.txt
+
+Debugging
+=========
+
+1. NuttX needs to be compiled in Cygwin.
+
+The following Configuration needs to be set, in order to do source level
+debugging:
+
+``CONFIG_DEBUG_SYMBOLS=y`` (Set this option, using menuconfig only, DO NOT
+Enable this as default configuration).
+
+2. Download & Install Renesas e2studio IDE.
+3. Load the project(NuttX built on Cygwin) as Makefile project with existing code
+4. Right click on the project, and select Debug Configurations.
+5. The binary(NuttX) needs to be loaded using E1/E2 Emulator.
+6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used)
+7. Select Connection type as FINE.
+8. Load and run the binary.
+
+Flashing NuttX
+==============
+
+Alternatively, NuttX binary can be flashed using Renesas flash programmer tool
+without using e2 studio/Cygwin
+
+Below are the steps mentioned to flash NuttX binary using Renesas flash
+programmer tool(RFP).
+
+1. In order to flash using Renesas flash programmer tool, nuttx.mot file should
+   be generated.
+
+2. Add the following lines in tools/Unix.mk file:
+
+.. code:: makefile
+
+   ifeq ($(CONFIG_MOTOROLA_SREC),y)
+     @echo "CP: nuttx.mot"
+     $(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns nuttx.mot
+   endif
+
+3. Add ``CONFIG_MOTOROLA_SREC=y`` in defconfig file or choose ``make
+   menuconfig`` -> Build Setup -> Binary Output Format -> Select Motorola SREC
+   format.
+
+4. Download Renesas flash programmer tool from
+   https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
+
+5. Refer to the user manual document, for steps to flash NuttX binary using RFP
+   tool.
+
+ROMFS
+======
+
+Overview
+--------
+
+This directory contains logic to support a custom ROMFS system-init script and
+start-up script. These scripts are used by by the NSH when it starts provided
+that ``CONFIG_ETC_ROMFS=y``. These scripts provide a ROMFS volume that will be
+mounted at /etc and will look like this at run-time:
+
+.. code:: console
+
+   NuttShell (NSH) NuttX-8.2
+   nsh> ls -Rl /etc
+   /etc:
+    dr-xr-xr-x       0 .
+    -r--r--r--      20 group
+    dr-xr-xr-x       0 init.d/
+    -r--r--r--      35 passwd
+   /etc/init.d:
+    dr-xr-xr-x       0 ..
+    -r--r--r--     110 rcS
+    -r--r--r--     110 rc.sysinit
+   nsh>
+
+``/etc/init.d/rc.sysinit`` is system init script; ``/etc/init.d/rcS`` is the
+start-up script; ``/etc/passwd`` is a the password file. It supports a single
+user:
+
+.. code:: text
+
+   USERNAME:  admin
+   PASSWORD:  Administrator
+
+   nsh> cat /etc/passwd
+   admin:8Tv+Hbmr3pLVb5HHZgd26D:0:0:/
+
+The encrypted passwords in the provided passwd file are only valid if the TEA
+key is set to: 012345678 9abcdef0 012345678 9abcdef0. Changes to either the key
+or the password word will require regeneration of the ``nsh_romfimg.h`` header
+file.
+
+The format of the password file is:
+
+.. code:: text
+
+   user:x:uid:gid:home
+
+   Where:
+   user:  User name
+   x:     Encrypted password
+   uid:   User ID (0 for now)
+   gid:   Group ID (0 for now)
+   home:  Login directory (/ for now)
+
+``/etc/group`` is a group file. It is not currently used.
+
+.. code:: console
+
+   nsh> cat /etc/group
+   root:*:0:root,admin
+
+The format of the group file is:
+
+.. code:: text
+
+   group:x:gid:users
+
+   Where:
+   group:  The group name
+   x:      Group password
+   gid:    Group ID
+   users:  A comma separated list of members of the group
+
+``/etc/init.d/rcS`` should have the following contents:
+
+.. code:: text
+
+   vi rcS
+   echo "This is NuttX"
+
+Updating the ROMFS File System
+------------------------------
+
+The content on the ``nsh_romfsimg.h`` header file is generated from a sample
+directory structure. That directory structure is contained in the ``etc/``
+directory and can be modified per the following steps:
+
+1. Change directory to etc/:
+
+   .. code:: console
+
+      $ cd etc/
+
+2. Make modifications as desired.
+
+3. Create the new ROMFS image.
+
+   .. code:: console
+
+      $ genromfs -f romfs_img -d etc -V SimEtcVol
+
+4. Convert the ROMFS image to a C header file
+
+   .. code:: console
+
+      $ xxd -i romfs_img >nsh_romfsimg.h
+
+5. Edit ``nsh_romfsimg.h``, mark both data definitions as ``const`` so that that
+   will be stored in FLASH.

Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/README.txt

@@ -1,391 +0,0 @@
-README
-======
-
-This README file discusses the port of NuttX to the RX65N RSK2MB board. This board features the RX65N (R5F565NEHDFC 176pin)
-
-Contents
-========
-
-  - Board Features
-  - Status/Open Issues
-  - Serial Console
-  - LEDs
-  - Networking
-  - RTC
-  - USB Device
-  - RSPI
-  - RIIC
-  - DTC
-  - USB Host
-  - USB Host Hub
-  - Debugging
-
-Board Features
-==============
-- Mounted devices: RX65N (R5F565NEDDFC: No Encrypt Function, Code Flash 2MB, Pin Count 176-pin),
-  or RX65N (R5F565NEHDFC: Supported Encrypt Function, Code Flash 2MB, Pin Count 176-pin)
-- Mounts TFT Display. Graphic LCD controller can be evaluated
-- 1 channel Ethernet can be evaluated
-- RX65N builds in Trusted Secure IP. AES encryption function and robust key management can be evaluated (*)
-- Mounts SD slot. If an optional Wireless LAN expansion board package for RSK (RTK0ZZZZZZP00000BR#WS) is used,
-  Wireless LAN can evaluated
-- 1 channel USB Function and 1 channel USB Host can be evaluated
-- In addition, CAN, RSPI, QSPI, etc. can be evaluated
-
-See the RX65N RSK2MB website for further information about this board:
-
-  - https://www.renesas.com/br/en/products/software-tools/boards-and-kits/starter-kits/renesas-starter-kitplus-for-rx65n-2mb.html
-
-Serial Console
-==============
-RX65N RSK2MB supports 12 serial ports (SCI0 - SCI12), however only 1 port can be tested(SCI8, which is the serial console). Only SCI8 port can be tested which is connected to USB Serial port.
-
-Serial ports SCI1, SCI2, SCI9-SCI12, cannot be tested because they are multiplexed to other Rx65N controller interfaces.
-
-Following SCI ports are configured w.r.t RX65N pin configuration
-SCI1 Pin Configuration :
------------
-RX65N RSK2MB
-  Function
------------
-  PF2   RXD1
-  PF1   TXD1
-------------
-
-SCI2 Pin Configuration :
------------
-RX65N RSK2MB
-  Function
------------
-  P52   RXD2
-  P50   TXD2
-------------
-SCI8 Pin Configuration :
------------
-RX65N RSK2MB
-  Function
------------
-  PJ1   RXD8
-  PJ2   TXD8
-------------
-
-Serial Connection Configuration
--------------------------------
-1. RSK2MB board needs to be connected to PC, using USB cable(One end of which is connected to PC, other end
-connected to USB serial port on H/W board).
-2. RSK USB Serial Driver needs to be downloaded on PC side.
-3. Configure Teraterm to 115200 baud.
-
-LEDs
-====
-
-  The RX65N RSK2MB board has 2 Power LED's(PowerLED5 LED_G, PowerLED3 LED_G) and 4 user LED's (LED_G, LED_O, LED_R, LED_R).
-
-  If enabled 4 User LED's are simply turned on when the board boots
-  successfully, and is blinking on panic / assertion failed.
-
-Networking
-==========
-
-Ethernet Connections
---------------------
-
-  ------        ---------
-  RX65N
-  RSK2MB        Ethernet
-  Pin           Function
-  ------        ---------
-  PC4           ET0_TX_CLK
-  P76           ET0_RX_CLK
-  P80           ET0_TX_EN
-  PC6           ET0_ETXD3
-  PC5           ET0_ETXD2
-  P82           ET0_ETXD1
-  P81           ET0_ETXD0
-  PC3           ET0_TX_ER
-  PC2           ET0_RX_DV
-  PC0           ET0_ERXD3
-  PC1           ET0_ERXD2
-  P74           ET0_ERXD1
-  P75           ET0_ERXD0
-  P77           ET0_RX_ER
-  P83           ET0_CRS
-  PC7           ET0_COL
-  P72           ET0_MDC
-  P71           ET0_MDIO
-  P54           ET0_LINKSTA
-  ------         ---------
-
-USB Device
------------
-
-For the RX65N RSK2MB board, to be used as USB Device, the following Jumper settings need to be done
-
-J7     Short Pin 2 & Pin 3
-J16    Short Pin 1 & Pin 2
-
-NuttX Configurations
---------------------
-The following configurations, need to be enabled for network.
-
-CONFIG_RX65N_EMAC=y    : Enable the EMAC Peripheral for RX65N
-CONFIG_RX65N_EMAC0=y   : Enable the EMAC Peripheral for RX65N
-CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register
-CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18  : Needed for PHY CHIP
-CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08  : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14   : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04   : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : "    " " " "     "
-CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : "    " " " "     "
-CONFIG_RX65N_EMAC0_RMII=y
-CONFIG_RX65N_EMAC0_PHYADDR=0 :  PHY is at address 1
-
-CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed
-CONFIG_SCHED_HPWORK=y    :  High Priority Work queue support
-CONFIG_SCHED_LPWORK=y    :  Low Priority Work queue support
-
-Using the network with NSH
---------------------------
-The IP address is configured using DHCP, using the below mentioned configurations :
-
-CONFIG_NETUTILS_DHCPC=y
-CONFIG_NETUTILS_DHCPD=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NETINIT_DHCPC=y
-
-nsh> ifconfig
-  eth0    HWaddr 00:e0:de:ad:be:ef at UP
-          IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
-
-You can use ping to test for connectivity to the host (Careful,
-Window firewalls usually block ping-related ICMP traffic).  On the
-target side, you can:
-
-  nsh> ping 10.75.24.250
-  PING 10.75.24.250 56 bytes of data
-  56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
-  56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
-  10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
-
-On the host side, you should also be able to ping the RX65N-RSK2MB:
-
-  $ ping 10.75.24.53
-
-Configure UDP blaster application as mentioned below :
-
-CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801  (10.75.24.1) ------> Gateway IP
-CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
-CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
-
-RSPI
------------
-
-For RX65N RSK2MB board, Following pin is configured for all channels in JA3.
-Channel0: Pin number 7 and 8 in JA3 is used for MOSIA and MISOA respectively
-Channel1: Pin number 35 and 36 in JA3 is used for MOSIB and MISOB respectively
-Channel2: Pin number 18 and 19 in JA3 is used for MOSIC and MISOC respectively
-and for enabling these pin need to select DSW-SEL0 by making off SW4-4
-
-USB Host
-=============
-For the RX65N RSK2MB board, to be used as USB Device, the following Jumper settings need to be done
-
-J7     Short Pin 1 & Pin 2
-J16    Short Pin 2 & Pin 3
-
-USB Device
-=============
-For the RX65N RSK2MB board, to be used as USB Device, the following Jumper settings need to be done
-
-J7     Short Pin 2 & Pin 3
-J16    Short Pin 1 & Pin 2
-
-RTC
-==========
-
-NuttX Configurations
----------------
-The configurations listed in Renesas_RX65N_NuttX_RTC_Design.doc need to be enabled.
-
-RTC Testing
-------------------
-The test cases mentioned in Renesas_RX65N_RTC_Test_Cases.xls are to be executed
-as part of RTC testing.
-
-The following configurations are to be enabled as part of testing RTC examples.
-CONFIG_EXAMPLES_ALARM
-CONFIG_EXAMPLES_PERIODIC
-CONFIG_EXAMPLES_CARRY
-
-USB Device Configurations
---------------------------
-The following configurations need to be enabled for USB Device
-
-CONFIG_USBDEV
-CONFIG_CDCACM
-CONFIG_STDIO_BUFFER_SIZE=64
-CONFIG_STDIO_LINEBUFFER
-
-USB Device Testing
-------------------------
-The following testing is executed as part of USB Device testing on RX65N target for GRROSE board
-
-echo "This is a test for USB Device" > /dev/ttyACM0
-
-xd 0 0x20000 > /dev/ttyACM0
-
-The output of the commands mentioned above should be seen on the USB Device COM port on teraterm
-
-RSPI Configurations
---------------------------
-The following configurations need to be enabled for RSPI
-
-CONFIG_SYSTEM_SPITOOL=y
-
-RSPI Testing
-------------------------
-The following testing is executed as part of RSPI testing on RX65N target for RSK2MB board
-
-On RSK2MB board, all three channels 0, 1 and 2 has been brought out and tested.
-
-Following command can be used for testing RSPI communication to slave device.
-spi exch -b 0 -x 4 aabbccdd
-where b is bus number and x is Number of word to exchange.
-
-RIIC Configurations
---------------------------
-The following configurations need to be enabled for RIIC.
-
-CONFIG_SYSTEM_I2CTOOL=y
-
-RIIC Testing
-------------------------
-The following testing is executed as part of RIIC testing on RX65N target for RSK2MB board
-
-On RSK2MB board only channel 0 can be tested.
-
-Following command can be used for testing RIIC communication with slave device.
-i2c set -b 0 -a 53 -r 0 10
-where b is bus number, a is the slave address, r is the register address and 10 is the value to be written.
-
-DTC Configurations
---------------------------
-The following configurations need to be enabled for DTC.
-
-CONFIG_SYSTEM_SPITOOL=y
-
-DTC Testing
-------------------------
-
-DTC has been tested using RSPI driver.
-
-USB Host Configurations
---------------------------
-The following configurations need to be enabled for USB Host Mode driver to
-support USB HID Keyboard class and MSC Class.
-
-CONFIG_USBHOST=y
-CONFIG_USBHOST_HIDKBD=y
-CONFIG_FS_FAT=y
-CONFIG_EXAMPLES_HIDKBD=y
-
-USB Host Driver Testing
-------------------------
-The Following Class Drivers were tested as mentioned below :
-
-- USB HID Keyboard Class
-On the NuttX Console "hidkbd" application was executed
-
-nsh> hidkbd
-The characters typed from the keyboard were executed correctly.
-
-- USB MSC Class
-
-The MSC device is enumerated as sda in /dev directory.
-
-The block device is mounted using the command as mentioned below :
-
-mount -t vfat /dev/sda /mnt
-
-The MSC device is mounted in /dev directory
-
-The copy command is executed to test the Read/Write functionality
-
-cp /mnt/<file.txt> /mnt/file_copy.txt
-
-USB Host Hub Configurations
---------------------------
-The following configurations need to be enabled for USB Host Mode driver to
-support USB HID Keyboard class and MSC Class.
-
-CONFIG_RX65N_USBHOST=y
-CONFIG_USBHOST_HUB=y
-CONFIG_USBHOST_ASYNCH=y
-CONFIG_USBHOST=y
-CONFIG_USBHOST_HIDKBD=y
-CONFIG_FS_FAT=y
-CONFIG_EXAMPLES_HIDKBD=y
-
-USB Host Hub Driver Testing
-------------------------
-The Following Class Drivers were tested as mentioned below :
-
-- USB HID Keyboard Class
-On the NuttX Console "hidkbd" application was executed
-
-nsh> hidkbd
-The characters typed from the keyboard were executed correctly.
-
-- USB MSC Class
-The MSC device is enumerated as sda in /dev directory.
-
-The block device is mounted using the command as mentioned below :
-
-mount -t vfat /dev/sda /mnt
-
-The MSC device is mounted in /dev directory
-
-The copy command is executed to test the Read/Write functionality
-
-cp /mnt/<file.txt> /mnt/file_copy.txt
-
-Debugging
-==========
-1. NuttX needs to be compiled in Cygwin environment on Windows.
-
-The following Configuration needs to be set, in order to do source level debugging.
-
-CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration).
-
-2. Download & Install Renesas e2studio IDE
-3. Load the project(NuttX built on Cygwin) as Makefile project with existing code
-4. Right click on the project, and select Debug Configurations
-5. The binary(NuttX) needs to be loaded using E1/E2 Emulator
-6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used)
-7. Select Connection type as JTAG
-8. Load and run the binary
-
-Flashing NuttX
-===============
-Alternatively, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin
-
-Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP).
-
-1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated.
-2. Add the following lines in tools/Unix.mk file :
-ifeq ($(CONFIG_MOTOROLA_SREC),y)
-	@echo "CP: nuttx.mot"
-	$(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns nuttx.mot
-endif
-3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format->
-   Select Motorola SREC format.
-4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
-5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool.

Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/ROMFS.txt

@@ -1,85 +0,0 @@
-README
-======
-
-  Overview
-  --------
-  This directory contains logic to support a custom ROMFS system-init script
-  and start-up script.  These scripts are used by by the NSH when it starts
-  provided that CONFIG_ETC_ROMFS=y.  These scripts provide a ROMFS volume
-  that will be mounted at /etc and will look like this at run-time:
-
-    NuttShell (NSH) NuttX-8.2
-    nsh> ls -l /etc
-    /etc:
-     dr-xr-xr-x       0 .
-     -r--r--r--      20 group
-     dr-xr-xr-x       0 init.d/
-     -r--r--r--      35 passwd
-    /etc/init.d:
-     dr-xr-xr-x       0 ..
-     -r--r--r--     110 rcS
-     -r--r--r--     110 rc.sysinit
-    nsh>
-
-  /etc/init.d/rc.sysinit is system init script; /etc/init.d/rcS is the start-up
-  script; /etc/passwd is a the password file.  It supports a single user:
-
-    USERNAME:  admin
-    PASSWORD:  Administrator
-
-    nsh> cat /etc/passwd
-    admin:8Tv+Hbmr3pLVb5HHZgd26D:0:0:/
-
-  The encrypted passwords in the provided passwd file are only valid if the
-  TEA key is set to:  012345678 9abcdef0 012345678 9abcdef0.  Changes to either
-  the key or the password word will require regeneration of the nsh_romfimg.h
-  header file.
-
-  The format of the password file is:
-
-    user:x:uid:gid:home
-
-  Where:
-    user:  User name
-    x:     Encrypted password
-    uid:   User ID (0 for now)
-    gid:   Group ID (0 for now)
-    home:  Login directory (/ for now)
-
-  /etc/group is a group file.  It is not currently used.
-
-    nsh> cat /etc/group
-    root:*:0:root,admin
-
-  The format of the group file is:
-
-    group:x:gid:users
-
-  Where:
-    group:  The group name
-    x:      Group password
-    gid:    Group ID
-    users:  A comma separated list of members of the group
-
-  Updating the ROMFS File System
-  ------------------------------
-  The content on the nsh_romfsimg.h header file is generated from a sample
-  directory structure.  That directory structure is contained in the etc/ directory and can be modified per the following steps:
-
-    1. Change directory to etc/:
-
-       cd etc/
-
-    2. Make modifications as desired.
-
-    3. Create the new ROMFS image.
-
-       genromfs -f romfs_img -d etc -V SimEtcVol
-
-    4. Convert the ROMFS image to a C header file
-
-        xxd -i romfs_img >nsh_romfsimg.h
-
-    5. Edit nsh_romfsimg.h, mark both data definitions as 'const' so that
-       that will be stored in FLASH.
-

Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/index.rst

@@ -2,8 +2,475 @@
 RX65N RSK2MB
 ============
 
-.. include:: README.txt
+.. tags:: arch:renesas
-   :literal:
 
-.. include:: ROMFS.txt
+This README file discusses the port of NuttX to the RX65N RSK2MB board. This board features the RX65N (R5F565NEHDFC
-   :literal:
+176 pin)
+
+Board Features
+==============
+
+- Mounted devices: RX65N (R5F565NEDDFC: No Encrypt Function, Code Flash 2MB, Pin
+  Count 176-pin), or RX65N (R5F565NEHDFC: Supported Encrypt Function, Code Flash
+  2MB, Pin Count 176-pin)
+- Mounts TFT Display. Graphic LCD controller can be evaluated
+- 1 channel Ethernet can be evaluated
+- RX65N builds in Trusted Secure IP. AES encryption function and robust key
+  management can be evaluated (*)
+- Mounts SD slot. If an optional Wireless LAN expansion board package for RSK
+  (RTK0ZZZZZZP00000BR#WS) is used, Wireless
+  LAN can evaluated
+- 1 channel USB Function and 1 channel USB Host can be evaluated
+- In addition, CAN, RSPI, QSPI, etc. can be evaluated
+
+See the RX65N RSK2MB website for further information about this board:
+https://www.renesas.com/br/en/products/software-tools/boards-and-kits/starter-kits/renesas-starter-kitplus-for-rx65n-2mb.html
+
+Serial Console
+==============
+
+RX65N RSK2MB supports 12 serial ports (SCI0 - SCI12), however only 1 port can be
+tested (SCI8, which is the serial console). Only SCI8 port can be tested which
+is connected to USB Serial port.
+
+Serial ports SCI1, SCI2, SCI9-SCI12, cannot be tested because they are
+multiplexed to other Rx65N controller interfaces.
+
+Following SCI ports are configured w.r.t RX65N pin configuration
+
+SCI1 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+PF2 RXD1
+PF1 TXD1
+=== ========
+
+SCI2 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+P52 RXD2
+P50 TXD2
+=== ========
+
+SCI8 Pin Configuration:
+
+=== ========
+Pin Function
+=== ========
+PJ1 RXD8
+PJ2 TXD8
+=== ========
+
+Serial Connection Configuration
+-------------------------------
+
+1. RSK2MB board needs to be connected to PC, using USB cable (One end of which is
+   connected to PC, other end connected to USB serial port on H/W board).
+
+2. RSK USB Serial Driver needs to be downloaded on PC side.
+
+3. Configure Teraterm to 115200 baud.
+
+LEDs
+====
+
+The RX65N RSK2MB board has 2 Power LEDs:
+
+* PowerLED5 LED_G
+* PowerLED3 LED_G
+
+and 4 user LEDs:
+
+* LED_G
+* LED_O
+* LED_R
+* LED_R
+
+If enabled 4 User LED's are simply turned on when the board boots successfully,
+and is blinking on panic / assertion failed.
+
+Networking
+==========
+
+Ethernet Connections
+--------------------
+
+=== ===========
+Pin Function
+=== ===========
+PC4 ET0_TX_CLK
+P76 ET0_RX_CLK
+P80 ET0_TX_EN
+PC6 ET0_ETXD3
+PC5 ET0_ETXD2
+P82 ET0_ETXD1
+P81 ET0_ETXD0
+PC3 ET0_TX_ER
+PC2 ET0_RX_DV
+PC0 ET0_ERXD3
+PC1 ET0_ERXD2
+P74 ET0_ERXD1
+P75 ET0_ERXD0
+P77 ET0_RX_ER
+P83 ET0_CRS
+PC7 ET0_COL
+P72 ET0_MDC
+P71 ET0_MDIO
+P54 ET0_LINKSTA
+=== ===========
+
+USB Device
+-----------
+
+For the RX65N RSK2MB board, to be used as USB Device, the following jumper
+settings need to be done:
+
+* J7: Short Pin 2 & Pin 3
+* J16: Short Pin 1 & Pin 2
+
+NuttX Configuration Options
+---------------------------
+
+The following configurations, need to be enabled for network.
+
+* ``CONFIG_RX65N_EMAC=y``: Enable the EMAC Peripheral for RX65N
+* ``CONFIG_RX65N_EMAC0=y``: Enable the EMAC Peripheral for RX65N
+* ``CONFIG_RX65N_EMAC0_PHYSR=30``: Address of PHY status register
+* ``CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18``: Needed for PHY CHIP
+* ``CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08``
+* ``CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14``
+* ``CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04``
+* ``CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y``
+* ``CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c``
+* ``CONFIG_RX65N_EMAC0_RMII=y``
+* ``CONFIG_RX65N_EMAC0_PHYADDR=0``:  PHY is at address 1
+* ``CONFIG_SCHED_WORKQUEUE=y``: Work queue support is needed
+* ``CONFIG_SCHED_HPWORK=y``:  High Priority Work queue support
+* ``CONFIG_SCHED_LPWORK=y``:  Low Priority Work queue support
+
+Using the network with NSH
+--------------------------
+
+The IP address is configured using DHCP, using the below mentioned
+configurations:
+
+* ``CONFIG_NETUTILS_DHCPC=y``
+* ``CONFIG_NETUTILS_DHCPD=y``
+* ``CONFIG_NSH_DHCPC=y``
+* ``CONFIG_NETINIT_DHCPC=y``
+
+.. code:: console
+
+   nsh> ifconfig
+     eth0    HWaddr 00:e0:de:ad:be:ef at UP
+             IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0
+
+You can use ping to test for connectivity to the host (Careful, Window firewalls
+usually block ping-related ICMP traffic). On the target side, you can:
+
+.. code:: console
+
+   nsh> ping 10.75.24.250
+   PING 10.75.24.250 56 bytes of data
+   56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms
+   56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms
+   10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
+
+On the host side, you should also be able to ping the RX65N-RSK2MB:
+
+.. code:: console
+
+   $ ping 10.75.24.53
+
+Configure UDP blaster application as mentioned below:
+
+* ``CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801``  (10.75.24.1) ------> Gateway IP
+* ``CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00`` (255.255.254.0) --------> Netmask
+* ``CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b`` (10.75.24.155) ---------> Target IP
+
+RSPI
+----
+
+For RX65N RSK2MB board, the following pins are configured for all channels in JA3.
+
+* Channel0: Pin number 7 and 8 in JA3 is used for MOSIA and MISOA respectively
+* Channel1: Pin number 35 and 36 in JA3 is used for MOSIB and MISOB respectively
+* Channel2: Pin number 18 and 19 in JA3 is used for MOSIC and MISOC respectively
+
+and for enabling these pins, you need to select DSW-SEL0 by turning off SW4-4.
+
+USB Host Jumpers
+================
+
+For the RX65N RSK2MB board, to be used as USB Device, the following jumper
+settings need to be done:
+
+* J7: Short Pin 1 & Pin 2
+* J16: Short Pin 2 & Pin 3
+
+USB Device Jumpers
+==================
+
+For the RX65N RSK2MB board, to be used as USB Device, the following jumper
+settings need to be done:
+
+* J7: Short Pin 2 & Pin 3
+* J16: Short Pin 1 & Pin 2
+
+RTC
+===
+
+NuttX Configurations
+--------------------
+
+The configurations listed in Renesas_RX65N_NuttX_RTC_Design.doc need to be enabled.
+
+RTC Testing
+-----------
+
+The test cases mentioned in Renesas_RX65N_RTC_Test_Cases.xls are to be executed as part of RTC testing.
+
+The following configurations are to be enabled as part of testing RTC examples.
+
+* ``CONFIG_EXAMPLES_ALARM``
+* ``CONFIG_EXAMPLES_PERIODIC``
+* ``CONFIG_EXAMPLES_CARRY``
+
+USB Device Configurations
+-------------------------
+
+The following configurations need to be enabled for USB Device
+
+* ``CONFIG_USBDEV``
+* ``CONFIG_CDCACM``
+* ``CONFIG_STDIO_BUFFER_SIZE=64``
+* ``CONFIG_STDIO_LINEBUFFER``
+
+USB Device Testing
+------------------
+
+The following testing is executed as part of USB Device testing on RX65N target for GRROSE board
+
+.. code:: console
+
+   $ echo "This is a test for USB Device" > /dev/ttyACM0
+   $ xd 0 0x20000 > /dev/ttyACM0
+
+The output of the commands mentioned above should be seen on the USB Device COM port on teraterm
+
+RSPI Configurations
+-------------------
+
+The following configurations need to be enabled for RSPI
+
+* ``CONFIG_SYSTEM_SPITOOL=y``
+
+RSPI Testing
+------------
+
+The following testing is executed as part of RSPI testing on RX65N target for RSK2MB board
+
+On RSK2MB board, all three channels 0, 1 and 2 has been brought out and tested.
+
+Following command can be used for testing RSPI communication to slave device.
+
+.. code:: console
+
+   $ spi exch -b 0 -x 4 aabbccdd
+
+where b is bus number and x is number of words to exchange.
+
+RIIC Configurations
+-------------------
+
+The following configurations need to be enabled for RIIC.
+
+* ``CONFIG_SYSTEM_I2CTOOL=y``
+
+RIIC Testing
+------------
+
+The following testing is executed as part of RIIC testing on RX65N target for RSK2MB board
+
+On RSK2MB board only channel 0 can be tested.
+
+Following command can be used for testing RIIC communication with slave device.
+
+.. code:: console
+
+   $ i2c set -b 0 -a 53 -r 0 10
+
+where b is bus number, a is the slave address, r is the register address and 10 is the value to be written.
+
+DTC Configurations
+------------------
+
+The following configurations need to be enabled for DTC.
+
+* ``CONFIG_SYSTEM_SPITOOL=y``
+
+DTC Testing
+-----------
+
+DTC has been tested using RSPI driver.
+
+USB Host Configurations
+-----------------------
+
+The following configurations need to be enabled for USB Host Mode driver to
+support USB HID Keyboard class and MSC Class.
+
+* ``CONFIG_USBHOST=y``
+* ``CONFIG_USBHOST_HIDKBD=y``
+* ``CONFIG_FS_FAT=y``
+* ``CONFIG_EXAMPLES_HIDKBD=y``
+
+USB Host Driver Testing
+------------------------
+
+The Following Class Drivers were tested as mentioned below :
+
+- USB HID Keyboard Class
+
+On the NuttX Console "hidkbd" application was executed
+
+.. code:: console
+
+   nsh> hidkbd
+
+The characters typed from the keyboard were executed correctly.
+
+- USB MSC Class
+
+The MSC device is enumerated as ``sda`` in ``/dev`` directory.
+
+The block device is mounted using the command as mentioned below:
+
+.. code:: console
+
+   $ mount -t vfat /dev/sda /mnt
+
+The MSC device is mounted in ``/dev`` directory
+
+The copy command is executed to test the Read/Write functionality
+
+.. code:: console
+
+   $ cp /mnt/<file.txt> /mnt/file_copy.txt
+
+USB Host Hub Configurations
+---------------------------
+
+The following configurations need to be enabled for USB Host Mode driver to support USB HID Keyboard class and MSC
+Class.
+
+* ``CONFIG_RX65N_USBHOST=y``
+* ``CONFIG_USBHOST_HUB=y``
+* ``CONFIG_USBHOST_ASYNCH=y``
+* ``CONFIG_USBHOST=y``
+* ``CONFIG_USBHOST_HIDKBD=y``
+* ``CONFIG_FS_FAT=y``
+* ``CONFIG_EXAMPLES_HIDKBD=y``
+
+USB Host Hub Driver Testing
+---------------------------
+
+The Following Class Drivers were tested as mentioned below :
+
+- USB HID Keyboard Class
+
+On the NuttX Console "hidkbd" application was executed
+
+.. code:: console
+
+   nsh> hidkbd
+
+The characters typed from the keyboard were executed correctly.
+
+- USB MSC Class
+
+The MSC device is enumerated as ``sda`` in ``/dev`` directory.
+
+The block device is mounted using the command as mentioned below:
+
+.. code:: console
+
+   $ mount -t vfat /dev/sda /mnt
+
+The MSC device is mounted in ``/dev`` directory
+
+The copy command is executed to test the Read/Write functionality
+
+.. code:: console
+
+   $ cp /mnt/<file.txt> /mnt/file_copy.txt
+
+Debugging
+=========
+
+1. NuttX needs to be compiled in Cygwin environment on Windows.
+
+The following Configuration needs to be set, in order to do source level
+debugging.
+
+``CONFIG_DEBUG_SYMBOLS=y`` (Set this option, using menuconfig only, DO NOT
+Enable this as default configuration).
+
+2. Download & Install Renesas e2studio IDE
+3. Load the project (NuttX built on Cygwin) as Makefile project with existing
+   code
+4. Right click on the project, and select Debug Configurations
+5. The binary (NuttX) needs to be loaded using E1/E2 Emulator
+6. Select the Device name as R5F565NE and Emulator as E1/E2 (whichever is being
+   used)
+7. Select Connection type as JTAG
+8. Load and run the binary
+
+Flashing NuttX
+==============
+
+Alternatively, NuttX binary can be flashed using Renesas flash programmer tool
+without using e2 studio/Cygwin
+
+Below are the steps mentioned to flash NuttX binary using Renesas flash
+programmer tool (RFP).
+
+1. In order to flash using Renesas flash programmer tool, nuttx.mot file should
+   be generated.
+
+2. Add the following lines in ``tools/Unix.mk`` file:
+
+.. code:: makefile
+
+   ifeq ($(CONFIG_MOTOROLA_SREC),y)
+   	 @echo "CP: nuttx.mot"
+   	 $(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns nuttx.mot
+   endif
+
+3. Add ``CONFIG_MOTOROLA_SREC=y`` in defconfig file or choose ``make
+   menuconfig`` -> Build Setup-> Binary Output Format-> Select Motorola SREC
+   format.
+
+4. Download Renesas flash programmer tool from
+   https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads
+
+5. Refer to the user manual document, for steps to flash NuttX binary using RFP
+   tool.
+
+ROMFS
+=====
+
+See the "ROMFS" section of
+:doc:`/platforms/renesas/rx65n/boards/rx65n-grrose/index` for more information.

Documentation/platforms/renesas/sh1/boards/us7032evb1/README.txt

@@ -1,151 +0,0 @@
-Status
-^^^^^^
-
-*** UNSTABLE ***
-The port is basically complete and many examples run correctly.  However, there
-are remaining instabilities that make the port un-usable.  The nature of these
-is not understood; the behavior is that certain SH-1 instructions stop working
-as advertised.  This could be a silicon problem, some pipeline issue that is not
-handled properly by the gcc 3.4.5 toolchain (which has very limited SH-1 support
-to begin with), or perhaps with the CMON debugger.  At any rate, I have exhausted
-all of the energy that I am willing to put into this cool old processor for the
-time being.
-
-Toolchain
-^^^^^^^^^
-
-  A GNU GCC-based toolchain is assumed.  The PATH environment variable should
-  be modified to point to the correct path to the SH toolchain (if
-  different from the default).
-
-  If you have no SH toolchain, one can be downloaded from the NuttX
-  Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/).
-
-  1. You must have already configured NuttX in <some-dir>nuttx.
-
-     tools/configure.sh us7032evb1:<sub-dir>
-
-  2. Download the latest buildroot package into <some-dir>
-
-  3. unpack
-
-  4. cd <some-dir>/buildroot
-
-  5. cp boards/sh-defconfig .config
-
-  6. make oldconfig
-
-  7. make
-
-  8. Make sure that the PATH variable includes the path to the newly built
-     binaries.
-
-shterm
-^^^^^^
-
-  The USB7032EVB1 supports CMON in PROM.  CMON requires special
-  serial interactions in order to upload and download program files.
-  Therefore, a standard terminal emulation program (such as minicom)
-  cannot be used.
-
-  The shterm subdirectory contains a small terminal emulation
-  program that supports these special interactions for file transfers.
-
-Configurations
-^^^^^^^^^^^^^^
-
-Common Configuration Notes
---------------------------
-
-  1. Each SH-1 configuration is maintained in a sub-directory and
-     can be selected as follow:
-
-       tools/configure.sh us7032evb1:<subdir>
-
-     Where <subdir> is one of the configuration sub-directories described in
-     the following paragraph.
-
-  2. These configurations use the mconf-based configuration tool.  To
-     change a configurations using that tool, you should:
-
-     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
-        see additional README.txt files in the NuttX tools repository.
-
-     b. Execute 'make menuconfig' in nuttx/ in order to start the
-        reconfiguration process.
-
-  3. By default, all configurations assume that you are building under
-     Linux (should work under Windows with Cygwin as well).  This is
-     is easily reconfigured:
-
-        CONFIG_HOST_LINUX=y
-
-Configuration Sub-Directories
------------------------------
-
-  ostest
-
-    This configuration directory, performs a simple OS test using
-    examples/ostest.
-
-  nsh
-
-    Configures the NuttShell (nsh) located at examples/nsh.  The
-    Configuration enables only the serial NSH interfaces.
-
-    NOTE:  At present, the NSH example does not run.  See the "Status"
-    discussion above for a full explanation.
-
-Configuration Options
-^^^^^^^^^^^^^^^^^^^^^
-
-In additional to the common configuration options listed in the
-file boards/README.txt, there are other configuration options
-specific to the SH-1
-
-Architecture selection
-
-  CONFIG_ARCH - identifies the arch subdirectory and, hence, the
-    processor architecture.  This should be renesas (for arch/renesas)
-  CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory.
-    This should be sh1 (for arch/renesas/src/sh1 and arch/renesas/include/sh1)
-  CONFIG_ARCH_SH1 and CONFIG_ARCH_CHIP_SH7032 - for use in C code.  These
-    identify the particular chip or SoC that the architecture is
-    implemented in.
-  CONFIG_ARCH_BOARD - identifies the boards/ subdirectory and, hence,
-    the board that supports the particular chip or SoC.  This
-    should be us7032evb1 for (boards/renesas/sh1/us7032evb1).
-  CONFIG_ARCH_BOARD_US7032EVB1 - for use in C code
-  CONFIG_ENDIAN_BIG - the SH-1 usually runs big-endian
-  CONFIG_ARCH_NOINTC - define if the architecture does not
-    support an interrupt controller or otherwise cannot support
-    APIs like up_enable_irq() and up_disable_irq().  Should be
-    defined.
-  CONFIG_BOARD_LOOPSPERMSEC - for delay loops
-  CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to SH1_LCEVB1
-  CONFIG_RAM_SIZE - Describes the internal DRAM.
-  CONFIG_RAM_START - The start address of internal DRAM
-  CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
-    stack. If defined, this symbol is the size of the interrupt
-    stack in bytes.  If not defined, the user task stacks will be
-    used during interrupt handling.
-  CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
-
-  CONFIG_SH1_DMAC0, CONFIG_SH1_DMAC1, CONFIG_SH1_DMAC2, CONFIG_SH1_DMAC3,
-  CONFIG_SH1_ITU1, CONFIG_SH1_ITU2, CONFIG_SH1_ITU3, CONFIG_SH1_ITU4,
-  CONFIG_SH1_SCI0, CONFIG_SH1_SCI1, CONFIG_SH1_PCU, CONFIG_SH1_AD,
-  CONFIG_SH1_WDT, CONFIG_SH1_CMI - Each unused chip block should b
-    disabled to save space
-
-SH1 specific device driver settings
-
-  CONFIG_SCIn_SERIAL_CONSOLE - selects the SCIn for the
-    console and ttys0 (default is the UART0).
-  CONFIG_SCIn_RXBUFSIZE - Characters are buffered as received.
-    This specific the size of the receive buffer
-  CONFIG_SCIn_TXBUFSIZE - Characters are buffered before
-    being sent.  This specific the size of the transmit buffer
-  CONFIG_SCIn_BAUD - The configure BAUD of the UART.  Must be
-  CONFIG_SCIn_BITS - The number of bits.  Must be either 7 or 8.
-  CONFIG_SCIn_PARTIY - 0=no parity, 1=odd parity, 2=even parity, 3=mark 1, 4=space 0
-  CONFIG_SCIn_2STOP - Two stop bits

Documentation/platforms/renesas/sh1/boards/us7032evb1/index.rst

@@ -2,5 +2,119 @@
 US7032EVB1
 ==========
 
-.. include:: README.txt
+.. tags:: arch:renesas, experimental
-   :literal:
+
+.. warning::
+
+   The port is basically complete and many examples run correctly. However,
+   there are remaining instabilities that make the port un-usable. The nature
+   of these is not understood; the behavior is that certain SH-1 instructions
+   stop working as advertised. This could be a silicon problem, some pipeline
+   issue that is not handled properly by the gcc 3.4.5 toolchain (which has very
+   limited SH-1 support to begin with), or perhaps with the CMON debugger. At
+   any rate, I have exhausted all of the energy that I am willing to put into
+   this cool old processor for the time being.
+
+Toolchain
+=========
+
+A GNU GCC-based toolchain is assumed. The PATH environment variable should be
+modified to point to the correct path to the SH toolchain (if different from the
+default).
+
+If you have no SH toolchain, one can be downloaded from the NuttX Bitbucket
+download site (https://bitbucket.org/nuttx/buildroot/downloads/).
+
+1. You must have already configured NuttX in <some-dir>nuttx.
+
+.. code:: console
+
+   $ tools/configure.sh us7032evb1:<sub-dir>
+
+2. Download the latest buildroot package into <some-dir>
+
+3. unpack
+
+4.
+   .. code:: console
+
+      $ cd <some-dir>/buildroot
+      $ cp boards/sh-defconfig .config
+      $ make oldconfig
+      $ make
+
+5. Make sure that the PATH variable includes the path to the newly built
+   binaries.
+
+shterm
+======
+
+The USB7032EVB1 supports CMON in PROM. CMON requires special serial
+interactions in order to upload and download program files. Therefore, a
+standard terminal emulation program (such as minicom) cannot be used.
+
+The shterm subdirectory contains a small terminal emulation program that
+supports these special interactions for file transfers.
+
+Configurations
+==============
+
+Each SH-1 configuration is maintained in a sub-directory and can be selected as
+follows:
+
+.. code:: console
+
+   $ tools/configure.sh us7032evb1:<subdir>
+
+Where <subdir> is one of the configuration sub-directories described in
+the following paragraph.
+
+ostest
+------
+
+This configuration directory performs a simple OS test using examples/ostest in
+the nuttx-apps repository.
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at examples/nsh. The Configuration
+enables only the serial NSH interfaces.
+
+.. note::
+
+   At present, the NSH example does not run.
+
+Configuration Options
+=====================
+
+Each unused chip block should be disabled to save space:
+
+* ``CONFIG_SH1_DMAC0``
+* ``CONFIG_SH1_DMAC1``
+* ``CONFIG_SH1_DMAC2``
+* ``CONFIG_SH1_DMAC3``
+* ``CONFIG_SH1_ITU1``
+* ``CONFIG_SH1_ITU2``
+* ``CONFIG_SH1_ITU3``
+* ``CONFIG_SH1_ITU4``
+* ``CONFIG_SH1_SCI0``
+* ``CONFIG_SH1_SCI1``
+* ``CONFIG_SH1_PCU``
+* ``CONFIG_SH1_AD``
+* ``CONFIG_SH1_WDT``
+* ``CONFIG_SH1_CMI``
+
+SH1 specific device driver settings:
+
+* ``CONFIG_SCIn_SERIAL_CONSOLE``: Selects the SCIn for the console and ttys0
+  (default is the UART0).
+* ``CONFIG_SCIn_RXBUFSIZE``: Characters are buffered as received. This specific
+  the size of the receive buffer
+* ``CONFIG_SCIn_TXBUFSIZE``: Characters are buffered before being sent.  This
+  specific the size of the transmit buffer
+* ``CONFIG_SCIn_BAUD``: The configure BAUD of the UART.  Must be
+* ``CONFIG_SCIn_BITS``: The number of bits.  Must be either 7 or 8.
+* ``CONFIG_SCIn_PARTIY``: 0=no parity, 1=odd parity, 2=even parity, 3=mark 1,
+  4=space 0
+* ``CONFIG_SCIn_2STOP``: Two stop bits

Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst

@@ -153,6 +153,21 @@ You can check that the sensor is working by using the ``bmp180`` application::
     Pressure value = 91526
     Pressure value = 91525
 
+buttons
+-------
+
+This configuration shows the use of the buttons subsystem. It can be used by executing
+the ``buttons`` application and pressing the ``BOOT`` button on the board::
+
+    nsh> buttons
+    buttons_main: Starting the button_daemon
+    buttons_main: button_daemon started
+    button_daemon: Running
+    button_daemon: Opening /dev/buttons
+    button_daemon: Supported BUTTONs 0x01
+    nsh> Sample = 1
+    Sample = 0
+
 coremark
 --------
 
@@ -399,6 +414,59 @@ This same configuration enables the usage of the RMT peripheral and the example
 Please note that this board contains an on-board WS2812 LED connected to GPIO8
 and, by default, this config configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/risc-v/esp32c3/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/risc-v/esp32c3/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 

Documentation/platforms/risc-v/esp32c3/index.rst

@@ -600,6 +600,115 @@ to ``Application image secondary slot``.
    **After disabling UART Download Mode you will not be able to flash other images through UART.**
 
 
+Flash Allocation for MCUBoot
+----------------------------
+
+When MCUBoot is enabled on ESP32-C3, the flash memory is organized as follows
+based on the default KConfig values:
+
+**Flash Layout (MCUBoot Enabled)**
+
+.. list-table::
+   :header-rows: 1
+   :widths: 40 20 20
+   :align: left
+
+   * - Region
+     - Offset
+     - Size
+   * - Bootloader
+     - 0x000000
+     - 64KB
+   * - E-Fuse Virtual (see Note)
+     - 0x010000
+     - 64KB
+   * - Primary Application Slot (/dev/ota0)
+     - 0x020000
+     - 1MB
+   * - Secondary Application Slot (/dev/ota1)
+     - 0x120000
+     - 1MB
+   * - Scratch Partition (/dev/otascratch)
+     - 0x220000
+     - 256KB
+   * - Storage MTD (optional)
+     - 0x260000
+     - 1MB
+   * - Available Flash
+     - 0x360000+
+     - Remaining
+
+.. raw:: html
+
+   <div style="clear: both"></div>
+
+
+**Note**: The E-Fuse Virtual region is optional and only used when
+``ESPRESSIF_EFUSE_VIRTUAL_KEEP_IN_FLASH`` is enabled. However, this 64KB
+location is always allocated in the memory layout to prevent accidental
+erasure during board flashing operations, ensuring data preservation if
+virtual E-Fuses are later enabled.
+
+.. code-block:: text
+
+    Memory Map (Addresses in hex):
+
+    0x000000  ┌─────────────────────────────┐
+              │                             │
+              │      MCUBoot Bootloader     │
+              │           (64KB)            │
+              │                             │
+    0x010000  ├─────────────────────────────┤
+              │       E-Fuse Virtual        │
+              │           (64KB)            │
+    0x020000  ├─────────────────────────────┤
+              │                             │
+              │      Primary App Slot       │
+              │            (1MB)            │
+              │          /dev/ota0          │
+              │                             │
+    0x120000  ├─────────────────────────────┤
+              │                             │
+              │     Secondary App Slot      │
+              │            (1MB)            │
+              │          /dev/ota1          │
+              │                             │
+    0x220000  ├─────────────────────────────┤
+              │                             │
+              │      Scratch Partition      │
+              │           (256KB)           │
+              │       /dev/otascratch       │
+              │                             │
+    0x260000  ├─────────────────────────────┤
+              │                             │
+              │   Storage MTD (optional)    │
+              │            (1MB)            │
+              │                             │
+    0x360000  ├─────────────────────────────┤
+              │                             │
+              │       Available Flash       │
+              │         (Remaining)         │
+              │                             │
+              └─────────────────────────────┘
+
+The key KConfig options that control this layout:
+
+- ``ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET`` (default: 0x20000)
+- ``ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET`` (default: 0x120000)
+- ``ESPRESSIF_OTA_SLOT_SIZE`` (default: 0x100000)
+- ``ESPRESSIF_OTA_SCRATCH_OFFSET`` (default: 0x220000)
+- ``ESPRESSIF_OTA_SCRATCH_SIZE`` (default: 0x40000)
+- ``ESPRESSIF_STORAGE_MTD_OFFSET`` (default: 0x260000 when MCUBoot enabled)
+- ``ESPRESSIF_STORAGE_MTD_SIZE`` (default: 0x100000)
+
+For MCUBoot operation:
+
+- The **Primary Slot** contains the currently running application
+- The **Secondary Slot** receives OTA updates
+- The **Scratch Partition** is used by MCUBoot for image swapping during updates
+- MCUBoot manages image validation, confirmation, and rollback functionality
+
+
 _`Managing esptool on virtual environment`
 ==========================================
 

Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst

@@ -120,6 +120,21 @@ You can check that the sensor is working by using the ``bmp180`` application::
     Pressure value = 91526
     Pressure value = 91525
 
+buttons
+-------
+
+This configuration shows the use of the buttons subsystem. It can be used by executing
+the ``buttons`` application and pressing the ``BOOT`` button on the board::
+
+    nsh> buttons
+    buttons_main: Starting the button_daemon
+    buttons_main: button_daemon started
+    button_daemon: Running
+    button_daemon: Opening /dev/buttons
+    button_daemon: Supported BUTTONs 0x01
+    nsh> Sample = 1
+    Sample = 0
+
 capture
 --------
 
@@ -342,6 +357,32 @@ nsh
 
 Basic configuration to run the NuttShell (nsh).
 
+oa_tc6
+------
+
+This configuration features the network driver for 10BASE-T1S and 10BASE-T1L SPI MAC-PHYs
+that follow the `OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface` specification (OA-TC6).
+
+Among such MAC-PHYs are e.g. Microchip LAN865x, Onsemi NCV7410 (NCN26010), Analog Devices ADIN1110.
+See the build configuration utility (e.g. ``make menuconfig``) to find out which ones are currently supported.
+
+The OA-TC6 defines a 5 signal connection between the MAC-PHY and the host MCU. These are 4 lines for the standard SPI and 1 line for the interrupt signal from the MAC-PHY to the MCU.
+
+**Default pinout**
+
+============ ========== =========================================
+ESP32-C6 Pin Signal Pin Description
+============ ========== =========================================
+0            CS         SPI Chip Select
+2            MISO       SPI Master In Slave Out
+5            INT        MAC-PHY interrupt signal
+6            CLK        SPI Clock
+7            MOSI       SPI Master Out Slave In
+============ ========== =========================================
+
+The ``oa_tc6`` configuration is additionally equipped with the ``plcatool`` utility. This allows configuration of the Physical Layer Collision Avoidance (PLCA) functionality
+in 10BASE-T1S PHYs.
+
 ostest
 ------
 
@@ -397,6 +438,59 @@ This same configuration enables the usage of the RMT peripheral and the example
 Please note that this board contains an on-board WS2812 LED connected to GPIO8
 and, by default, this config configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/risc-v/esp32c6/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/risc-v/esp32c6/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 
@@ -538,6 +632,44 @@ and running the ``can`` example::
         SJW: 3
       ID:    1 DLC: 1
 
+ulp
+---
+
+This configuration enables the support for the ULP LP core (Low-power core) coprocessor.
+To get more information about LP Core please check :ref:`ULP LP Core Coprocessor docs. <esp32c6_ulp>`
+
+Configuration uses a pre-built binary in ``Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/ulp_blink.bin``
+which is a blink example for GPIO0. After flashing operation, GPIO0 pin will blink.
+
+Prebuild binary runs this code:
+
+.. code-block:: C
+
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_lp_core_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_lp_core_gpio_set_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
 usbconsole
 ----------
 

Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst

@@ -99,6 +99,21 @@ You can check that the sensor is working by using the ``bmp180`` application::
     Pressure value = 91526
     Pressure value = 91525
 
+buttons
+-------
+
+This configuration shows the use of the buttons subsystem. It can be used by executing
+the ``buttons`` application and pressing the ``BOOT`` button on the board::
+
+    nsh> buttons
+    buttons_main: Starting the button_daemon
+    buttons_main: button_daemon started
+    button_daemon: Running
+    button_daemon: Opening /dev/buttons
+    button_daemon: Supported BUTTONs 0x01
+    nsh> Sample = 1
+    Sample = 0
+
 coremark
 --------
 
@@ -267,6 +282,32 @@ nsh
 
 Basic configuration to run the NuttShell (nsh).
 
+oa_tc6
+------
+
+This configuration features the network driver for 10BASE-T1S and 10BASE-T1L SPI MAC-PHYs
+that follow the `OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface` specification (OA-TC6).
+
+Among such MAC-PHYs are e.g. Microchip LAN865x, Onsemi NCV7410 (NCN26010), Analog Devices ADIN1110.
+See the build configuration utility (e.g. ``make menuconfig``) to find out which ones are currently supported.
+
+The OA-TC6 defines a 5 signal connection between the MAC-PHY and the host MCU. These are 4 lines for the standard SPI and 1 line for the interrupt signal from the MAC-PHY to the MCU.
+
+**Default pinout**
+
+============ ========== =========================================
+ESP32-C6 Pin Signal Pin Description
+============ ========== =========================================
+0            CS         SPI Chip Select
+2            MISO       SPI Master In Slave Out
+5            INT        MAC-PHY interrupt signal
+6            CLK        SPI Clock
+7            MOSI       SPI Master Out Slave In
+============ ========== =========================================
+
+The ``oa_tc6`` configuration is additionally equipped with the ``plcatool`` utility. This allows configuration of the Physical Layer Collision Avoidance (PLCA) functionality
+in 10BASE-T1S PHYs.
+
 ostest
 ------
 
@@ -312,6 +353,59 @@ This same configuration enables the usage of the RMT peripheral and the example
 Please note that this board contains an on-board WS2812 LED connected to GPIO8
 and, by default, this config configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/risc-v/esp32c6/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/risc-v/esp32c6/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 

Documentation/platforms/risc-v/esp32c6/index.rst

@@ -178,6 +178,8 @@ Now opening the serial port with a terminal emulator should show the NuttX conso
   nsh> uname -a
   NuttX 12.8.0 759d37b97c-dirty Mar  5 2025 19:42:41 risc-v esp32c6-devkitc
 
+.. _esp32c6_debug:
+
 Debugging
 =========
 
@@ -200,7 +202,7 @@ USB-to-JTAG adapter.
 
 OpenOCD can then be used::
 
-  openocd -s <tcl_scripts_path> -c 'set ESP_RTOS hwthread' -f board/esp32c3-builtin.cfg -c 'init; reset halt; esp appimage_offset 0x0'
+  openocd -s <tcl_scripts_path> -c 'set ESP_RTOS hwthread' -f board/esp32c6-builtin.cfg -c 'init; reset halt; esp appimage_offset 0x0'
 
 .. note::
   - ``appimage_offset`` should be set to ``0x0`` when ``Simple Boot`` is used. For MCUboot, this value should be set to
@@ -486,6 +488,288 @@ Finally, the image is loaded but not confirmed.
 To make sure it won't rollback to the previous image, you must confirm with ``mcuboot_confirm`` and reboot the board.
 The OTA is now complete.
 
+Flash Allocation for MCUBoot
+----------------------------
+
+When MCUBoot is enabled on ESP32-C6, the flash memory is organized as follows
+based on the default KConfig values:
+
+**Flash Layout (MCUBoot Enabled)**
+
+.. list-table::
+   :header-rows: 1
+   :widths: 40 20 20
+   :align: left
+
+   * - Region
+     - Offset
+     - Size
+   * - Bootloader
+     - 0x000000
+     - 64KB
+   * - E-Fuse Virtual (see Note)
+     - 0x010000
+     - 64KB
+   * - Primary Application Slot (/dev/ota0)
+     - 0x020000
+     - 1MB
+   * - Secondary Application Slot (/dev/ota1)
+     - 0x120000
+     - 1MB
+   * - Scratch Partition (/dev/otascratch)
+     - 0x220000
+     - 256KB
+   * - Storage MTD (optional)
+     - 0x260000
+     - 1MB
+   * - Available Flash
+     - 0x360000+
+     - Remaining
+
+.. raw:: html
+
+   <div style="clear: both"></div>
+
+
+**Note**: The E-Fuse Virtual region is optional and only used when
+``ESPRESSIF_EFUSE_VIRTUAL_KEEP_IN_FLASH`` is enabled. However, this 64KB
+location is always allocated in the memory layout to prevent accidental
+erasure during board flashing operations, ensuring data preservation if
+virtual E-Fuses are later enabled.
+
+.. code-block:: text
+
+    Memory Map (Addresses in hex):
+
+    0x000000  ┌─────────────────────────────┐
+              │                             │
+              │      MCUBoot Bootloader     │
+              │           (64KB)            │
+              │                             │
+    0x010000  ├─────────────────────────────┤
+              │       E-Fuse Virtual        │
+              │           (64KB)            │
+    0x020000  ├─────────────────────────────┤
+              │                             │
+              │      Primary App Slot       │
+              │            (1MB)            │
+              │          /dev/ota0          │
+              │                             │
+    0x120000  ├─────────────────────────────┤
+              │                             │
+              │     Secondary App Slot      │
+              │            (1MB)            │
+              │          /dev/ota1          │
+              │                             │
+    0x220000  ├─────────────────────────────┤
+              │                             │
+              │      Scratch Partition      │
+              │           (256KB)           │
+              │       /dev/otascratch       │
+              │                             │
+    0x260000  ├─────────────────────────────┤
+              │                             │
+              │    Storage MTD (optional)   │
+              │            (1MB)            │
+              │                             │
+    0x360000  ├─────────────────────────────┤
+              │                             │
+              │       Available Flash       │
+              │         (Remaining)         │
+              │                             │
+              └─────────────────────────────┘
+
+The key KConfig options that control this layout:
+
+- ``ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET`` (default: 0x20000)
+- ``ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET`` (default: 0x120000)
+- ``ESPRESSIF_OTA_SLOT_SIZE`` (default: 0x100000)
+- ``ESPRESSIF_OTA_SCRATCH_OFFSET`` (default: 0x220000)
+- ``ESPRESSIF_OTA_SCRATCH_SIZE`` (default: 0x40000)
+- ``ESPRESSIF_STORAGE_MTD_OFFSET`` (default: 0x260000 when MCUBoot enabled)
+- ``ESPRESSIF_STORAGE_MTD_SIZE`` (default: 0x100000)
+
+For MCUBoot operation:
+
+- The **Primary Slot** contains the currently running application
+- The **Secondary Slot** receives OTA updates
+- The **Scratch Partition** is used by MCUBoot for image swapping during updates
+- MCUBoot manages image validation, confirmation, and rollback functionality
+
+.. _esp32c6_ulp:
+
+ULP LP Core Coprocessor
+=======================
+
+The ULP LP core (Low-power core) is a 32-bit RISC-V coprocessor integrated into the ESP32-C6 SoC.
+It is designed to run independently of the main high-performance (HP) core and is capable of executing lightweight tasks
+such as GPIO polling, simple peripheral control and I/O interactions.
+
+This coprocessor benefits to offload simple tasks from HP core (e.g., GPIO polling , I2C operations, basic control logic) and
+frees the main CPU for higher-level processing
+
+For more information about ULP LP Core Coprocessor `check here <https://docs.espressif.com/projects/esp-idf/en/stable/esp32c6/api-reference/system/ulp-lp-core.html>`__.
+
+Features of the ULP LP-Core
+---------------------------
+
+* Processor Architecture
+   - RV32I RISC-V core with IMAC extensions—Integer (I), Multiplication/Division (M), Atomic (A), and Compressed (C) instructions
+   - Runs at 20 MHz
+* Memory
+   - Access to 16 KB of low-power memory (LP-RAM) and LP-domain peripherals any time
+   - Full access to all of the chip's memory and peripherals when when the HP core is active
+* Debugging
+   - Built-in JTAG debug module for external debugging
+   - Supports LP UART for logging from the ULP itself
+   - Includes a panic handler capable of dumping register state via LP UART on exceptions
+* Peripheral support
+   - LP domain peripherals (LP GPIO, LP I2C, LP UART and LP Timer)
+   - Full access HP domain peripherals when when the HP core is active
+
+Loading Binary into ULP LP-Core
+-------------------------------
+
+There are two ways to load a binary into LP-Core:
+  - Using a prebuilt binary
+  - Using NuttX internal build system to build your own (bare-metal) application
+
+When using a prebuilt binary, the already compiled output for the ULP system whether built from NuttX
+or the ESP-IDF environment can be leveraged. However, whenever the ULP code needs to be modified, it must be rebuilt separately,
+and the resulting .bin file has to be integrated into NuttX. This workflow, while compatible, can become tedious.
+
+With NuttX internal build system, the ULP binary code can be built and flashed from a single location. It is more convenient but
+using build system has some dependencies on example side.
+
+Both methods requires `CONFIG_ESPRESSIF_USE_LP_CORE` variable to enable ULP core and
+`CONFIG_ESPRESSIF_ULP_PROJECT_PATH` variable to set the path to the ULP project or prebuilt binary file
+relative to NuttX root folder.
+These variables can be set using `make menuconfig` or `kconfig-tweak` commands.
+
+Here is an example for enabling ULP and using a prebuilt binary for ULP core::
+
+    make distclean
+    ./tools/configure.sh esp32c6-devkitc:nsh
+    kconfig-tweak -e CONFIG_ESPRESSIF_USE_LP_CORE
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_PROJECT_PATH "Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/ulp_blink.bin"
+    make olddefconfig
+    make -j
+
+Creating an ULP LP-Core Application
+-----------------------------------
+
+To use NuttX's internal build system to compile the bare-metal LP binary, check the following instructions.
+
+First, create a folder for the ULP source and header files. This folder is just for ULP project and it is
+an independent project. Therefore, the NuttX example guide should not be followed, and no Makefile or similar
+build files should be added. Also folder location could be anywhere. To include ULP folder into build
+system don't forget to set `CONFIG_ESPRESSIF_ULP_PROJECT_PATH` variable with path of the ULP project folder relative to
+NuttX root folder. Instructions for setting up can be found above.
+
+NuttX's internal functions or POSIX calls are not supported.
+
+Here is an example:
+
+- ULP UART Snippet:
+
+.. code-block:: C
+
+  #include <stdint.h>
+  #include "ulp_lp_core_print.h"
+  #include "ulp_lp_core_utils.h"
+  #include "ulp_lp_core_uart.h"
+  #include "ulp_lp_core_gpio.h"
+
+  #define nop() __asm__ __volatile__ ("nop")
+
+  int main (void)
+  {
+    while(1)
+    {
+
+      lp_core_printf("Hello from the LP core!!\r\n");
+      for (int i = 0; i < 10000; i++)
+        {
+          nop();
+        }
+    }
+
+    return 0;
+  }
+
+For more information about ULP Core Coprocessor examples `check here <https://github.com/espressif/esp-idf/tree/master/examples/system/ulp/lp_core>`__.
+After these settings follow the same steps as for any other configuration to build NuttX. Build system checks ULP project path,
+adds every source and header file into project and builds it.
+
+To sum up, here is an complete example. `ulp_example/ulp (../ulp_example/ulp)` folder selected as example
+to create a subfolder for ULP but folder that includes ULP source code can be anywhere:
+
+- Tree view:
+
+.. code-block:: text
+
+   nuttxspace/
+   ├── nuttx/
+   └── apps/
+   └── ulp_example/
+       └── ulp/
+           └── ulp_main.c
+
+- Contents in ulp_main.c:
+
+.. code-block:: C
+
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_lp_core_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_lp_core_gpio_set_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
+- Command to build::
+
+    make distclean
+    ./tools/configure.sh esp32c6-devkitc:nsh
+    kconfig-tweak -e CONFIG_ESPRESSIF_GPIO_IRQ
+    kconfig-tweak -e CONFIG_DEV_GPIO
+    kconfig-tweak -e CONFIG_ESPRESSIF_USE_LP_CORE
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_PROJECT_PATH "../ulp_example/ulp"
+    make olddefconfig
+    make -j
+
+Debugging ULP LP-Core
+---------------------
+
+To debug ULP LP-Core please first refer to :ref:`Debugging section. <esp32c6_debug>`
+Debugging ULP core consist same steps with some small differences. First of all, configuration file
+needs to be changed from `board/esp32c6-builtin.cfg` or `board/esp32c6-ftdi.cfg` to
+`board/esp32c6-lpcore-builtin.cfg` or `board/esp32c6-lpcore-ftdi.cfg` depending on preferred debug adapter.
+
+LP core supports limited set of HW exceptions, so, for example, writing at address
+0x0 will not cause a panic as it would be for the code running on HP core.
+This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application,
+so ubsan can help to catch some errors. But note that it will increase code size significantly and
+it can happen that application won't fit into RTC RAM.
+To enable ubsan for ULP please add `CONFIG_ESPRESSIF_ULP_ENABLE_UBSAN` in menuconfig.
+
 _`Managing esptool on virtual environment`
 ==========================================
 

Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst

@@ -119,6 +119,21 @@ You can check that the sensor is working by using the ``bmp180`` application::
     Pressure value = 91526
     Pressure value = 91525
 
+buttons
+-------
+
+This configuration shows the use of the buttons subsystem. It can be used by executing
+the ``buttons`` application and pressing the ``BOOT`` button on the board::
+
+    nsh> buttons
+    buttons_main: Starting the button_daemon
+    buttons_main: button_daemon started
+    button_daemon: Running
+    button_daemon: Opening /dev/buttons
+    button_daemon: Supported BUTTONs 0x01
+    nsh> Sample = 1
+    Sample = 0
+
 coremark
 --------
 
@@ -355,6 +370,59 @@ This same configuration enables the usage of the RMT peripheral and the example
 Please note that this board contains an on-board WS2812 LED connected to GPIO8
 and, by default, this config configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/risc-v/esp32h2/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/risc-v/esp32h2/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 

Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst

@@ -924,6 +924,59 @@ to ESP32 GPIO 4 and run::
 
     nsh> ws2812esp32 0 <number_of_leds_on_strip>
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/xtensa/esp32/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/xtensa/esp32/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 

Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst

@@ -475,6 +475,59 @@ This same configuration enables the usage of the RMT peripheral and the example
 Please note that this board contains an on-board WS2812 LED connected to GPIO18
 and, by default, this config configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/xtensa/esp32s2/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/xtensa/esp32s2/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 
@@ -568,6 +621,47 @@ the ``Device Drivers -> CAN Driver Support -> CAN loopback mode`` option and run
         SJW: 3
       ID:    1 DLC: 1
 
+ulp
+---
+
+This configuration enables the support for the ULP RISC-V core coprocessor.
+To get more information about LP Core please check :ref:`ULP LP Core Coprocessor docs. <esp32s2_ulp>`
+
+Configuration uses a pre-built binary in ``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/ulp_riscv_blink.bin``
+which is a blink example for GPIO0. After flashing operation, GPIO0 pin will blink.
+
+Prebuild binary runs this code:
+
+.. code-block:: C
+
+   #include <stdio.h>
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_riscv.h"
+   #include "ulp_riscv_utils.h"
+   #include "ulp_riscv_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_riscv_gpio_output_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
 watchdog
 --------
 

Documentation/platforms/xtensa/esp32s2/index.rst

@@ -821,6 +821,167 @@ to ``Application image secondary slot``.
    and change usage mode to ``Release`` in `System Type --> Application Image Configuration --> Enable usage mode`.
    **After disabling UART Download Mode you will not be able to flash other images through UART.**
 
+.. _esp32s2_ulp:
+
+ULP RISC-V Coprocessor
+======================
+
+The ULP RISC-V core is a 32-bit coprocessor integrated into the ESP32-S2 SoC.
+It is designed to run independently of the main high-performance (HP) core and is capable of executing lightweight tasks
+such as GPIO polling, simple peripheral control and I/O interactions.
+
+This coprocessor benefits to offload simple tasks from HP core (e.g., GPIO polling , I2C operations, basic control logic) and
+frees the main CPU for higher-level processing
+
+For more information about ULP RISC-V Coprocessor `check here <https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-reference/system/ulp-risc-v.html>`__.
+
+Features of the ULP RISC-V Coprocessor
+--------------------------------------
+
+* Processor Architecture
+   - RV32IMC RISC-V core — Integer (I), Multiplication/Division (M), and Compressed (C) instructions
+   - Runs at 17.5 MHz
+* Memory
+   - Access to 8 KB of RTC slow memory (RTC_SLOW_MEM) memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals
+* Debugging
+   - Logging via bit-banged UART
+   - Shared memory for state inspection
+   - Panic or exception handlers can trigger wake-up or signal to main CPU if main CPU is in sleep
+* Peripheral support
+   - RTC domain peripherals (RTC GPIO, RTC I2C, ADC)
+
+Loading Binary into ULP RISC-V Coprocessor
+------------------------------------------
+
+There are two ways to load a binary into LP-Core:
+  - Using a prebuilt binary
+  - Using NuttX internal build system to build your own (bare-metal) application
+
+When using a prebuilt binary, the already compiled output for the ULP system whether built from NuttX
+or the ESP-IDF environment can be leveraged. However, whenever the ULP code needs to be modified, it must be rebuilt separately,
+and the resulting .bin file has to be integrated into NuttX. This workflow, while compatible, can become tedious.
+
+With NuttX internal build system, the ULP binary code can be built and flashed from a single location. It is more convenient but
+using build system has some dependencies on example side.
+
+Both methods requires `CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM` variable to set ULP RISC-V core and
+`CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH` variable to set the path to the ULP project or prebuilt binary file
+relative to NuttX root folder.
+These variables can be set using `make menuconfig` or `kconfig-tweak` commands.
+
+Here is an example for enabling ULP and using a prebuilt binary for ULP RISC-V core::
+
+    make distclean
+    ./tools/configure.sh esp32s2-saola-1:nsh
+    kconfig-tweak --set-val CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM 8176
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH "Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/ulp_riscv_blink.bin"
+    make olddefconfig
+    make -j
+
+Creating an ULP RISC-V Coprocessor Application
+----------------------------------------------
+
+To use NuttX's internal build system to compile the bare-metal ULP RISC-V Coprocessor binary, check the following instructions.
+
+First, create a folder for the ULP source and header files. This folder is just for ULP project and it is
+an independent project. Therefore, the NuttX example guide should not be followed, and no Makefile or similar
+build files should be added. Also folder location could be anywhere. To include ULP folder into build
+system don't forget to set `CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH` variable with path of the ULP project folder relative to
+NuttX root folder. Instructions for setting up can be found above.
+
+NuttX's internal functions or POSIX calls are not supported.
+
+Here is an example:
+
+- ULP UART Snippet:
+
+.. code-block:: C
+
+  #include "ulp_riscv.h"
+  #include "ulp_riscv_utils.h"
+  #include "ulp_riscv_print.h"
+  #include "ulp_riscv_uart_ulp_core.h"
+  #include "sdkconfig.h"
+
+  static ulp_riscv_uart_t s_print_uart;
+
+  int main (void)
+  {
+    ulp_riscv_uart_cfg_t cfg = {
+        .tx_pin = 0,
+    };
+    ulp_riscv_uart_init(&s_print_uart, &cfg);
+    ulp_riscv_print_install((putc_fn_t)ulp_riscv_uart_putc, &s_print_uart);
+
+    while(1)
+    {
+      ulp_riscv_print_str("Hello from the LP core!!\r\n");
+      ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
+    }
+
+    return 0;
+  }
+
+For more information about ULP RISC-V Coprocessor examples `check here <https://github.com/espressif/esp-idf/tree/master/examples/system/ulp/lp_core>`__.
+After these settings follow the same steps as for any other configuration to build NuttX. Build system checks ULP project path,
+adds every source and header file into project and builds it.
+
+To sum up, here is an complete example. `ulp_example/ulp (../ulp_example/ulp)` folder selected as example
+to create a subfolder for ULP but folder that includes ULP source code can be anywhere:
+
+- Tree view:
+
+.. code-block:: text
+
+   nuttxspace/
+   ├── nuttx/
+   └── apps/
+   └── ulp_example/
+       └── ulp/
+           └── ulp_main.c
+
+- Contents in ulp_main.c:
+
+.. code-block:: C
+
+   #include <stdio.h>
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_riscv.h"
+   #include "ulp_riscv_utils.h"
+   #include "ulp_riscv_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_riscv_gpio_output_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
+- Command to build::
+
+    make distclean
+    ./tools/configure.sh esp32s2-saola-1:nsh
+    kconfig-tweak --set-val CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM 8176
+    kconfig-tweak -e CONFIG_DEV_GPIO
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH "../ulp_example/ulp"
+    make olddefconfig
+    make -j
+
 _`Managing esptool on virtual environment`
 ==========================================
 

Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst

@@ -639,7 +639,7 @@ Enables PM support. You can define standby mode and sleep mode delay time::
 
 You can also define an EXT1 wakeup for both sleep modes by selecting which RTC
 GPIO will be used and the logic level that will trigger it::
-    
+
     $ make menuconfig
     -> Board Selection
         -> [*] PM EXT1 Wakeup
@@ -829,6 +829,59 @@ Please note that this board contains an on-board WS2812 LED connected to GPIO48
 (or GPIO38, depending on the board version) and, by default, this config
 configures the RMT transmitter in the same pin.
 
+romfs
+-----
+
+This configuration demonstrates the use of ROMFS (Read-Only Memory File System) to provide
+automated system initialization and startup scripts. ROMFS allows embedding a read-only
+filesystem directly into the NuttX binary, which is mounted at ``/etc`` during system startup.
+
+**What ROMFS provides:**
+
+* **System initialization script** (``/etc/init.d/rc.sysinit``): Executed after board bring-up
+* **Startup script** (``/etc/init.d/rcS``): Executed after system init, typically used to start applications
+
+**Default behavior:**
+
+When this configuration is used, NuttX will:
+
+1. Create a read-only RAM disk containing the ROMFS filesystem
+2. Mount the ROMFS at ``/etc``
+3. Execute ``/etc/init.d/rc.sysinit`` during system initialization
+4. Execute ``/etc/init.d/rcS`` for application startup
+
+**Customizing startup scripts:**
+
+The startup scripts are located in:
+``boards/xtensa/esp32s3/common/src/etc/init.d/``
+
+* ``rc.sysinit`` - System initialization script
+* ``rcS`` - Application startup script
+
+To customize these scripts:
+
+1. **Edit the script files** in ``boards/xtensa/esp32s3/common/src/etc/init.d/``
+2. **Add your initialization commands** using any NSH-compatible commands
+
+**Example customizations:**
+
+* **rc.sysinit** - Set up system services, mount additional filesystems, configure network.
+* **rcS** - Start your application, launch daemons, configure peripherals. This is executed after the rc.sysinit script.
+
+Example output::
+
+    *** Booting NuttX ***
+    [...]
+    rc.sysinit is called!
+    rcS file is called!
+    NuttShell (NSH) NuttX-12.8.0
+    nsh> ls /etc/init.d
+    /etc/init.d:
+    .
+    ..
+    rc.sysinit
+    rcS
+
 rtc
 ---
 
@@ -985,13 +1038,13 @@ board terminal::
 
     nsh> spislv -x 5 1a2b3c4d5e
 
-This command enqueues the data sequence ``1a2b3c4d5e`` in the slave buffer.  
+This command enqueues the data sequence ``1a2b3c4d5e`` in the slave buffer.
 On the next transfer, the external SPI master should receive this data back
 from the slave.
 
 By default, SPI2 pins are used for the slave interface. The exact pin mapping
 depends on the ESP32-S3 DevKit version and can be adjusted through
-``menuconfig`` under *System type → SPI configuration*.  
+``menuconfig`` under *System type → SPI configuration*.
 
 sta_softap
 ----------
@@ -1098,6 +1151,47 @@ the ``Device Drivers -> CAN Driver Support -> CAN loopback mode`` option and run
         SJW: 3
       ID:    1 DLC: 1
 
+ulp
+---
+
+This configuration enables the support for the ULP RISC-V core coprocessor.
+To get more information about LP Core please check :ref:`ULP LP Core Coprocessor docs. <esp32s3_ulp>`
+
+Configuration uses a pre-built binary in ``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/ulp_riscv_blink.bin``
+which is a blink example for GPIO0. After flashing operation, GPIO0 pin will blink.
+
+Prebuild binary runs this code:
+
+.. code-block:: C
+
+   #include <stdio.h>
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_riscv.h"
+   #include "ulp_riscv_utils.h"
+   #include "ulp_riscv_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_riscv_gpio_output_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
 usbnsh
 ------
 

Documentation/platforms/xtensa/esp32s3/index.rst

@@ -646,6 +646,170 @@ Set the attribute ``__attribute__ ((section (".ext_ram.bss")))`` to the variable
 
 This is particularly useful when the internal RAM is not enough to hold all the data.
 
+.. _esp32s3_ulp:
+
+ULP RISC-V Coprocessor
+======================
+
+The ULP RISC-V core is a 32-bit coprocessor integrated into the ESP32-S3 SoC.
+It is designed to run independently of the main high-performance (HP) core and is capable of executing lightweight tasks
+such as GPIO polling, simple peripheral control and I/O interactions.
+
+This coprocessor benefits to offload simple tasks from HP core (e.g., GPIO polling , I2C operations, basic control logic) and
+frees the main CPU for higher-level processing
+
+For more information about ULP RISC-V Coprocessor `check here <https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/system/ulp-risc-v.html>`__.
+
+Features of the ULP RISC-V Coprocessor
+--------------------------------------
+
+* Processor Architecture
+   - RV32IMC RISC-V core — Integer (I), Multiplication/Division (M), and Compressed (C) instructions
+   - Runs at 17.5 MHz
+* Memory
+   - Access to 8 KB of RTC slow memory (RTC_SLOW_MEM) memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals
+* Debugging
+   - Logging via bit-banged UART
+   - Shared memory for state inspection
+   - Panic or exception handlers can trigger wake-up or signal to main CPU if main CPU is in sleep
+* Peripheral support
+   - RTC domain peripherals (RTC GPIO, RTC I2C, ADC)
+
+Loading Binary into ULP RISC-V Coprocessor
+------------------------------------------
+
+There are two ways to load a binary into LP-Core:
+  - Using a prebuilt binary
+  - Using NuttX internal build system to build your own (bare-metal) application
+
+When using a prebuilt binary, the already compiled output for the ULP system whether built from NuttX
+or the ESP-IDF environment can be leveraged. However, whenever the ULP code needs to be modified, it must be rebuilt separately,
+and the resulting .bin file has to be integrated into NuttX. This workflow, while compatible, can become tedious.
+
+With NuttX internal build system, the ULP binary code can be built and flashed from a single location. It is more convenient but
+using build system has some dependencies on example side.
+
+Both methods requires `CONFIG_ESP32S3_ULP_COPROC_ENABLED` and `CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM` variables to set ULP RISC-V core and
+`CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH` variable to set the path to the ULP project or prebuilt binary file
+relative to NuttX root folder.
+These variables can be set using `make menuconfig` or `kconfig-tweak` commands.
+
+Here is an example for enabling ULP and using a prebuilt binary for ULP RISC-V core::
+
+    make distclean
+    ./tools/configure.sh esp32s3-devkit:nsh
+    kconfig-tweak -e CONFIG_ESP32S3_ULP_COPROC_ENABLED
+    kconfig-tweak --set-val CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM 8176
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH "Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/ulp_riscv_blink.bin"
+    make olddefconfig
+    make -j
+
+Creating an ULP RISC-V Coprocessor Application
+----------------------------------------------
+
+To use NuttX's internal build system to compile the bare-metal ULP RISC-V Coprocessor binary, check the following instructions.
+
+First, create a folder for the ULP source and header files. This folder is just for ULP project and it is
+an independent project. Therefore, the NuttX example guide should not be followed, and no Makefile or similar
+build files should be added. Also folder location could be anywhere. To include ULP folder into build
+system don't forget to set `CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH` variable with path of the ULP project folder relative to
+NuttX root folder. Instructions for setting up can be found above.
+
+NuttX's internal functions or POSIX calls are not supported.
+
+Here is an example:
+
+- ULP UART Snippet:
+
+.. code-block:: C
+
+  #include "ulp_riscv.h"
+  #include "ulp_riscv_utils.h"
+  #include "ulp_riscv_print.h"
+  #include "ulp_riscv_uart_ulp_core.h"
+  #include "sdkconfig.h"
+
+  static ulp_riscv_uart_t s_print_uart;
+
+  int main (void)
+  {
+    ulp_riscv_uart_cfg_t cfg = {
+        .tx_pin = 0,
+    };
+    ulp_riscv_uart_init(&s_print_uart, &cfg);
+    ulp_riscv_print_install((putc_fn_t)ulp_riscv_uart_putc, &s_print_uart);
+
+    while(1)
+    {
+      ulp_riscv_print_str("Hello from the LP core!!\r\n");
+      ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
+    }
+
+    return 0;
+  }
+
+For more information about ULP RISC-V Coprocessor examples `check here <https://github.com/espressif/esp-idf/tree/master/examples/system/ulp/lp_core>`__.
+After these settings follow the same steps as for any other configuration to build NuttX. Build system checks ULP project path,
+adds every source and header file into project and builds it.
+
+To sum up, here is an complete example. `ulp_example/ulp (../ulp_example/ulp)` folder selected as example
+to create a subfolder for ULP but folder that includes ULP source code can be anywhere:
+
+- Tree view:
+
+.. code-block:: text
+
+   nuttxspace/
+   ├── nuttx/
+   └── apps/
+   └── ulp_example/
+       └── ulp/
+           └── ulp_main.c
+
+- Contents in ulp_main.c:
+
+.. code-block:: C
+
+   #include <stdio.h>
+   #include <stdint.h>
+   #include <stdbool.h>
+   #include "ulp_riscv.h"
+   #include "ulp_riscv_utils.h"
+   #include "ulp_riscv_gpio.h"
+
+   #define GPIO_PIN 0
+
+   #define nop() __asm__ __volatile__ ("nop")
+
+   bool gpio_level_previous = true;
+
+   int main (void)
+    {
+       while (1)
+           {
+           ulp_riscv_gpio_output_level(GPIO_PIN, gpio_level_previous);
+           gpio_level_previous = !gpio_level_previous;
+           for (int i = 0; i < 10000; i++)
+             {
+               nop();
+             }
+           }
+
+       return 0;
+    }
+
+- Command to build::
+
+    make distclean
+    ./tools/configure.sh esp32s3-devkitc:nsh
+    kconfig-tweak -e CONFIG_ESP32S3_ULP_COPROC_ENABLED
+    kconfig-tweak --set-val CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM 8176
+    kconfig-tweak -e CONFIG_DEV_GPIO
+    kconfig-tweak --set-str CONFIG_ESPRESSIF_ULP_RISCV_PROJECT_PATH "../ulp_example/ulp"
+    make olddefconfig
+    make -j
+
+
 _`Managing esptool on virtual environment`
 ==========================================
 

Documentation/reference/os/events.rst

@@ -116,6 +116,37 @@ Notifier Chain Interfaces
   :param events: Set of events to wait, 0 will indicate wait from any events
   :param eflags: Events flags
 
+.. c:function:: nxevent_mask_t nxevent_clear(FAR nxevent_t *event, nxevent_mask_t mask)
+
+  This function is used to clear specific bits from the event mask of the given event object.
+
+  :param event: Address of the event object
+  :param mask: Bit mask specifying which event flags should be cleared
+
+.. c:function:: nxevent_mask_t nxevent_tickwait_wait(FAR nxevent_t *event, FAR nxevent_wait_t *wait, nxevent_mask_t events, nxevent_flags_t eflags, uint32_t delay);
+
+  Wait for all of the specified events for the specified tick time.
+
+  This routine is functionally identical to nxevent_tickwait, except that the wait object is explicitly provided by the user.
+  In nxevent_tickwait, the wait object is allocated as a temporary variable on the event-wait thread's stack, and the user has no visibility or control over it.
+  Because this object is accessed by both the event-wait thread and the event-post thread, such an arrangement may lead to safety concerns.
+  To address this, the new function allows the user to supply the wait object directly, providing greater control and improving safety.
+
+  :param event: Address of the event object
+  :param wait:  Address of the event wait object
+  :param events: Set of events to wait, 0 will indicate wait from any events
+  :param eflags: Events flags
+  :param delay: Ticks to wait from the start time until the event is posted,
+                If ticks is zero, then this function is equivalent to nxevent_trywait().
+
+.. c:function:: nxevent_mask_t nxevent_getmask(FAR nxevent_t *event)
+
+  This function returns the event mask value of the current event object.
+
+  :param event: Location to return the event group reference.
+
+  :return: The event mask value of the current event object.
+
 .. c:function:: int nxevent_open(FAR nxevent_t **event, FAR const char *name, int oflags, ...)
 
   This function establishes a connection between named event groups and a

Documentation/reference/user/05_counting_semaphore.rst

@@ -108,6 +108,11 @@ result.
 Semaphore does not support priority inheritance by default. If you need to
 use a semaphore as a mutex you need to change its default behavior.
 
+Each semaphore is assigned a default maximum value defined by SEM_VALUE_MAX.
+If ``CONFIG_CUSTOM_SEMAPHORE_MAXVALUE`` is enabled, applications may override this limit.
+In such cases, the function ``nxsem_setmaxvalue()`` can be used to specify a custom maximum value
+for an individual semaphore.
+
 In user space, it is recommended to use pthread_mutex instead of
 semaphore for resource protection
 

Kconfig

@@ -2455,6 +2455,25 @@ config STACK_COLORATION
 
 		Only supported by a few architectures.
 
+config STACKCHECK_SOFTWARE
+	bool "Software detection of stack overflow"
+	depends on STACK_COLORATION && DEBUG_ASSERTIONS
+	---help---
+		When switching contexts, it will detect whether a stack overflow occurs.
+		Two methods are used here.
+		The first is to check the legitimacy of the value of the sp register;
+		the second is to check the specified number of bytes at the bottom of the stack.
+		If either of these two methods fails, an ASSERT will be triggered.
+
+config STACKCHECK_MARGIN
+	int "Stack overflow check size (bytes)"
+	depends on STACKCHECK_SOFTWARE
+	default 16
+	---help---
+		Specifies the number of bytes at the end of the stack to check for overflow.
+		A value of 0 disables additional checking. Increase this value for stricter
+		overflow detection, at the cost of additional overhead.
+
 config STACK_CANARIES
 	bool "Compiler stack canaries"
 	depends on ARCH_HAVE_STACKCHECK
@@ -2469,6 +2488,46 @@ config STACK_CANARIES
 		Enabling this option can result in a significant increase
 		in footprint and an associated decrease in performance.
 
+choice STACK_CANARIES_LEVEL
+	prompt "Stack Canaries Level Configuration"
+	default STACK_PROTECTOR_ALL
+	depends on STACK_CANARIES
+	---help---
+		Based on the configuration options, configure the stack Canaries Level.
+
+config STACK_PROTECTOR
+	bool "-fstack-protector"
+	---help---
+		Enable basic stack protection.
+
+config STACK_PROTECTOR_STRONG
+	bool "-fstack-protector-strong"
+	---help---
+		Using stronger stack protection mechanisms may involve more complex
+		security checks.
+
+config STACK_PROTECTOR_ALL
+	bool "-fstack-protector-all"
+	---help---
+		Enable stack protection for all functions, including those that are
+		typically not protected.
+
+config STACK_PROTECTOR_EXPLICIT
+	bool "-fstack-protector-explicit"
+	---help---
+		Enable stack protection only for functions explicitly marked as
+		requiring stack protection.
+
+endchoice # Stack Canaries Level Configuration
+
+config STACK_CANARIES_LEVEL
+	string
+	default "-fstack-protector" if STACK_PROTECTOR
+	default "-fstack-protector-strong" if STACK_PROTECTOR_STRONG
+	default "-fstack-protector-all" if STACK_PROTECTOR_ALL
+	default "-fstack-protector-explicit" if STACK_PROTECTOR_EXPLICIT
+	depends on STACK_CANARIES
+
 config STACK_USAGE
 	bool "Generate stack usage information"
 	---help---

arch/Kconfig

@@ -223,23 +223,57 @@ config ARCH
 	default "sparc"   if ARCH_SPARC
 	default "tricore" if ARCH_TRICORE
 
+if ARCH_ARM
 source "arch/arm/Kconfig"
+endif
+if ARCH_ARM64
 source "arch/arm64/Kconfig"
+endif
+if ARCH_AVR
 source "arch/avr/Kconfig"
+endif
+if ARCH_HC
 source "arch/hc/Kconfig"
+endif
+if ARCH_MIPS
 source "arch/mips/Kconfig"
+endif
+if ARCH_MISOC
 source "arch/misoc/Kconfig"
+endif
+if ARCH_RENESAS
 source "arch/renesas/Kconfig"
+endif
+if ARCH_RISCV
 source "arch/risc-v/Kconfig"
+endif
+if ARCH_SIM
 source "arch/sim/Kconfig"
+endif
+if ARCH_X86
 source "arch/x86/Kconfig"
+endif
+if ARCH_X86_64
 source "arch/x86_64/Kconfig"
+endif
+if ARCH_XTENSA
 source "arch/xtensa/Kconfig"
+endif
+if ARCH_Z16
 source "arch/z16/Kconfig"
+endif
+if ARCH_Z80
 source "arch/z80/Kconfig"
+endif
+if ARCH_OR1K
 source "arch/or1k/Kconfig"
+endif
+if ARCH_SPARC
 source "arch/sparc/Kconfig"
+endif
+if ARCH_TRICORE
 source "arch/tricore/Kconfig"
+endif
 
 config ARCH_CHIP_CUSTOM
 	bool "Custom Chip Support"

arch/arm/Kconfig

@@ -1279,6 +1279,26 @@ config ARM_FPU_ABI_SOFT
 	---help---
 		Pass float value via integer register (-mfloat-abi=softfp)
 
+config ARM_BUSY_WAIT
+	bool "Busy wait when boot"
+	default n
+	depends on ARCH_HAVE_MULTICPU
+	---help---
+		On a system with multiple CPU cores, when the system is powered on,
+		multiple cores may start running simultaneously. In this case, software
+		is required to handle the startup logic for multi-core synchronization.
+		One approach is to use global variables.
+		however, the global variable region may not have been initialized yet.
+		In such scenarios, we can use a busywait flag to
+		implement the synchronization strategy.
+
+config ARM_BUSY_WAIT_FLAG_ADDR
+	hex "Busy wait flag address"
+	depends on ARM_BUSY_WAIT
+	---help---
+		The busywait address is typically a region that is initialized to 0
+		during the boot phase.
+
 config ARM_DPFPU32
 	bool "FPU with 32 double-precision register"
 	default y

arch/arm/include/samv7/chip.h

@@ -183,8 +183,8 @@
 #  define SAMV7_NDAC12                1             /* 1 12-bit DAC channel */
 #  define SAMV7_NTCCH                 12            /* 12 Timer/counter channels */
 #  define SAMV7_NTCCHIO               3             /* 3 Timer/counter channels I/O */
-#  define SAMV7_NUSART                0             /* No USARTs */
+#  define SAMV7_NUSART                2             /* 2 USARTs */
-#  define SAMV7_NUART                 5             /* 5 UARTs */
+#  define SAMV7_NUART                 3             /* 3 UARTs */
 #  define SAMV7_NQSPI                 0             /* No Quad SPI */
 #  define SAMV7_NQSPI_SPI             1             /* QSPI functions in SPI mode only */
 #  define SAMV7_NSPI                  0             /* No SPI */
@@ -354,8 +354,8 @@
 #  define SAMV7_NDAC12                1             /* 1 12-bit DAC channels */
 #  define SAMV7_NTCCH                 12            /* 12 Timer/counter channels */
 #  define SAMV7_NTCCHIO               3             /* 3 Timer/counter channels I/O */
-#  define SAMV7_NUSART                0             /* No USARTs */
+#  define SAMV7_NUSART                2             /* 2 USARTs */
-#  define SAMV7_NUART                 5             /* 5 UARTs */
+#  define SAMV7_NUART                 3             /* 3 UARTs */
 #  define SAMV7_NQSPI                 0             /* No Quad SPI */
 #  define SAMV7_NQSPI_SPI             1             /* QSPI functions in SPI mode only */
 #  define SAMV7_NSPI                  0             /* No SPI */

arch/arm/include/stm32h7/chip.h

@@ -76,7 +76,10 @@
     defined (CONFIG_ARCH_CHIP_STM32H7B3LI) || \
     defined (CONFIG_ARCH_CHIP_STM32H745XI) || \
     defined (CONFIG_ARCH_CHIP_STM32H745ZI) || \
-    defined (CONFIG_ARCH_CHIP_STM32H750B)  || \
+    defined (CONFIG_ARCH_CHIP_STM32H750VB) || \
+    defined (CONFIG_ARCH_CHIP_STM32H750ZB) || \
+    defined (CONFIG_ARCH_CHIP_STM32H750IB) || \
+    defined (CONFIG_ARCH_CHIP_STM32H750XB) || \
     defined (CONFIG_ARCH_CHIP_STM32H755II)
 #elif defined(CONFIG_ARCH_CHIP_STM32H747XI)
 #else
@@ -85,7 +88,7 @@
 
 /* Size SRAM */
 
-#if defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
+#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
 /* Memory */
 
 #    define STM32H7_SRAM_SIZE             (512*1024)  /* 512Kb SRAM on AXI bus Matrix (D1) */

arch/arm/include/stm32h7/irq.h

@@ -69,7 +69,9 @@
  * Included Files
  ****************************************************************************/
 
-#if defined(CONFIG_STM32H7_STM32H7X3XX)
+#if defined(CONFIG_STM32H7_STM32H7X0XX)
+#  include <arch/stm32h7/stm32h7x3xx_irq.h>
+#elif defined(CONFIG_STM32H7_STM32H7X3XX)
 #  include <arch/stm32h7/stm32h7x3xx_irq.h>
 #elif defined(CONFIG_STM32H7_STM32H7B3XX)
 #  include <arch/stm32h7/stm32h7x3xx_irq.h>

arch/arm/src/arm/arm_doirq.c

@@ -88,6 +88,8 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   if (regs != tcb->xcp.regs)
     {
+      struct tcb_s **running_task = &g_running_tasks[this_cpu()];
+
 #ifdef CONFIG_ARCH_ADDRENV
       /* Make sure that the address environment for the previously
        * running task is closed down gracefully (data caches dump,
@@ -100,15 +102,14 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
       /* Update scheduler parameters */
 
-      nxsched_suspend_scheduler(g_running_tasks[this_cpu()]);
+      nxsched_switch_context(*running_task, tcb);
-      nxsched_resume_scheduler(tcb);
 
       /* Record the new "running" task when context switch occurred.
        * g_running_tasks[] is only used by assertion logic for reporting
        * crashes.
        */
 
-      g_running_tasks[this_cpu()] = tcb;
+      *running_task = tcb;
 
       regs = tcb->xcp.regs;
     }

arch/arm/src/arm/arm_syscall.c

@@ -92,10 +92,15 @@ uint32_t *arm_syscall(uint32_t *regs)
 
         /* Update scheduler parameters */
 
-        nxsched_resume_scheduler(tcb);
+        nxsched_switch_context(*running_task, tcb);
 
       case SYS_restore_context:
-        nxsched_suspend_scheduler(*running_task);
+
+        /* No context switch occurs in SYS_restore_context, or the
+         * context switch has been completed, so there is no
+         * need to update scheduler parameters.
+         */
+
         *running_task = tcb;
 
         /* Restore the cpu lock */

arch/arm/src/armv6-m/arm_doirq.c

@@ -102,10 +102,13 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   tcb = this_task();
 
-  /* Update scheduler parameters */
+  /* Update scheduler parameters.
+   * The arm-m architecture svc call will trigger an interrupt,
+   * and the actual context switch is executed after doirq is completed,
+   * so only the scheduling information needs to be updated in doirq.
+   */
 
-  nxsched_suspend_scheduler(*running_task);
+  nxsched_switch_context(*running_task, tcb);
-  nxsched_resume_scheduler(tcb);
 
   /* Record the new "running" task when context switch occurred.
    * g_running_tasks[] is only used by assertion logic for reporting

arch/arm/src/armv7-a/Kconfig

@@ -62,17 +62,6 @@ config ARMV7A_HAVE_L2CC
 		Selected by the configuration tool if the architecture supports any
 		kind of L2 cache.
 
-config ARMV7A_SMP_BUSY_WAIT
-	bool "Busy wait when SMP boot"
-	default n
-	depends on SMP
-	---help---
-		Enables busy wait when SMP boot
-
-config ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
-	hex "Busy wait flag address"
-	depends on ARMV7A_SMP_BUSY_WAIT
-
 config ARMV7A_HAVE_L2CC_PL310
 	bool
 	default n

arch/arm/src/armv7-a/arm_cpustart.c

@@ -77,10 +77,6 @@ int arm_start_handler(int irq, void *context, void *arg)
   sched_note_cpu_started(tcb);
 #endif
 
-  /* Reset scheduler parameters */
-
-  nxsched_resume_scheduler(tcb);
-
   UNUSED(tcb);
 
   return OK;

arch/arm/src/armv7-a/arm_doirq.c

@@ -88,6 +88,8 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   if (regs != tcb->xcp.regs)
     {
+      struct tcb_s **running_task = &g_running_tasks[this_cpu()];
+
 #ifdef CONFIG_ARCH_ADDRENV
       /* Make sure that the address environment for the previously
        * running task is closed down gracefully (data caches dump,
@@ -100,15 +102,14 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
       /* Update scheduler parameters */
 
-      nxsched_suspend_scheduler(g_running_tasks[this_cpu()]);
+      nxsched_switch_context(*running_task, tcb);
-      nxsched_resume_scheduler(tcb);
 
       /* Record the new "running" task when context switch occurred.
        * g_running_tasks[] is only used by assertion logic for reporting
        * crashes.
        */
 
-      g_running_tasks[this_cpu()] = tcb;
+      *running_task = tcb;
       regs = tcb->xcp.regs;
     }
 

arch/arm/src/armv7-a/arm_head.S

@@ -187,8 +187,8 @@ __start:
 	cmp		r0, #0
 	beq		__cpu0_start
 
-#ifdef CONFIG_ARMV7A_SMP_BUSY_WAIT
+#ifdef CONFIG_ARM_BUSY_WAIT
-	ldr		r2, =CONFIG_ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
+	ldr		r2, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
 1:
 	ldr		r1, [r2, #0]
 	cmp		r1, #0
@@ -690,8 +690,8 @@ __cpu0_start:
 
 	/* finish busy wait */
 
-#ifdef CONFIG_ARMV7A_SMP_BUSY_WAIT
+#ifdef CONFIG_ARM_BUSY_WAIT
-	ldr		r0, =CONFIG_ARMV7A_SMP_BUSY_WAIT_FLAG_ADDR
+	ldr		r0, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
 	mov		r1, #1
 	str		r1, [r0]
 	dsb		sy

arch/arm/src/armv7-a/arm_syscall.c

@@ -270,10 +270,15 @@ uint32_t *arm_syscall(uint32_t *regs)
 
         /* Update scheduler parameters */
 
-        nxsched_resume_scheduler(tcb);
+        nxsched_switch_context(*running_task, tcb);
 
       case SYS_restore_context:
-        nxsched_suspend_scheduler(*running_task);
+
+        /* No context switch occurs in SYS_restore_context, or the
+         * context switch has been completed, so there is no
+         * need to update scheduler parameters.
+         */
+
         *running_task = tcb;
 
         /* Restore the cpu lock */

arch/arm/src/armv7-m/arm_doirq.c

@@ -102,10 +102,13 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   tcb = this_task();
 
-  /* Update scheduler parameters */
+  /* Update scheduler parameters.
+   * The arm-m architecture svc call will trigger an interrupt,
+   * and the actual context switch is executed after doirq is completed,
+   * so only the scheduling information needs to be updated in doirq.
+   */
 
-  nxsched_suspend_scheduler(*running_task);
+  nxsched_switch_context(*running_task, tcb);
-  nxsched_resume_scheduler(tcb);
 
   /* Record the new "running" task when context switch occurred.
    * g_running_tasks[] is only used by assertion logic for reporting

arch/arm/src/armv7-r/arm_cpustart.c

@@ -77,10 +77,6 @@ int arm_start_handler(int irq, void *context, void *arg)
   sched_note_cpu_started(tcb);
 #endif
 
-  /* Reset scheduler parameters */
-
-  nxsched_resume_scheduler(tcb);
-
   UNUSED(tcb);
 
   return OK;

arch/arm/src/armv7-r/arm_doirq.c

@@ -77,17 +77,18 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   if (regs != tcb->xcp.regs)
     {
+      struct tcb_s **running_task = &g_running_tasks[this_cpu()];
+
       /* Update scheduler parameters */
 
-      nxsched_suspend_scheduler(g_running_tasks[this_cpu()]);
+      nxsched_switch_context(*running_task, tcb);
-      nxsched_resume_scheduler(tcb);
 
       /* Record the new "running" task when context switch occurred.
        * g_running_tasks[] is only used by assertion logic for reporting
        * crashes.
        */
 
-      g_running_tasks[this_cpu()] = tcb;
+      *running_task = tcb;
       regs = tcb->xcp.regs;
     }
 

arch/arm/src/armv7-r/arm_head.S

@@ -134,7 +134,17 @@ __start:
 	and		r0, r0, #0x3
 	cmp		r0, #0
 	beq		__cpu0_start
+
+#ifdef CONFIG_ARM_BUSY_WAIT
+	ldr		r2, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
+1:
+	ldr		r1, [r2, #0]
+	cmp		r1, #0
+	beq		1b
+#else
 	wfe
+#endif
+
 	cmp		r0, #1
 	beq		__cpu1_start
 #  if CONFIG_SMP_NCPUS > 2
@@ -395,6 +405,15 @@ __cpu0_start:
 
 	b		arm_boot
 
+	/* finish busy wait */
+
+#if defined(CONFIG_ARM_BUSY_WAIT) && defined(CONFIG_SMP)
+	ldr		r0, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
+	mov		r1, #1
+	str		r1, [r0]
+	dsb		sy
+#endif
+
 	/* .text Data */
 
 .Lstackpointer:

arch/arm/src/armv7-r/arm_syscall.c

@@ -267,10 +267,15 @@ uint32_t *arm_syscall(uint32_t *regs)
 
         /* Update scheduler parameters */
 
-        nxsched_resume_scheduler(tcb);
+        nxsched_switch_context(*running_task, tcb);
 
       case SYS_restore_context:
-        nxsched_suspend_scheduler(*running_task);
+
+        /* No context switch occurs in SYS_restore_context, or the
+         * context switch has been completed, so there is no
+         * need to update scheduler parameters.
+         */
+
         *running_task = tcb;
 
         /* Restore the cpu lock */

arch/arm/src/armv8-m/arm_doirq.c

@@ -113,10 +113,13 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   tcb = this_task();
 
-  /* Update scheduler parameters */
+  /* Update scheduler parameters.
+   * The arm-m architecture svc call will trigger an interrupt,
+   * and the actual context switch is executed after doirq is completed,
+   * so only the scheduling information needs to be updated in doirq.
+   */
 
-  nxsched_suspend_scheduler(*running_task);
+  nxsched_switch_context(*running_task, tcb);
-  nxsched_resume_scheduler(tcb);
 
   /* Record the new "running" task when context switch occurred.
    * g_running_tasks[] is only used by assertion logic for reporting

arch/arm/src/armv8-m/arm_schedulesigaction.c

@@ -119,6 +119,11 @@ void up_schedule_sigaction(struct tcb_s *tcb)
 
       tcb->xcp.saved_regs           = tcb->xcp.regs;
 
+      /* Stack pointer should be 8-byte aligned */
+
+      tcb->xcp.regs                 = (void *)STACK_ALIGN_DOWN(
+                                      (uint32_t)tcb->xcp.regs);
+
       /* Duplicate the register context.  These will be
        * restored by the signal trampoline after the signal has been
        * delivered.

arch/arm/src/armv8-r/arm_doirq.c

@@ -78,17 +78,18 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
   if (regs != tcb->xcp.regs)
     {
+      struct tcb_s **running_task = &g_running_tasks[this_cpu()];
+
       /* Update scheduler parameters */
 
-      nxsched_suspend_scheduler(g_running_tasks[this_cpu()]);
+      nxsched_switch_context(*running_task, tcb);
-      nxsched_resume_scheduler(tcb);
 
       /* Record the new "running" task when context switch occurred.
        * g_running_tasks[] is only used by assertion logic for reporting
        * crashes.
        */
 
-      g_running_tasks[this_cpu()] = tcb;
+      *running_task = tcb;
       regs = tcb->xcp.regs;
     }
 

arch/arm/src/armv8-r/arm_head.S

@@ -142,7 +142,17 @@ __start:
 	cmp		r0, #0
 #if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
 	beq		__cpu0_start
+
+#ifdef CONFIG_ARM_BUSY_WAIT
+	ldr		r2, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
+1:
+	ldr		r1, [r2, #0]
+	cmp		r1, #0
+	beq		1b
+#else
 	wfe
+#endif
+
 	cmp		r0, #1
 	beq		__cpu1_start
 #  if CONFIG_SMP_NCPUS > 2
@@ -247,6 +257,13 @@ __cpu0_start:
 	mov		lr, #0				/* LR = return address (none) */
 	b		nx_start			/* Branch to nx_start */
 
+#if defined(CONFIG_ARM_BUSY_WAIT) && defined(CONFIG_SMP)
+	ldr		r0, =CONFIG_ARM_BUSY_WAIT_FLAG_ADDR
+	mov		r1, #1
+	str		r1, [r0]
+	dsb		sy
+#endif
+
 	/* .text Data */
 
 .Lstackpointer:

arch/arm/src/armv8-r/arm_syscall.c

@@ -267,11 +267,16 @@ uint32_t *arm_syscall(uint32_t *regs)
 
         /* Update scheduler parameters */
 
-        nxsched_resume_scheduler(tcb);
+        nxsched_switch_context(*running_task, tcb);
 
       case SYS_restore_context:
-        nxsched_suspend_scheduler(*running_task);
+        /* No context switch occurs in SYS_restore_context, or the
+         * context switch has been completed, so there is no
+         * need to update scheduler parameters.
+         */
+
         *running_task = tcb;
+        g_running_tasks[cpu] = *running_task;
 
         /* Restore the cpu lock */
 

arch/arm/src/cmake/armclang.cmake

@@ -107,7 +107,7 @@ else()
 endif()
 
 if(CONFIG_STACK_CANARIES)
-  add_compile_options(-fstack-protector-all)
+  add_compile_options(${CONFIG_STACK_CANARIES_LEVEL})
 endif()
 
 if(CONFIG_STACK_USAGE)

arch/arm/src/cmake/clang.cmake

@@ -111,7 +111,7 @@ else()
 endif()
 
 if(CONFIG_STACK_CANARIES)
-  add_compile_options(-fstack-protector-all)
+  add_compile_options(${CONFIG_STACK_CANARIES_LEVEL})
 endif()
 
 if(CONFIG_STACK_USAGE)

arch/arm/src/cmake/gcc.cmake

@@ -126,7 +126,7 @@ else()
 endif()
 
 if(CONFIG_STACK_CANARIES)
-  add_compile_options(-fstack-protector-all)
+  add_compile_options(${CONFIG_STACK_CANARIES_LEVEL})
 endif()
 
 if(CONFIG_STACK_USAGE)

arch/arm/src/cmake/ghs.cmake

@@ -79,7 +79,7 @@ else()
 endif()
 
 if(CONFIG_STACK_CANARIES)
-  add_compile_options(-fstack-protector-all)
+  add_compile_options(${CONFIG_STACK_CANARIES_LEVEL})
 endif()
 
 if(CONFIG_STACK_USAGE)

arch/arm/src/common/CMakeLists.txt

@@ -43,10 +43,6 @@ set(SRCS
     arm_poweroff.c
     ${ARCH_TOOLCHAIN_PATH}/fork.S)
 
-if(NOT CONFIG_ALARM_ARCH AND NOT CONFIG_TIMER_ARCH)
-  list(APPEND SRCS arm_mdelay.c arm_udelay.c)
-endif()
-
 if(CONFIG_STACK_COLORATION)
   list(APPEND SRCS arm_checkstack.c)
 endif()

arch/arm/src/common/Make.defs

@@ -30,12 +30,6 @@ CMN_CSRCS += arm_nputs.c arm_releasestack.c arm_registerdump.c
 CMN_CSRCS += arm_stackframe.c arm_modifyreg.c
 CMN_CSRCS += arm_usestack.c arm_fork.c arm_poweroff.c
 
-ifneq ($(CONFIG_ALARM_ARCH),y)
-  ifneq ($(CONFIG_TIMER_ARCH),y)
-    CMN_CSRCS += arm_mdelay.c arm_udelay.c
-  endif
-endif
-
 ifeq ($(CONFIG_STACK_COLORATION),y)
   CMN_CSRCS += arm_checkstack.c
 endif

arch/arm/src/common/Toolchain.defs

@@ -63,7 +63,7 @@ else
 endif
 
 ifeq ($(CONFIG_STACK_CANARIES),y)
-  ARCHOPTIMIZATION += -fstack-protector-all
+  ARCHOPTIMIZATION += $(patsubst "%",%,$(CONFIG_STACK_CANARIES_LEVEL))
 endif
 
 ifeq ($(CONFIG_STACK_USAGE),y)

arch/arm/src/common/arm_checkstack.c

@@ -200,7 +200,7 @@ void arm_stack_color(void *stackbase, size_t nbytes)
  *
  ****************************************************************************/
 
-size_t up_check_tcbstack(struct tcb_s *tcb)
+size_t up_check_tcbstack(struct tcb_s *tcb, size_t check_size)
 {
   size_t size;
 
@@ -213,7 +213,7 @@ size_t up_check_tcbstack(struct tcb_s *tcb)
     }
 #endif
 
-  size = arm_stack_check(tcb->stack_base_ptr, tcb->adj_stack_size);
+  size = arm_stack_check(tcb->stack_base_ptr, check_size);
 
 #ifdef CONFIG_ARCH_ADDRENV
   if (tcb->addrenv_own != NULL)
@@ -226,10 +226,14 @@ size_t up_check_tcbstack(struct tcb_s *tcb)
 }
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3
-size_t up_check_intstack(int cpu)
+size_t up_check_intstack(int cpu, size_t check_size)
 {
-  return arm_stack_check((void *)up_get_intstackbase(cpu),
+  if (check_size == 0)
-                         STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
+    {
+      check_size = STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK);
+    }
+
+  return arm_stack_check((void *)up_get_intstackbase(cpu), check_size);
 }
 #endif
 

arch/arm/src/common/arm_usestack.c

@@ -73,6 +73,9 @@
 
 int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
 {
+  uintptr_t top_of_stack;
+  size_t size_of_stack;
+
 #ifdef CONFIG_TLS_ALIGNED
   /* Make certain that the user provided stack is properly aligned */
 
@@ -103,9 +106,11 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
   /* Save the new stack allocation */
 
   tcb->stack_alloc_ptr = stack;
-  tcb->stack_base_ptr  = tcb->stack_alloc_ptr;
+  tcb->stack_base_ptr  = (void *)STACK_ALIGN_UP((uintptr_t)stack);
-  tcb->adj_stack_size  =
+
-      STACK_ALIGN_DOWN((uintptr_t)stack + stack_size) - (uintptr_t)stack;
+  top_of_stack = STACK_ALIGN_DOWN((uintptr_t)stack + stack_size);
+  size_of_stack = top_of_stack - (uintptr_t)tcb->stack_base_ptr;
+  tcb->adj_stack_size  = size_of_stack;
 
 #ifdef CONFIG_STACK_COLORATION
   /* If stack debug is enabled, then fill the stack with a

arch/arm/src/imxrt/hardware/imxrt_usbotg.h

@@ -121,82 +121,85 @@
 #define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET        0x0800 /* OTG1 Control Register */
 #define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET  0x0818 /* OTG1 Phy Control Register */
 
+#define IMXRT_USBNC_USB_OTG2_CTRL_OFFSET        0x0804 /* OTG1 Control Register */
+#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET  0x081c /* OTG1 Phy Control Register */
+
 /* USBOTG register (virtual) addresses **************************************/
 
 /* Device/host capability registers */
 
-#define IMXRT_USBOTG_HCCR_BASE             (IMXRT_USB_BASE + IMXRT_USBOTG_HCCR_OFFSET)
+#define IMXRT_USBOTG_HCCR_BASE(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_HCCR_OFFSET)
-#define IMXRT_USBOTG_CAPLENGTH             (IMXRT_USB_BASE + IMXRT_USBOTG_CAPLENGTH_OFFSET)
+#define IMXRT_USBOTG_CAPLENGTH(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_CAPLENGTH_OFFSET)
-#define IMXRT_USBHOST_HCIVERSION           (IMXRT_USB_BASE + IMXRT_USBHOST_HCIVERSION_OFFSET)
+#define IMXRT_USBHOST_HCIVERSION(n)           (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_HCIVERSION_OFFSET)
-#define IMXRT_USBHOST_HCSPARAMS            (IMXRT_USB_BASE + IMXRT_USBHOST_HCSPARAMS_OFFSET)
+#define IMXRT_USBHOST_HCSPARAMS(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_HCSPARAMS_OFFSET)
-#define IMXRT_USBHOST_HCCPARAMS            (IMXRT_USB_BASE + IMXRT_USBHOST_HCCPARAMS_OFFSET)
+#define IMXRT_USBHOST_HCCPARAMS(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_HCCPARAMS_OFFSET)
-#define IMXRT_USBDEV_DCIVERSION            (IMXRT_USB_BASE + IMXRT_USBDEV_DCIVERSION_OFFSET)
+#define IMXRT_USBDEV_DCIVERSION(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_DCIVERSION_OFFSET)
-#define IMXRT_USBDEV_DCCPARAMS             (IMXRT_USB_BASE + IMXRT_USBDEV_DCCPARAMS_OFFSET)
+#define IMXRT_USBDEV_DCCPARAMS(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_DCCPARAMS_OFFSET)
 
 /* Device/host operational registers */
 
-#define IMXRT_USBOTG_HCOR_BASE             (IMXRT_USB_BASE + IMXRT_USBOTG_HCOR_OFFSET)
+#define IMXRT_USBOTG_HCOR_BASE(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_HCOR_OFFSET)
-#define IMXRT_USBOTG_USBCMD                (IMXRT_USB_BASE + IMXRT_USBOTG_USBCMD_OFFSET)
+#define IMXRT_USBOTG_USBCMD(n)                (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_USBCMD_OFFSET)
-#define IMXRT_USBOTG_USBSTS                (IMXRT_USB_BASE + IMXRT_USBOTG_USBSTS_OFFSET)
+#define IMXRT_USBOTG_USBSTS(n)                (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_USBSTS_OFFSET)
-#define IMXRT_USBOTG_USBINTR               (IMXRT_USB_BASE + IMXRT_USBOTG_USBINTR_OFFSET)
+#define IMXRT_USBOTG_USBINTR(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_USBINTR_OFFSET)
-#define IMXRT_USBOTG_FRINDEX               (IMXRT_USB_BASE + IMXRT_USBOTG_FRINDEX_OFFSET)
+#define IMXRT_USBOTG_FRINDEX(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_FRINDEX_OFFSET)
-#define IMXRT_USBOTG_PERIODICLIST          (IMXRT_USB_BASE + IMXRT_USBOTG_PERIODICLIST_OFFSET)
+#define IMXRT_USBOTG_PERIODICLIST(n)          (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_PERIODICLIST_OFFSET)
-#define IMXRT_USBOTG_DEVICEADDR            (IMXRT_USB_BASE + IMXRT_USBOTG_DEVICEADDR_OFFSET)
+#define IMXRT_USBOTG_DEVICEADDR(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_DEVICEADDR_OFFSET)
-#define IMXRT_USBOTG_ASYNCLISTADDR         (IMXRT_USB_BASE + IMXRT_USBOTG_ASYNCLISTADDR_OFFSET)
+#define IMXRT_USBOTG_ASYNCLISTADDR(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_ASYNCLISTADDR_OFFSET)
-#define IMXRT_USBOTG_ENDPOINTLIST          (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPOINTLIST_OFFSET)
+#define IMXRT_USBOTG_ENDPOINTLIST(n)          (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_ENDPOINTLIST_OFFSET)
-#define IMXRT_USBOTG_TTCTRL                (IMXRT_USB_BASE + IMXRT_USBOTG_TTCTRL_OFFSET)
+#define IMXRT_USBOTG_TTCTRL(n)                (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_TTCTRL_OFFSET)
-#define IMXRT_USBOTG_BURSTSIZE             (IMXRT_USB_BASE + IMXRT_USBOTG_BURSTSIZE_OFFSET)
+#define IMXRT_USBOTG_BURSTSIZE(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_BURSTSIZE_OFFSET)
-#define IMXRT_USBOTG_TXFILLTUNING          (IMXRT_USB_BASE + IMXRT_USBOTG_TXFILLTUNING_OFFSET)
+#define IMXRT_USBOTG_TXFILLTUNING(n)          (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_TXFILLTUNING_OFFSET)
-#define IMXRT_USBOTG_BINTERVAL             (IMXRT_USB_BASE + IMXRT_USBOTG_BINTERVAL_OFFSET)
+#define IMXRT_USBOTG_BINTERVAL(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_BINTERVAL_OFFSET)
-#define IMXRT_USBOTG_ENDPTNAK              (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAK_OFFSET)
+#define IMXRT_USBOTG_ENDPTNAK(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_ENDPTNAK_OFFSET)
-#define IMXRT_USBOTG_ENDPTNAKEN            (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAKEN_OFFSET)
+#define IMXRT_USBOTG_ENDPTNAKEN(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_ENDPTNAKEN_OFFSET)
-#define IMXRT_USBOTG_PORTSC1               (IMXRT_USB_BASE + IMXRT_USBOTG_PORTSC1_OFFSET)
+#define IMXRT_USBOTG_PORTSC1(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_PORTSC1_OFFSET)
-#define IMXRT_USBOTG_OTGSC                 (IMXRT_USB_BASE + IMXRT_USBOTG_OTGSC_OFFSET)
+#define IMXRT_USBOTG_OTGSC(n)                 (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_OTGSC_OFFSET)
-#define IMXRT_USBOTG_USBMODE               (IMXRT_USB_BASE + IMXRT_USBOTG_USBMODE_OFFSET)
+#define IMXRT_USBOTG_USBMODE(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBOTG_USBMODE_OFFSET)
 
-#define IMXRT_USBDEV_USBCMD                (IMXRT_USB_BASE + IMXRT_USBDEV_USBCMD_OFFSET)
+#define IMXRT_USBDEV_USBCMD(n)                (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_USBCMD_OFFSET)
-#define IMXRT_USBDEV_USBSTS                (IMXRT_USB_BASE + IMXRT_USBDEV_USBSTS_OFFSET)
+#define IMXRT_USBDEV_USBSTS(n)                (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_USBSTS_OFFSET)
-#define IMXRT_USBDEV_USBINTR               (IMXRT_USB_BASE + IMXRT_USBDEV_USBINTR_OFFSET)
+#define IMXRT_USBDEV_USBINTR(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_USBINTR_OFFSET)
-#define IMXRT_USBDEV_FRINDEX               (IMXRT_USB_BASE + IMXRT_USBDEV_FRINDEX_OFFSET)
+#define IMXRT_USBDEV_FRINDEX(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_FRINDEX_OFFSET)
-#define IMXRT_USBDEV_DEVICEADDR            (IMXRT_USB_BASE + IMXRT_USBDEV_DEVICEADDR_OFFSET)
+#define IMXRT_USBDEV_DEVICEADDR(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_DEVICEADDR_OFFSET)
-#define IMXRT_USBDEV_ENDPOINTLIST          (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPOINTLIST_OFFSET)
+#define IMXRT_USBDEV_ENDPOINTLIST(n)          (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPOINTLIST_OFFSET)
-#define IMXRT_USBDEV_BURSTSIZE             (IMXRT_USB_BASE + IMXRT_USBDEV_BURSTSIZE_OFFSET)
+#define IMXRT_USBDEV_BURSTSIZE(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_BURSTSIZE_OFFSET)
-#define IMXRT_USBDEV_BINTERVAL             (IMXRT_USB_BASE + IMXRT_USBDEV_BINTERVAL_OFFSET)
+#define IMXRT_USBDEV_BINTERVAL(n)             (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_BINTERVAL_OFFSET)
-#define IMXRT_USBDEV_ENDPTNAK              (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAK_OFFSET)
+#define IMXRT_USBDEV_ENDPTNAK(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTNAK_OFFSET)
-#define IMXRT_USBDEV_ENDPTNAKEN            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAKEN_OFFSET)
+#define IMXRT_USBDEV_ENDPTNAKEN(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTNAKEN_OFFSET)
-#define IMXRT_USBDEV_PORTSC1               (IMXRT_USB_BASE + IMXRT_USBDEV_PORTSC1_OFFSET)
+#define IMXRT_USBDEV_PORTSC1(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_PORTSC1_OFFSET)
-#define IMXRT_USBDEV_USBMODE               (IMXRT_USB_BASE + IMXRT_USBDEV_USBMODE_OFFSET)
+#define IMXRT_USBDEV_USBMODE(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_USBMODE_OFFSET)
 
-#define IMXRT_USBHOST_USBCMD               (IMXRT_USB_BASE + IMXRT_USBHOST_USBCMD_OFFSET)
+#define IMXRT_USBHOST_USBCMD(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_USBCMD_OFFSET)
-#define IMXRT_USBHOST_USBSTS               (IMXRT_USB_BASE + IMXRT_USBHOST_USBSTS_OFFSET)
+#define IMXRT_USBHOST_USBSTS(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_USBSTS_OFFSET)
-#define IMXRT_USBHOST_USBINTR              (IMXRT_USB_BASE + IMXRT_USBHOST_USBINTR_OFFSET)
+#define IMXRT_USBHOST_USBINTR(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_USBINTR_OFFSET)
-#define IMXRT_USBHOST_FRINDEX              (IMXRT_USB_BASE + IMXRT_USBHOST_FRINDEX_OFFSET)
+#define IMXRT_USBHOST_FRINDEX(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_FRINDEX_OFFSET)
-#define IMXRT_USBHOST_PERIODICLIST         (IMXRT_USB_BASE + IMXRT_USBHOST_PERIODICLIST_OFFSET)
+#define IMXRT_USBHOST_PERIODICLIST(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_PERIODICLIST_OFFSET)
-#define IMXRT_USBHOST_ASYNCLISTADDR        (IMXRT_USB_BASE + IMXRT_USBHOST_ASYNCLISTADDR_OFFSET)
+#define IMXRT_USBHOST_ASYNCLISTADDR(n)        (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_ASYNCLISTADDR_OFFSET)
-#define IMXRT_USBHOST_TTCTRL               (IMXRT_USB_BASE + IMXRT_USBHOST_TTCTRL_OFFSET)
+#define IMXRT_USBHOST_TTCTRL(n)               (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_TTCTRL_OFFSET)
-#define IMXRT_USBHOST_BURSTSIZE            (IMXRT_USB_BASE + IMXRT_USBHOST_BURSTSIZE_OFFSET)
+#define IMXRT_USBHOST_BURSTSIZE(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_BURSTSIZE_OFFSET)
-#define IMXRT_USBHOST_TXFILLTUNING         (IMXRT_USB_BASE + IMXRT_USBHOST_TXFILLTUNING_OFFSET)
+#define IMXRT_USBHOST_TXFILLTUNING(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_TXFILLTUNING_OFFSET)
-#define IMXRT_USBHOST_BINTERVAL            (IMXRT_USB_BASE + IMXRT_USBHOST_BINTERVAL_OFFSET)
+#define IMXRT_USBHOST_BINTERVAL(n)            (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_BINTERVAL_OFFSET)
-#define IMXRT_USBHOST_PORTSC1              (IMXRT_USB_BASE + IMXRT_USBHOST_PORTSC1_OFFSET)
+#define IMXRT_USBHOST_PORTSC1(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_PORTSC1_OFFSET)
-#define IMXRT_USBHOST_USBMODE              (IMXRT_USB_BASE + IMXRT_USBHOST_USBMODE_OFFSET)
+#define IMXRT_USBHOST_USBMODE(n)              (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBHOST_USBMODE_OFFSET)
 
 /* Device endpoint registers */
 
-#define IMXRT_USBDEV_ENDPTSETUPSTAT        (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET)
+#define IMXRT_USBDEV_ENDPTSETUPSTAT(n)     (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET)
-#define IMXRT_USBDEV_ENDPTPRIME            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTPRIME_OFFSET)
+#define IMXRT_USBDEV_ENDPTPRIME(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTPRIME_OFFSET)
-#define IMXRT_USBDEV_ENDPTFLUSH            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTFLUSH_OFFSET)
+#define IMXRT_USBDEV_ENDPTFLUSH(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTFLUSH_OFFSET)
-#define IMXRT_USBDEV_ENDPTSTATUS           (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSTATUS_OFFSET)
+#define IMXRT_USBDEV_ENDPTSTATUS(n)        (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTSTATUS_OFFSET)
-#define IMXRT_USBDEV_ENDPTCOMPLETE         (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET)
+#define IMXRT_USBDEV_ENDPTCOMPLETE(n)      (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET)
 
 #define IMXRT_USBDEV_ENDPTCTRL(n)          (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL_OFFSET(n))
-#define IMXRT_USBDEV_ENDPTCTRL0            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL0_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL0(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL0_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL1            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL1_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL1(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL1_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL2            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL2_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL2(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL2_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL3            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL3_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL3(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL3_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL4            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL4_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL4(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL4_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL5            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL5_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL5(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL5_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL6            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL6_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL6(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL6_OFFSET)
-#define IMXRT_USBDEV_ENDPTCTRL7            (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL7_OFFSET)
+#define IMXRT_USBDEV_ENDPTCTRL7(n)         (IMXRT_USB_BASE + (0x200 * (n)) + IMXRT_USBDEV_ENDPTCTRL7_OFFSET)
 
 /* Device non-core registers */
 
@@ -733,4 +736,16 @@
                                                        /* Bit 30: Reserved */
 #define USBNC_WIR                            (1 << 31) /* Bit 31: Wake up interrupt request */
 
+/* USB VBUS 3.0 Regulator */
+
+#define IMXRT_PMU_REG_3P0                    0x120
+
+#define PMU_REG_3P0_OUTPUT_TRG_SHIFT         (8)
+#define PMU_REG_3P0_OUTPUT_TRG_MASK          (0x1f << PMU_REG_3P0_OUTPUT_TRG_SHIFT)
+#define PMU_REG_3P0_OUTPUT_TRG(x)            (x << PMU_REG_3P0_OUTPUT_TRG_SHIFT)
+
+#define PMU_REG_3P0_ENABLE_LINREG            (1 << 0)
+
+#define IMXRT_USBVBUS_REG_3P0                (IMXRT_ANATOP_BASE + IMXRT_PMU_REG_3P0)
+
 #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H */

arch/arm/src/imxrt/hardware/imxrt_usbphy.h

@@ -34,30 +34,41 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define IMXRT_USBPHY_BASE                   (IMXRT_USBPHY1_BASE)  /* USB PHY Base */
+#define IMXRT_USBPHY_BASE_OFFSET            0x1000  /* USB1 PHY Base */
+
+/* Simple hack to get iMXRT117x working with same macro */
+
+#ifdef CONFIG_ARCH_FAMILY_IMXRT117x
+#  define IMXRT_ANATOP_BASE                 0x40433000 /* ANATOP doesn't exist on rt117x, it is used this way here only to make the code compatible */
+#  define IMXRT_USBPHY_SHIFT                0x4000
+#else
+#  define IMXRT_USBPHY_SHIFT                0x1000
+#endif
+
+#define IMXRT_USBPHY_BASE(n)                (IMXRT_ANATOP_BASE + IMXRT_USBPHY_BASE_OFFSET + (IMXRT_USBPHY_SHIFT * (n)))  /* USB PHY Base */
 
 /* Register Offsets *********************************************************/
 
-#define IMXRT_USBPHY1_PWD_OFFSET            0x0000  /* USBPHY1 USB PHY Power-Down Register */
+#define IMXRT_USBPHY_PWD_OFFSET             0x0000  /* USBPHY1/2 USB PHY Power-Down Register */
-#define IMXRT_USBPHY1_PWD_CLR_OFFSET        0x0008  /* USBPHY1 USB PHY Power-Down Register Clear */
+#define IMXRT_USBPHY_PWD_CLR_OFFSET         0x0008  /* USBPHY1/2 USB PHY Power-Down Register Clear */
-#define IMXRT_USBPHY1_CTRL_OFFSET           0x0030  /* USBPHY1 USB PHY General Control Register */
+#define IMXRT_USBPHY_CTRL_OFFSET            0x0030  /* USBPHY1/2 USB PHY General Control Register */
-#define IMXRT_USBPHY1_CTRL_CLR_OFFSET       0x0038  /* USBPHY1 USB PHY General Control Register Clear */
+#define IMXRT_USBPHY_CTRL_CLR_OFFSET        0x0038  /* USBPHY1/2 USB PHY General Control Register Clear */
 
-#define IMXRT_USBPHY1_PLL_SIC_OFFSET        0x00a0
+#define IMXRT_USBPHY_PLL_SIC_OFFSET         0x00a0
-#define IMXRT_USBPHY1_PLL_SIC_SET_OFFSET    0x00a4
+#define IMXRT_USBPHY_PLL_SIC_SET_OFFSET     0x00a4
-#define IMXRT_USBPHY1_PLL_SIC_CLR_OFFSET    0x00a8
+#define IMXRT_USBPHY_PLL_SIC_CLR_OFFSET     0x00a8
-#define IMXRT_USBPHY1_PLL_SIC_TOG_OFFSET    0x00ac
+#define IMXRT_USBPHY_PLL_SIC_TOG_OFFSET     0x00ac
 
 /* Register addresses *******************************************************/
 
-#define IMXRT_USBPHY1_PWD                   (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_OFFSET)      /* USBPHY1 USB PHY Power-Down Register */
+#define IMXRT_USBPHY_PWD(n)                   (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PWD_OFFSET)      /* USBPHY1 USB PHY Power-Down Register */
-#define IMXRT_USBPHY1_PWD_CLR               (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET)  /* USBPHY1 USB PHY Power-Down Register Clear */
+#define IMXRT_USBPHY_PWD_CLR(n)               (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PWD_CLR_OFFSET)  /* USBPHY1 USB PHY Power-Down Register Clear */
-#define IMXRT_USBPHY1_CTRL                  (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_OFFSET)     /* USBPHY1 USB PHY General Control Register */
+#define IMXRT_USBPHY_CTRL(n)                  (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_CTRL_OFFSET)     /* USBPHY1 USB PHY General Control Register */
-#define IMXRT_USBPHY1_CTRL_CLR              (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */
+#define IMXRT_USBPHY_CTRL_CLR(n)              (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */
-#define IMXRT_USBPHY1_PLL_SIC               (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PLL_SIC_OFFSET)
+#define IMXRT_USBPHY_PLL_SIC(n)               (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PLL_SIC_OFFSET)
-#define IMXRT_USBPHY1_PLL_SIC_SET           (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PLL_SIC_SET_OFFSET)
+#define IMXRT_USBPHY_PLL_SIC_SET(n)           (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PLL_SIC_SET_OFFSET)
-#define IMXRT_USBPHY1_PLL_SIC_CLR           (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PLL_SIC_CLR_OFFSET)
+#define IMXRT_USBPHY_PLL_SIC_CLR(n)           (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PLL_SIC_CLR_OFFSET)
-#define IMXRT_USBPHY1_PLL_SIC_TOG           (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PLL_SIC_TOG_OFFSET)
+#define IMXRT_USBPHY_PLL_SIC_TOG(n)           (IMXRT_USBPHY_BASE(n) + IMXRT_USBPHY_PLL_SIC_TOG_OFFSET)
 
 /* Register Bit Definitions *************************************************/
 
@@ -73,23 +84,52 @@
 
 /* USB PHY General Control Register  */
 
-#define USBPHY_CTRL_SFTRST          (1 << 31)  /* Bit 31: Soft-reset */
+#define USBPHY_CTRL_SFTRST            (1 << 31)  /* Bit 31: Soft-reset */
-#define USBPHY_CTRL_CLKGATE         (1 << 30)  /* Bit 30: Gate UTMI clocks */
+#define USBPHY_CTRL_CLKGATE           (1 << 30)  /* Bit 30: Gate UTMI clocks */
+#define USBPHY_CTRL_UTMI_SUSPENDM     (1 << 29)  /* Bit 29: UTMI suspend DM */
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28)  /* Bit 28: Host force low-speed */
+#define USBPHY_CTRL_OTG_ID_VALUE      (1 << 27)  /* Bit 27: Filter glitches ID pad */
+                                                 /* Bits 26-25: Reserved */
+#define USBPHY_CTRL_FSDLL_RST_EN      (1 << 24)  /* Bit 24: Enable FSDLL logic */
+#define USBPHY_CTRL_ENVBUSCHG_WKUP    (1 << 23)  /* Bit 23: Wakeup if VBUS change when USB is suspended */
+#define USBPHY_CTRL_ENIDCHG_WKUP      (1 << 22)  /* Bit 22: Wakeup if ID change when USB is suspended */
+#define USBPHY_CTRL_ENDPDMCHG_WKUP    (1 << 21)  /* Bit 21: Wakeup if DP/DM change when USB is suspended */
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20)  /* Bit 20: Autoclear PWD bit if there wakeup event when USB is suspended */
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19)  /* Bit 19: Autoclear CLKGATE bit if there wakeup event when USB is suspended */
+#define USBPHY_CTRL_ENAUTO_PWRON_PLL  (1 << 18)  /* Bit 18: Autoclear POWER bit if there wakeup event when USB is suspended */
+#define USBPHY_CTRL_WAKEUP_IRQ        (1 << 17)  /* Bit 17: Indicates there is a wakeup event, reset this bit writing 1 to it */
+#define USBPHY_CTRL_ENIRQWAKEUP       (1 << 16)  /* Bit 16: Enable interrupt for  wakeup event */
+#define USBPHY_CTRL_ENUTMILEVEL3      (1 << 15)  /* Bit 15: Enable UTMI+ Level3 */
+#define USBPHY_CTRL_ENUTMILEVEL2      (1 << 14)  /* Bit 14: Enable UTMI+ Level2 */
+#define USBPHY_CTRL_DATA_ON_LRADC     (1 << 13)  /* Bit 13: Enable LRADC to monitor DP/DM, non-USB modes only */
+#define USBPHY_CTRL_DEVPLUGIN_IRQ     (1 << 12)  /* Bit 12: Enable interrupt for detection activity to the USB line */
+#define USBPHY_CTRL_ENIRQDEVPLUGIN    (1 << 11)  /* Bit 11: Enable interrupt for detection activity to the USB line */
+#define USBPHY_CTRL_RESUME_IRQ        (1 << 10)  /* Bit 10: Indicates to host is sending a wake-up after suspend, write 1 to clear this interrupt */
+#define USBPHY_CTRL_ENIRQRESUMEDET    (1 << 9)   /* Bit 9:  Enable the resume IRQ */
+#define USBPHY_CTRL_RESUMEIRQSTICKY   (1 << 8)   /* Bit 8:  Set 1 to make RESUME IRQ Sticky */
+#define USBPHY_CTRL_ENOTGIDDETECT     (1 << 7)   /* Bit 7:  Enable circuit to detect ID pin */
+#define USBPHY_CTRL_OTG_ID_CHG_IRG    (1 << 6)   /* Bit 6:  OTG ID IRQ, indicates value of ID pin changed */
+#define USBPHY_CTRL_DEVPLUGIN_POL     (1 << 5)   /* Bit 5:  If 0 IRQ when plugged in, if 1 IRQ when plugged out */
+#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4)   /* Bit 4:  Enables 220K ohm pullup to detect host connectivity */
+#define USBPHY_CTRL_HOSTDISCONDET_IRQ (1 << 3)   /* Bit 3:  Indicates the device was disconnected in high-speed mode, write 1 to clear IRQ */
+#define USBPHY_CTRL_ENIRQHOSTDISCON   (1 << 2)   /* Bit 2:  Enable device disconnected IRQ */
+#define USBPHY_CTRL_ENHOSTDISCONDET   (1 << 1)   /* Bit 1:  Enable HighSpeed disconnect detector */
+#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ  (1 << 0)   /* Bit 0:  Enable OTG_ID_CHG_IRQ */
 
 /* USB PHY PLL Control/Status Register (PLL_SIC, only in IMXRT117X) */
-#define USBPHY1_PLL_SIC_PLL_POSTDIV_SHIFT  (2)        /* Bits 2-5: PLL_POSTDIV */
+#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT   (2)        /* Bits 2-5: PLL_POSTDIV */
-#define USBPHY1_PLL_SIC_PLL_POSTDIV_MASK   (0x7 << USBPHY1_PLL_SIC_PLL_POSTDIV_SHIFT)
+#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK    (0x7 << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)
-#define USBPHY1_PLL_SIC_PLL_POSTDIV(n)     (((n) << USBPHY1_PLL_SIC_PLL_POSTDIV_SHIFT) & USBPHY1_PLL_SIC_PLL_POSTDIV_MASK)
+#define USBPHY_PLL_SIC_PLL_POSTDIV(n)      (((n) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
-#define USBPHY1_PLL_SIC_PLL_EN_USB_CLKS    (1 << 6)   /* Bit 6: PLL_EN_USB_CLKS */
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS     (1 << 6)   /* Bit 6: PLL_EN_USB_CLKS */
-#define USBPHY1_PLL_SIC_PLL_POWER          (1 << 12)  /* Bit 12: PLL_POWER */
+#define USBPHY_PLL_SIC_PLL_POWER           (1 << 12)  /* Bit 12: PLL_POWER */
-#define USBPHY1_PLL_SIC_PLL_ENABLE         (1 << 13)  /* Bit 13: PLL_ENABLE */
+#define USBPHY_PLL_SIC_PLL_ENABLE          (1 << 13)  /* Bit 13: PLL_ENABLE */
-#define USBPHY1_PLL_SIC_PLL_BYPASS         (1 << 16)  /* Bit 16: PLL_BYPASS */
+#define USBPHY_PLL_SIC_PLL_BYPASS          (1 << 16)  /* Bit 16: PLL_BYPASS */
-#define USBPHY1_PLL_SIC_REFBIAS_PWD_SEL    (1 << 19)  /* Bit 19: REFBIAS_PWD_SEL */
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL     (1 << 19)  /* Bit 19: REFBIAS_PWD_SEL */
-#define USBPHY1_PLL_SIC_REFBIAS_PWD        (1 << 20)  /* Bit 20: Power down the reference bias */
+#define USBPHY_PLL_SIC_REFBIAS_PWD         (1 << 20)  /* Bit 20: Power down the reference bias */
-#define USBPHY1_PLL_SIC_PLL_REG_ENABLE     (1 << 21)  /* Bit 21: PLL_REG_ENABLE */
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE      (1 << 21)  /* Bit 21: PLL_REG_ENABLE */
-#define USBPHY1_PLL_SIC_PLL_DIV_SEL_SHIFT  (22)       /* Bits 22-25: PLL_DIV_SEL */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT   (22)       /* Bits 22-25: PLL_DIV_SEL */
-#define USBPHY1_PLL_SIC_PLL_DIV_SEL_MASK   (0x7 << USBPHY1_PLL_SIC_PLL_DIV_SEL_SHIFT)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK    (0x7 << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)
-#define USBPHY1_PLL_SIC_PLL_DIV_SEL(n)     (((n) << USBPHY1_PLL_SIC_PLL_DIV_SEL_SHIFT) & USBPHY1_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(n)      (((n) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
-#define USBPHY1_PLL_SIC_PLL_LOCK           (1 << 31)  /* Bit 31: PLL_LOCK */
+#define USBPHY_PLL_SIC_PLL_LOCK            (1 << 31)  /* Bit 31: PLL_LOCK */
 
 #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBPHY_H */

arch/arm/src/imxrt/imxrt_ehci.h

@@ -76,7 +76,7 @@ extern "C"
  *
  ****************************************************************************/
 
-extern void imxrt_usbhost_vbusdrive(int rhport, bool enable);
+extern void imxrt_usbhost_vbusdrive(int ctrid, int rhport, bool enable);
 
 /****************************************************************************
  * Name: imxrt_setup_overcurrent

arch/arm/src/imxrt/imxrt_usbdev.c

@@ -791,9 +791,9 @@ static void imxrt_queuedtd(uint8_t epphy, struct imxrt_dtd_s *dtd)
 
   uint32_t bit = IMXRT_ENDPTMASK(epphy);
 
-  imxrt_setbits(bit, IMXRT_USBDEV_ENDPTPRIME);
+  imxrt_setbits(bit, IMXRT_USBDEV_ENDPTPRIME(0));
 
-  while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME) & bit)
+  while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME(0)) & bit)
     ;
 }
 
@@ -832,7 +832,7 @@ static void imxrt_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl)
     {
       /* Set the trip wire */
 
-      imxrt_setbits(USBDEV_USBCMD_SUTW, IMXRT_USBDEV_USBCMD);
+      imxrt_setbits(USBDEV_USBCMD_SUTW, IMXRT_USBDEV_USBCMD(0));
 
       up_invalidate_dcache((uintptr_t)dqh,
                            (uintptr_t)dqh + sizeof(struct imxrt_dqh_s));
@@ -844,15 +844,16 @@ static void imxrt_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl)
           ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i];
         }
     }
-  while (!(imxrt_getreg(IMXRT_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW));
+  while (!(imxrt_getreg(IMXRT_USBDEV_USBCMD(0)) & USBDEV_USBCMD_SUTW));
 
   /* Clear the trip wire */
 
-  imxrt_clrbits(USBDEV_USBCMD_SUTW, IMXRT_USBDEV_USBCMD);
+  imxrt_clrbits(USBDEV_USBCMD_SUTW, IMXRT_USBDEV_USBCMD(0));
 
   /* Clear the Setup Interrupt */
 
-  imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT), IMXRT_USBDEV_ENDPTSETUPSTAT);
+  imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT),
+               IMXRT_USBDEV_ENDPTSETUPSTAT(0));
 }
 
 /****************************************************************************
@@ -871,7 +872,7 @@ static inline void imxrt_set_address(struct imxrt_usbdev_s *priv,
 
   imxrt_chgbits(USBDEV_DEVICEADDR_MASK,
                 priv->paddr << USBDEV_DEVICEADDR_SHIFT,
-                IMXRT_USBDEV_DEVICEADDR);
+                IMXRT_USBDEV_DEVICEADDR(0));
 }
 
 /****************************************************************************
@@ -887,11 +888,11 @@ static void imxrt_flushep(struct imxrt_ep_s *privep)
   uint32_t mask = IMXRT_ENDPTMASK(privep->epphy);
   do
     {
-      imxrt_putreg(mask, IMXRT_USBDEV_ENDPTFLUSH);
+      imxrt_putreg(mask, IMXRT_USBDEV_ENDPTFLUSH(0));
-      while ((imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH) & mask) != 0)
+      while ((imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH(0)) & mask) != 0)
       ;
     }
-  while ((imxrt_getreg(IMXRT_USBDEV_ENDPTSTATUS) & mask) != 0);
+  while ((imxrt_getreg(IMXRT_USBDEV_ENDPTSTATUS(0)) & mask) != 0);
 }
 
 /****************************************************************************
@@ -1138,7 +1139,7 @@ static void imxrt_ep0configure(struct imxrt_usbdev_s *priv)
   /* Enable EP0 */
 
   imxrt_setbits(USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE,
-                IMXRT_USBDEV_ENDPTCTRL0);
+                IMXRT_USBDEV_ENDPTCTRL0(0));
 }
 
 /****************************************************************************
@@ -1156,33 +1157,33 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv)
   /* Disable all endpoints. Control endpoint 0 is always enabled */
 
   imxrt_clrbits(USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE,
-                IMXRT_USBDEV_ENDPTCTRL1);
+                IMXRT_USBDEV_ENDPTCTRL1(0));
   imxrt_clrbits(USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE,
-                IMXRT_USBDEV_ENDPTCTRL2);
+                IMXRT_USBDEV_ENDPTCTRL2(0));
   imxrt_clrbits(USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE,
-                IMXRT_USBDEV_ENDPTCTRL3);
+                IMXRT_USBDEV_ENDPTCTRL3(0));
   imxrt_clrbits(USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE,
-                IMXRT_USBDEV_ENDPTCTRL4);
+                IMXRT_USBDEV_ENDPTCTRL4(0));
   imxrt_clrbits(USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE,
-                IMXRT_USBDEV_ENDPTCTRL5);
+                IMXRT_USBDEV_ENDPTCTRL5(0));
 
   /* Clear all pending interrupts */
 
-  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTNAK),
+  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTNAK(0)),
-               IMXRT_USBDEV_ENDPTNAK);
+               IMXRT_USBDEV_ENDPTNAK(0));
-  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT),
+  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT(0)),
-               IMXRT_USBDEV_ENDPTSETUPSTAT);
+               IMXRT_USBDEV_ENDPTSETUPSTAT(0));
-  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTCOMPLETE),
+  imxrt_putreg(imxrt_getreg(IMXRT_USBDEV_ENDPTCOMPLETE(0)),
-               IMXRT_USBDEV_ENDPTCOMPLETE);
+               IMXRT_USBDEV_ENDPTCOMPLETE(0));
 
   /* Wait for all prime operations to have completed and then flush all
    * DTDs
    */
 
-  while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME) != 0)
+  while (imxrt_getreg(IMXRT_USBDEV_ENDPTPRIME(0)) != 0)
     ;
-  imxrt_putreg(IMXRT_ENDPTMASK_ALL, IMXRT_USBDEV_ENDPTFLUSH);
+  imxrt_putreg(IMXRT_ENDPTMASK_ALL, IMXRT_USBDEV_ENDPTFLUSH(0));
-  while (imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH))
+  while (imxrt_getreg(IMXRT_USBDEV_ENDPTFLUSH(0)))
     ;
 
   /* Reset endpoints */
@@ -1210,7 +1211,7 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv)
   /* Set the interrupt Threshold control interval to 0 */
 
   imxrt_chgbits(USBDEV_USBCMD_ITC_MASK, USBDEV_USBCMD_ITCIMME,
-                IMXRT_USBDEV_USBCMD);
+                IMXRT_USBDEV_USBCMD(0));
 
   /* Zero out the Endpoint queue heads */
 
@@ -1226,7 +1227,7 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv)
 
   /* Initialise the Endpoint List Address */
 
-  imxrt_putreg((uint32_t)g_qh, IMXRT_USBDEV_ENDPOINTLIST);
+  imxrt_putreg((uint32_t)g_qh, IMXRT_USBDEV_ENDPOINTLIST(0));
 
   /* EndPoint 0 initialization */
 
@@ -1236,7 +1237,7 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv)
 
   imxrt_putreg(USB_FRAME_INT | USB_ERROR_INT | USBDEV_USBINTR_NAKE |
                USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE |
-               USBDEV_USBINTR_UE, IMXRT_USBDEV_USBINTR);
+               USBDEV_USBINTR_UE, IMXRT_USBDEV_USBINTR(0));
 }
 
 /****************************************************************************
@@ -1255,15 +1256,17 @@ static inline void imxrt_ep0state(struct imxrt_usbdev_s *priv,
   switch (state)
     {
     case EP0STATE_WAIT_NAK_IN:
-      imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN), IMXRT_USBDEV_ENDPTNAKEN);
+      imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN),
+                   IMXRT_USBDEV_ENDPTNAKEN(0));
       break;
 
     case EP0STATE_WAIT_NAK_OUT:
-      imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT), IMXRT_USBDEV_ENDPTNAKEN);
+      imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_OUT),
+                   IMXRT_USBDEV_ENDPTNAKEN(0));
       break;
 
     default:
-      imxrt_putreg(0, IMXRT_USBDEV_ENDPTNAKEN);
+      imxrt_putreg(0, IMXRT_USBDEV_ENDPTNAKEN(0));
       break;
     }
 }
@@ -1920,8 +1923,8 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
   /* Read the interrupts and then clear them */
 
-  disr = imxrt_getreg(IMXRT_USBDEV_USBSTS);
+  disr = imxrt_getreg(IMXRT_USBDEV_USBSTS(0));
-  imxrt_putreg(disr, IMXRT_USBDEV_USBSTS);
+  imxrt_putreg(disr, IMXRT_USBDEV_USBSTS(0));
 
   if (disr & USBDEV_USBSTS_URI)
     {
@@ -1973,7 +1976,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
   if (disr & USBDEV_USBSTS_PCI)
     {
-      portsc1 = imxrt_getreg(IMXRT_USBDEV_PORTSC1);
+      portsc1 = imxrt_getreg(IMXRT_USBDEV_PORTSC1(0));
 
       if (portsc1 & USBDEV_PRTSC1_HSP)
         priv->usbdev.speed = USB_SPEED_HIGH;
@@ -1996,7 +1999,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
     {
       usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_FRAME), 0);
 
-      uint32_t frindex = imxrt_getreg(IMXRT_USBDEV_FRINDEX);
+      uint32_t frindex = imxrt_getreg(IMXRT_USBDEV_FRINDEX(0));
       uint16_t frame_num =
           (frindex & USBDEV_FRINDEX_LFN_MASK) >> USBDEV_FRINDEX_LFN_SHIFT;
 
@@ -2016,14 +2019,14 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
     {
       /* Handle completion interrupts */
 
-      uint32_t mask = imxrt_getreg(IMXRT_USBDEV_ENDPTCOMPLETE);
+      uint32_t mask = imxrt_getreg(IMXRT_USBDEV_ENDPTCOMPLETE(0));
 
       if (mask)
         {
           /* Clear any NAK interrupt and completion interrupts */
 
-          imxrt_putreg(mask, IMXRT_USBDEV_ENDPTNAK);
+          imxrt_putreg(mask, IMXRT_USBDEV_ENDPTNAK(0));
-          imxrt_putreg(mask, IMXRT_USBDEV_ENDPTCOMPLETE);
+          imxrt_putreg(mask, IMXRT_USBDEV_ENDPTCOMPLETE(0));
 
           if (mask & IMXRT_ENDPTMASK(0))
             {
@@ -2051,7 +2054,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
       /* Handle setup interrupts */
 
-      uint32_t setupstat = imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT);
+      uint32_t setupstat = imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT(0));
       if (setupstat)
         {
           /* Clear the endpoint complete CTRL OUT and IN when a Setup is
@@ -2060,7 +2063,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
           imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN) |
                        IMXRT_ENDPTMASK(IMXRT_EP0_OUT),
-                       IMXRT_USBDEV_ENDPTCOMPLETE);
+                       IMXRT_USBDEV_ENDPTCOMPLETE(0));
 
           if (setupstat & IMXRT_ENDPTMASK(IMXRT_EP0_OUT))
             {
@@ -2073,8 +2076,8 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
   if (disr & USBDEV_USBSTS_NAKI)
     {
-      uint32_t pending = imxrt_getreg(IMXRT_USBDEV_ENDPTNAK) &
+      uint32_t pending = imxrt_getreg(IMXRT_USBDEV_ENDPTNAK(0)) &
-          imxrt_getreg(IMXRT_USBDEV_ENDPTNAKEN);
+          imxrt_getreg(IMXRT_USBDEV_ENDPTNAKEN(0));
       if (pending)
         {
           /* We shouldn't see NAK interrupts except on Endpoint 0 */
@@ -2092,7 +2095,7 @@ static int imxrt_usbinterrupt(int irq, void *context, void *arg)
 
       /* Clear the interrupts */
 
-      imxrt_putreg(pending, IMXRT_USBDEV_ENDPTNAK);
+      imxrt_putreg(pending, IMXRT_USBDEV_ENDPTNAK(0));
     }
 
   usbtrace(TRACE_INTEXIT(IMXRT_TRACEINTID_USB), 0);
@@ -2708,7 +2711,7 @@ static int imxrt_getframe(struct usbdev_s *dev)
   usbtrace(TRACE_DEVGETFRAME, (uint16_t)priv->sof);
   return priv->sof;
 #else
-  uint32_t frindex = imxrt_getreg(IMXRT_USBDEV_FRINDEX);
+  uint32_t frindex = imxrt_getreg(IMXRT_USBDEV_FRINDEX(0));
   uint16_t frame_num =
       (frindex & USBDEV_FRINDEX_LFN_MASK) >> USBDEV_FRINDEX_LFN_SHIFT;
 
@@ -2735,7 +2738,7 @@ static int imxrt_wakeup(struct usbdev_s *dev)
   usbtrace(TRACE_DEVWAKEUP, 0);
 
   flags = enter_critical_section();
-  imxrt_setbits(USBDEV_PRTSC1_FPR, IMXRT_USBDEV_PORTSC1);
+  imxrt_setbits(USBDEV_PRTSC1_FPR, IMXRT_USBDEV_PORTSC1(0));
   leave_critical_section(flags);
   return OK;
 }
@@ -2781,7 +2784,7 @@ static int imxrt_pullup(struct usbdev_s *dev, bool enable)
   irqstate_t flags = enter_critical_section();
   if (enable)
     {
-      imxrt_setbits(USBDEV_USBCMD_RS, IMXRT_USBDEV_USBCMD);
+      imxrt_setbits(USBDEV_USBCMD_RS, IMXRT_USBDEV_USBCMD(0));
 
 #ifdef CONFIG_IMXRT_USB0DEV_NOVBUS
       /* Create a 'false' power event on the USB port so the MAC connects */
@@ -2792,7 +2795,7 @@ static int imxrt_pullup(struct usbdev_s *dev, bool enable)
     }
   else
     {
-      imxrt_clrbits(USBDEV_USBCMD_RS, IMXRT_USBDEV_USBCMD);
+      imxrt_clrbits(USBDEV_USBCMD_RS, IMXRT_USBDEV_USBCMD(0));
     }
 
   leave_critical_section(flags);
@@ -2888,36 +2891,37 @@ void arm_usbinitialize(void)
 #ifdef CONFIG_ARCH_FAMILY_IMXRT117x
   up_mdelay(1);
 
-  putreg32(USBPHY1_PLL_SIC_PLL_POWER |
+  putreg32(USBPHY_PLL_SIC_PLL_POWER |
-           USBPHY1_PLL_SIC_PLL_REG_ENABLE,
+           USBPHY_PLL_SIC_PLL_REG_ENABLE,
-           IMXRT_USBPHY1_PLL_SIC_SET);
+           IMXRT_USBPHY_PLL_SIC_SET(0));
 
-  putreg32(USBPHY1_PLL_SIC_PLL_DIV_SEL_MASK,
+  putreg32(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK,
-           IMXRT_USBPHY1_PLL_SIC_CLR);
+           IMXRT_USBPHY_PLL_SIC_CLR(0));
 
-  putreg32(USBPHY1_PLL_SIC_PLL_DIV_SEL(3),
+  putreg32(USBPHY_PLL_SIC_PLL_DIV_SEL(3),
-           IMXRT_USBPHY1_PLL_SIC_SET);
+           IMXRT_USBPHY_PLL_SIC_SET(0));
 
-  putreg32(USBPHY1_PLL_SIC_PLL_BYPASS,
+  putreg32(USBPHY_PLL_SIC_PLL_BYPASS,
-           IMXRT_USBPHY1_PLL_SIC_CLR);
+           IMXRT_USBPHY_PLL_SIC_CLR(0));
 
-  putreg32(USBPHY1_PLL_SIC_PLL_EN_USB_CLKS,
+  putreg32(USBPHY_PLL_SIC_PLL_EN_USB_CLKS,
-           IMXRT_USBPHY1_PLL_SIC_SET);
+           IMXRT_USBPHY_PLL_SIC_SET(0));
 
   putreg32(USBPHY_CTRL_CLKGATE,
-           IMXRT_USBPHY1_CTRL_CLR);
+           IMXRT_USBPHY_CTRL_CLR(0));
 
-  while ((getreg32(IMXRT_USBPHY1_PLL_SIC) & USBPHY1_PLL_SIC_PLL_LOCK) == 0);
+  while ((getreg32(IMXRT_USBPHY_PLL_SIC(0)) & USBPHY_PLL_SIC_PLL_LOCK) == 0);
 
 #endif
 
   /* Disable USB interrupts */
 
-  imxrt_putreg(0, IMXRT_USBDEV_USBINTR);
+  imxrt_putreg(0, IMXRT_USBDEV_USBINTR(0));
 
   /* Soft reset PHY and enable clock */
 
-  putreg32(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, IMXRT_USBPHY1_CTRL_CLR);
+  putreg32(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
+           IMXRT_USBPHY_CTRL_CLR(0));
 
   /* Disconnect device */
 
@@ -2925,8 +2929,8 @@ void arm_usbinitialize(void)
 
   /* Reset the controller */
 
-  imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD);
+  imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD(0));
-  while (imxrt_getreg(IMXRT_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
+  while (imxrt_getreg(IMXRT_USBDEV_USBCMD(0)) & USBDEV_USBCMD_RST)
       ;
 
   /* Power up the PHY (turn off power disable) - USBPHYx_PWDn
@@ -2936,12 +2940,12 @@ void arm_usbinitialize(void)
    * CCM_ANALOG_USBPHYx_PLL_480_CTRLn.
    */
 
-  imxrt_putreg(0, IMXRT_USBPHY1_PWD);
+  imxrt_putreg(0, IMXRT_USBPHY_PWD(0));
 
   /* Program the controller to be the USB device controller */
 
   imxrt_putreg(USBDEV_USBMODE_SDIS | USBDEV_USBMODE_SLOM |
-                USBDEV_USBMODE_CM_DEVICE, IMXRT_USBDEV_USBMODE);
+                USBDEV_USBMODE_CM_DEVICE, IMXRT_USBDEV_USBMODE(0));
 
   /* Attach USB controller interrupt handler */
 
@@ -2986,15 +2990,15 @@ void arm_usbuninitialize(void)
 
   /* Reset the controller */
 
-  imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD);
+  imxrt_setbits(USBDEV_USBCMD_RST, IMXRT_USBDEV_USBCMD(0));
-  while (imxrt_getreg(IMXRT_USBDEV_USBCMD) & USBDEV_USBCMD_RST)
+  while (imxrt_getreg(IMXRT_USBDEV_USBCMD(0)) & USBDEV_USBCMD_RST)
       ;
 
   /* Turn off USB power and clocking */
 
   /* Power down the PHY */
 
-  imxrt_putreg(0xffffffff, IMXRT_USBPHY1_PWD);
+  imxrt_putreg(0xffffffff, IMXRT_USBPHY_PWD(0));
 
   /* Stop clock
    * NOTE: This will interfere with USB OTG 2 and should probably be removed

arch/arm/src/rp2040/.gitignore

@@ -0,0 +1 @@
+rp2040_boot_stage2.S

arch/arm/src/rp2040/CMakeLists.txt

@@ -0,0 +1,123 @@
+# ##############################################################################
+# arch/arm/src/rp2040/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+list(
+  APPEND
+  SRCS
+  rp2040_idle.c
+  rp2040_irq.c
+  rp2040_uart.c
+  rp2040_serial.c
+  rp2040_start.c
+  rp2040_timerisr.c
+  rp2040_gpio.c
+  rp2040_pio.c
+  rp2040_clock.c
+  rp2040_xosc.c
+  rp2040_pll.c)
+
+if(CONFIG_SMP)
+  list(APPEND SRCS rp2040_cpustart.c rp2040_smpcall.c rp2040_cpuidlestack.c
+       rp2040_testset.c)
+endif()
+
+if(CONFIG_ARCH_HAVE_MULTICPU)
+  list(APPEND SRCS rp2040_cpuindex.c)
+endif()
+
+if(CONFIG_RP2040_DMAC)
+  list(APPEND SRCS rp2040_dmac.c)
+endif()
+
+if(CONFIG_RP2040_SPI)
+  list(APPEND SRCS rp2040_spi.c)
+endif()
+
+if(CONFIG_RP2040_PWM)
+  list(APPEND SRCS rp2040_pwm.c)
+endif()
+
+if(CONFIG_RP2040_I2C)
+  list(APPEND SRCS rp2040_i2c.c)
+endif()
+
+if(CONFIG_RP2040_I2C_SLAVE)
+  list(APPEND SRCS rp2040_i2c_slave.c)
+endif()
+
+if(CONFIG_RP2040_I2S)
+  list(APPEND SRCS rp2040_i2s.c rp2040_i2s_pio.c)
+endif()
+
+if(CONFIG_USBDEV)
+  list(APPEND SRCS rp2040_usbdev.c)
+endif()
+
+if(CONFIG_WS2812)
+  list(APPEND SRCS rp2040_ws2812.c)
+endif()
+
+if(CONFIG_ADC)
+  list(APPEND SRCS rp2040_adc.c)
+endif()
+
+if(CONFIG_IEEE80211_INFINEON_CYW43439)
+  list(APPEND SRCS rp2040_cyw43439.c)
+endif()
+
+if(CONFIG_WATCHDOG)
+  list(APPEND SRCS rp2040_wdt.c)
+endif()
+
+if(CONFIG_RP2040_FLASH_FILE_SYSTEM)
+  list(APPEND SRCS rp2040_flash_mtd.c rp2040_flash_initialize.S)
+endif()
+
+if(CONFIG_RP2040_FLASH_BOOT)
+
+  # Set the Pico SDK path using the environment variable
+
+  if(NOT DEFINED ENV{PICO_SDK_PATH})
+    message(
+      FATAL_ERROR
+        "PICO_SDK_PATH environment variable is not set. Please set it to the path of your Pico SDK installation."
+    )
+  else()
+    message(STATUS "PICO_SDK_PATH environment variable is set.")
+
+    set(PICO_SDK_PATH $ENV{PICO_SDK_PATH})
+    include(${CMAKE_CURRENT_SOURCE_DIR}/boot2/rp2040_boot_stage2.cmake)
+
+    set(PATH_CHIP_RP2040 ${CMAKE_BINARY_DIR}/arch/${CONFIG_ARCH}/src/chip)
+    pico_define_boot_stage2(rp2040_boot_stage2 ${PATH_CHIP_RP2040})
+
+    if(EXISTS ${PATH_CHIP_RP2040}/rp2040_boot_stage2.S)
+      list(APPEND SRCS ${PATH_CHIP_RP2040}/rp2040_boot_stage2.S)
+      target_sources(nuttx PRIVATE ${PATH_CHIP_RP2040}/rp2040_boot_stage2.S)
+    else()
+      message(
+        FATAL_ERROR "No rp2040_boot_stage2.S found at ${PATH_CHIP_RP2040}")
+    endif()
+  endif()
+endif()
+
+target_sources(arch PRIVATE ${SRCS})

arch/arm/src/rp2040/boot2/rp2040_boot_stage2.cmake

@@ -0,0 +1,113 @@
+# ##############################################################################
+# arch/arm/src/rp2040/boot2/rp2040_boot_stage2.cmake
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+# ~~~
+# pico_define_boot_stage2
+#
+# Description: Define a boot stage 2 for the Raspberry Pi rp2040.
+#
+# Parameters:
+#  NAME        : The name of the boot stage 2
+#  path_chip   : The full path of the CMake build /${CONFIG_ARCH}/src/chip
+# ~~~
+
+function(pico_define_boot_stage2 NAME path_chip)
+
+  set(PICO_BOOT_STAGE2_DIR "${PICO_SDK_PATH}/src/rp2040/boot_stage2")
+  set(BOOT2SRC "${PICO_BOOT_STAGE2_DIR}/boot2_${CONFIG_RP2040_FLASH_CHIP}.S")
+
+  string(REPLACE "." "-" NUTTX_BOARD_NAME "${NUTTX_BOARD}")
+
+  set(BOOT2CFLAGSLIST
+      "-T${NUTTX_BOARD_DIR}/scripts/${NUTTX_BOARD_NAME}-flash.ld"
+      -DPICO_BOARD=\"pico\" -DPICO_BUILD=1 -DPICO_NO_HARDWARE=0
+      -DPICO_ON_DEVICE=1)
+
+  list(APPEND BOOT2CFLAGSLIST -I${path_chip}/boot2)
+  list(APPEND BOOT2CFLAGSLIST -I${PICO_BOOT_STAGE2_DIR}/asminclude)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2040/hardware_regs/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2_common/hardware_base/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/common/pico_base_headers/include)
+  list(APPEND BOOT2CFLAGSLIST -I${PICO_SDK_PATH}/src/boards/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2040/pico_platform/include)
+
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2_common/pico_platform_common/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2_common/pico_platform_compiler/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2_common/pico_platform_sections/include)
+  list(APPEND BOOT2CFLAGSLIST
+       -I${PICO_SDK_PATH}/src/rp2_common/pico_platform_panic/include)
+  list(APPEND BOOT2CFLAGSLIST -Wl,--no-warn-rwx-segments)
+
+  string(REPLACE ";" " " BOOT2CFLAGS "${BOOT2CFLAGSLIST}")
+
+  set(ORIGINAL_ELF ${path_chip}/${NAME}.elf)
+
+  execute_process(
+    COMMAND ${CMAKE_COMMAND} -E touch
+            ${PICO_SDK_PATH}/src/common/pico_base_headers/include/pico/version.h
+  )
+  execute_process(
+    COMMAND
+      ${CMAKE_COMMAND} -E touch
+      ${PICO_SDK_PATH}/src/common/pico_base_headers/include/pico/config_autogen.h
+  )
+
+  set(builtin
+      "${CMAKE_C_COMPILER} -nostdlib ${BOOT2CFLAGS} -o ${ORIGINAL_ELF} ${BOOT2SRC}"
+  )
+
+  if(CMAKE_HOST_SYSTEM_NAME MATCHES "Windows")
+    execute_process(COMMAND cmd /c "${builtin}" RESULT_VARIABLE resultVar)
+  else()
+    execute_process(COMMAND sh -c "${builtin}" RESULT_VARIABLE resultVar)
+  endif()
+
+  execute_process(
+    COMMAND ${CMAKE_COMMAND} -E remove -f
+            ${PICO_SDK_PATH}/src/common/pico_base_headers/include/pico/version.h
+  )
+  execute_process(
+    COMMAND
+      ${CMAKE_COMMAND} -E remove -f
+      ${PICO_SDK_PATH}/src/common/pico_base_headers/include/pico/config_autogen.h
+  )
+
+  if(resultVar AND NOT resultVar EQUAL 0)
+    message(FATAL_ERROR "Failed: ${resultVar}")
+  else()
+    set(ORIGINAL_BIN ${path_chip}/${NAME}.bin)
+    set(PADDED_CHECKSUMMED_ASM ${path_chip}/${NAME}.S)
+
+    execute_process(COMMAND ${CMAKE_OBJCOPY} -Obinary ${ORIGINAL_ELF}
+                            ${ORIGINAL_BIN})
+    execute_process(
+      COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s
+              0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM})
+  endif()
+endfunction()

arch/arm/src/rp2040/hardware/rp2040_address_mapped.h

@@ -0,0 +1,69 @@
+/****************************************************************************
+ * arch/arm/src/rp2040/hardware/rp2040_address_mapped.h
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * SPDX-FileCopyrightText: 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ADDRESS_MAPPED_H
+#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ADDRESS_MAPPED_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define REG_ALIAS_XOR_BITS (0x1u << 12u)
+#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
+#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+always_inline_function static void hw_xor_bits(volatile uint32_t *addr,
+  uint32_t mask)
+{
+    *(volatile uint32_t *)hw_xor_alias_untyped((volatile void *)addr) = mask;
+}
+
+always_inline_function static void hw_write_masked(volatile uint32_t *addr,
+  uint32_t values, uint32_t write_mask)
+{
+    hw_xor_bits(addr, (*addr ^ values) & write_mask);
+}
+
+#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_ADDRESS_MAPPED_H */

arch/arm/src/rp2040/rp2040_gpio.h

@@ -34,6 +34,7 @@
 #include <debug.h>
 
 #include "hardware/rp2040_sio.h"
+#include "hardware/rp2040_address_mapped.h"
 #include "hardware/rp2040_io_bank0.h"
 #include "hardware/rp2040_pads_bank0.h"
 
@@ -43,10 +44,6 @@
 
 #define RP2040_GPIO_NUM    30       /* Number of GPIO pins */
 
-#define REG_ALIAS_XOR_BITS (0x1u << 12u)
-#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
-#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
-
 /* GPIO function types ******************************************************/
 
 #define RP2040_GPIO_FUNC_JTAG       RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_JTAG
@@ -200,17 +197,6 @@ static inline void rp2040_gpio_set_drive_strength(uint32_t gpio,
                 RP2040_PADS_BANK0_GPIO(gpio));
 }
 
-always_inline_function static void hw_xor_bits(uint32_t *addr, uint32_t mask)
-{
-    *(uint32_t *) hw_xor_alias_untyped((volatile void *)addr) = mask;
-}
-
-always_inline_function static void hw_write_masked(uint32_t *addr,
-  uint32_t values, uint32_t write_mask)
-{
-    hw_xor_bits(addr, (*addr ^ values) & write_mask);
-}
-
 /****************************************************************************
  * Name: rp2040_gpio_set_outover
  *

arch/arm/src/rp23xx/CMakeLists.txt

@@ -0,0 +1,88 @@
+# ##############################################################################
+# arch/arm/src/rp23xx/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+list(
+  APPEND
+  SRCS
+  rp23xx_idle.c
+  rp23xx_irq.c
+  rp23xx_uart.c
+  rp23xx_serial.c
+  rp23xx_start.c
+  rp23xx_timerisr.c
+  rp23xx_gpio.c
+  rp23xx_pio.c
+  rp23xx_clock.c
+  rp23xx_xosc.c
+  rp23xx_pll.c)
+
+if(CONFIG_SMP)
+  list(APPEND SRCS rp23xx_cpustart.c rp23xx_smpcall.c rp23xx_cpuidlestack.c
+       rp23xx_testset.c)
+endif()
+
+if(CONFIG_ARCH_HAVE_MULTICPU)
+  list(APPEND SRCS rp23xx_cpuindex.c)
+endif()
+
+if(CONFIG_RP23XX_DMAC)
+  list(APPEND SRCS rp23xx_dmac.c)
+endif()
+
+if(CONFIG_RP23XX_SPI)
+  list(APPEND SRCS rp23xx_spi.c)
+endif()
+
+if(CONFIG_RP23XX_PWM)
+  list(APPEND SRCS rp23xx_pwm.c)
+endif()
+
+if(CONFIG_RP23XX_I2C)
+  list(APPEND SRCS rp23xx_i2c.c)
+endif()
+
+if(CONFIG_RP23XX_I2C_SLAVE)
+  list(APPEND SRCS rp23xx_i2c_slave.c)
+endif()
+
+if(CONFIG_RP23XX_I2S)
+  list(APPEND SRCS rp23xx_i2s.c)
+  list(APPEND SRCS rp23xx_i2s_pio.c)
+endif()
+
+if(CONFIG_USBDEV)
+  list(APPEND SRCS rp23xx_usbdev.c)
+endif()
+
+if(CONFIG_WS2812)
+  list(APPEND SRCS rp23xx_ws2812.c)
+endif()
+
+if(CONFIG_ADC)
+  list(APPEND SRCS rp23xx_adc.c)
+endif()
+
+if(CONFIG_WATCHDOG)
+  list(APPEND SRCS rp23xx_wdt.c)
+endif()
+
+target_sources(arch PRIVATE ${SRCS})

arch/arm/src/samv7/Kconfig

@@ -217,6 +217,8 @@ config ARCH_CHIP_SAME70J
 	select SAMV7_QSPI_IS_SPI
 	select SAMV7_HAVE_USBFS
 	select SAMV7_HAVE_ISI8
+	select SAMV7_HAVE_USART0
+	select SAMV7_HAVE_USART1
 
 config ARCH_CHIP_SAMV71
 	bool
@@ -269,6 +271,8 @@ config ARCH_CHIP_SAMV71J
 	select SAMV7_QSPI_IS_SPI
 	select SAMV7_HAVE_USBFS
 	select SAMV7_HAVE_ISI8
+	select SAMV7_HAVE_USART0
+	select SAMV7_HAVE_USART1
 
 config ARCH_CHIP_PIC32CZCA70
 	bool

arch/arm/src/stm32f0l0g0/Kconfig

@@ -909,166 +909,207 @@ config ARCH_CHIP_STM32L073RZ
 config ARCH_CHIP_STM32C051D8
 	bool "STM32C051D8"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C051F6
 	bool "STM32C051F6"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_6
 
 config ARCH_CHIP_STM32C051F8
 	bool "STM32C051F8"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C051G6
 	bool "STM32C051G6"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_6
 
 config ARCH_CHIP_STM32C051G8
 	bool "STM32C051G8"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C051K6
 	bool "STM32C051K6"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_6
 
 config ARCH_CHIP_STM32C051K8
 	bool "STM32C051K8"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C051C6
 	bool "STM32C051C6"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_6
 
 config ARCH_CHIP_STM32C051C8
 	bool "STM32C051C8"
 	select ARCH_CHIP_STM32C051XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071F8
 	bool "STM32C071F8"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071FB
 	bool "STM32C071FB"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C071G8
 	bool "STM32C071G8"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071GB
 	bool "STM32C071GB"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C071K8
 	bool "STM32C071K8"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071KB
 	bool "STM32C071KB"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C071C8
 	bool "STM32C071C8"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071CB
 	bool "STM32C071CB"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C071R8
 	bool "STM32C071R8"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_8
 
 config ARCH_CHIP_STM32C071RB
 	bool "STM32C071RB"
 	select ARCH_CHIP_STM32C071XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091FB
 	bool "STM32C091FB"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091FC
 	bool "STM32C091FC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C091EC
 	bool "STM32C091EC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C091GB
 	bool "STM32C091GB"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091GC
 	bool "STM32C091GC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C091KB
 	bool "STM32C091KB"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091KC
 	bool "STM32C091KC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C091CB
 	bool "STM32C091CB"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091CC
 	bool "STM32C091CC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C091RB
 	bool "STM32C091RB"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C091RC
 	bool "STM32C091RC"
 	select ARCH_CHIP_STM32C091XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092FB
 	bool "STM32C092FB"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C092FC
 	bool "STM32C092FC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092EC
 	bool "STM32C092EC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092GB
 	bool "STM32C092GB"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C092GC
 	bool "STM32C092GC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092KB
 	bool "STM32C092KB"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C092KC
 	bool "STM32C092KC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092CB
 	bool "STM32C092CB"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C092CC
 	bool "STM32C092CC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 config ARCH_CHIP_STM32C092RB
 	bool "STM32C092RB"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_B
 
 config ARCH_CHIP_STM32C092RC
 	bool "STM32C092RC"
 	select ARCH_CHIP_STM32C092XX
+	select STM32F0L0G0_FLASH_CONFIG_C
 
 endchoice # ST STM32F0/L0/G0/C0 Chip Selection
 
@@ -1210,6 +1251,7 @@ config STM32F0L0G0_STM32G0
 	select STM32F0L0G0_HAVE_TIM16
 	select STM32F0L0G0_HAVE_TIM17
 	select STM32F0L0G0_HAVE_I2C2
+	select ARCH_HAVE_PROGMEM
 
 config STM32F0L0G0_STM32L0
 	bool
@@ -1235,6 +1277,7 @@ config STM32F0L0G0_STM32C0
 	select STM32F0L0G0_HAVE_TIM14
 	select STM32F0L0G0_HAVE_TIM16
 	select STM32F0L0G0_HAVE_TIM17
+	select ARCH_HAVE_PROGMEM
 
 config STM32F0L0G0_STM32F03X
 	bool

arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h

@@ -87,6 +87,119 @@
 #define FLASH_ACR_DBGSWEN           (1 << 18) /* Bit 18: Debug access software enable */
                                               /* Bits 19-31: Reserved */
 
-/* TODO */
+/* Flash Status Register (SR) */
+
+#define FLASH_SR_EOP                 (1)       /* Bit 0: End of operation */
+#define FLASH_SR_OPERR               (1 << 1)  /* Bit 1: Operation error */
+                                               /* Bit 2: Reserved */
+#define FLASH_SR_PROGERR             (1 << 3)  /* Bit 3: Programming error */
+#define FLASH_SR_WRPERR              (1 << 4)  /* Bit 4: Write protection error */
+#define FLASH_SR_PGAERR              (1 << 5)  /* Bit 5: Programming alignment error */
+#define FLASH_SR_SIZERR              (1 << 6)  /* Bit 6: Size error */
+#define FLASH_SR_PGSERR              (1 << 7)  /* Bit 7: Programming sequence error */
+#define FLASH_SR_MISSERR             (1 << 8)  /* Bit 8: Fast programming data miss error */
+#define FLASH_SR_FASTERR             (1 << 9)  /* Bit 9: Fast programming error */
+                                               /* Bits 10-13: Reserved */
+#define FLASH_SR_RDERR               (1 << 14) /* Bit 14: PCROP read error */
+#define FLASH_SR_OPTVERR             (1 << 15) /* Bit 15: Option and engineering bits loading validity error */
+#define FLASH_SR_BSY1                (1 << 16) /* Bit 16: Busy */
+                                               /* Bit 17: Reserved */
+#define FLASH_SR_CFGBSY              (1 << 18) /* Bit 18: Programming or erase configuration busy */
+                                               /* Bits 19-31: Reserved */
+
+/* Flash Control Register (CR) */
+
+#define FLASH_CR_PG                  (1)      /* Bit 0: Flash memory programming enable */
+#define FLASH_CR_PER                 (1 << 1) /* Bit 1: Page erase enable */
+#define FLASH_CR_MER1                (1 << 2) /* Bit 2: Mass erase */
+#define FLASH_CR_PNB_SHIFT           (3)      /* Bits 3-9: Page number selection */
+#define FLASH_CR_PNB_MASK            (0x7f << FLASH_CR_PNB_SHIFT)
+#  define FLASH_CR_PNB(n)            ((n) << FLASH_CR_PNB_SHIFT)
+
+#define FLASH_CR_STRT                (1 << 16) /* Bit 16: Start erase operation */
+#define FLASH_CR_OPTSTRT             (1 << 17) /* Bit 17: Start of modification of option bytes */
+#define FLASH_CR_FSTPG               (1 << 18) /* Bit 18: Fast programming enable */
+                                               /* Bits 19-23: Reserved */
+#define FLASH_CR_EOPIE               (1 << 24) /* Bit 24: End-of-operation interrupt enable */
+#define FLASH_CR_ERRIE               (1 << 25) /* Bit 25: Error interrupt enable */
+#define FLASH_CR_RDERRIE             (1 << 26) /* Bit 26: PCROP read error interrupt enable */
+#define FLASH_CR_OBL_LAUNCH          (1 << 27) /* Bit 27: Option byte load launch */
+#define FLASH_CR_SEC_PROT            (1 << 28) /* Bit 28: Securable memory area protection enable */
+                                               /* Bit 29: Reserved */
+#define FLASH_CR_OPTLOCK             (1 << 30) /* Bit 30: Options Lock */
+#define FLASH_CR_LOCK                (1 << 31) /* Bit 31: FLASH_CR Lock */
+
+/* Flash Option Register (OPTR) */
+
+#define FLASH_OPTR_RDP_SHIFT         (0)
+#define FLASH_OPTR_RDP_MASK          (0xff << FLASH_OPTR_RDP_SHIFT)
+#define FLASH_OPTR_BOR_EN            (1 << 8) /* Brown out reset enable */
+#define FLASH_OPTR_BORR_LEV_SHIFT    (9)      /* BOR threshold at rising Vdd supply */
+#define FLASH_OPTR_BORR_LEV_MASK     (0x3 << FLASH_OPTR_BORR_LEV_SHIFT)
+#define FLASH_OPTR_BORF_LEV_SHIFT    (11)     /* BOR thresholda t falling Vdd supply */
+#define FLASH_OPTR_BORF_LEV_MASK     (0x3 << FLASH_OPTR_BORF_LEV_SHIFT)
+#define FLASH_OPTR_NRST_STOP         (1 << 13)
+#define FLASH_OPTR_NRST_STDBY        (1 << 14)
+#define FLASH_OPTR_NRSTS_SHDW        (1 << 15)
+#define FLASH_OPTR_IDWG_SW           (1 << 16) /* Bit 16: Independent watchdog selection */
+#define FLASH_OPTR_IDWG_STOP         (1 << 17) /* Bit 17: Independent watchdog counter freeze in stop mode */
+#define FLASH_OPTR_IDWG_STDBY        (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode */
+#define FLASH_OPTR_WWDG_SW           (1 << 19) /* Bit 19: Window watchdog selection */
+                                               /* Bit 20: Reserved */
+#define FLASH_OPTR_HSE_NOT_REMAPPED  (1 << 21) /* Bit 21: HSE remapping enable/disable */
+#define FLASH_OPTR_RAM_PARITY_CHECK  (1 << 22) /* Bit 22: SRAM parity check control */
+#define FLASH_OPTR_SECURE_MUXING_EN  (1 << 23) /* Bit 23: Multiple-bonding security */
+                                               /* Bit 23: Reserved */
+#define FLASH_OPTR_NBOOT_SEL         (1 << 24) /* Bit 24: BOOT0 signal source selection */
+#define FLASH_OPTR_NBOOT1            (1 << 25) /* Bit 25: NBOOT1 boot configuration */
+#define FLASH_OPTR_NBOOT0            (1 << 26) /* Bit 26: NBOOT0 option bit */
+#define FLASH_OPTR_NRST_MODE_SHIFT   (27)      /* Bits 27-28: PF2-NRST pin configuration */
+#define FLASH_OPTR_NRST_MODE_MASK    (0x3 << FLASH_OPTR_NRST_MODE_SHIFT)
+#define FLASH_OPTR_IRHEN             (1 << 29) /* Bit 29: Internal reset holder enable */
+#define FLASH_OPTR_FDCAN_BLCK_SHIFT  (30)      /* Bits 30-31: FDCAN bootloader clock source */
+#define FLASH_OPTR_FDCAN_BLCK_MASK   (0x3 << FLASH_OPTR_FDCAN_BLCK_SHIFT)
+
+/* Flash PCROP area A start address register (PCROP1ASR) */
+
+#define FLASH_PCROP1ASR_STRT_SHIFT          (0)
+#define FLASH_PCROP1ASR_STRT_MASK           (0x1ff << FLASH_PCROP1ASR_STRT_SHIFT)
+
+/* Flash PCROP area A end address register (PCROP1AER) */
+
+#define FLASH_PCROP1AER_PCROP1A_END_SHIFT   (0)
+#define FLASH_PCROP1AER_PCROP1A_END_MASK    (0x1ff << FLASH_PCROP1AER_PCROP1A_END_SHIFT)
+#define FLASH_PCROP1AER_PCROP_RDP           (1 << 31)
+
+/* Flash WRP area A address register (WRP1AR) */
+
+#define FLASH_WRP1AR_WRP1A_STRT_SHIFT       (0)
+#define FLASH_WRP1AR_WRP1A_STRT_MASK        (0x7f << FLASH_WRP1AR_WRP1A_STRT_SHIFT)
+#define FLASH_WRP1AR_WRP1A_END_SHIFT        (16)
+#define FLASH_WRP1AR_WRP1A_END_MASK         (0x7f << FLASH_WRP1AR_WRP1A_END_SHIFT)
+
+/* Flash WRP area B address register (WRP1BR) */
+
+#define FLASH_WRP1BR_WRP1B_STRT_SHIFT       (0)
+#define FLASH_WRP1BR_WRP1B_STRT_MASK        (0x7f << FLASH_WRP1BR_WRP1B_STRT_SHIFT)
+#define FLASH_WRP1BR_WRP1B_END_SHIFT        (16)
+#define FLASH_WRP1BR_WRP1B_END_MASK         (0x7f << FLASH_WRP1BR_WRP1B_END_SHIFT)
+
+/* Flash PCROP area B start address register (PCROP1BSR) */
+
+#define FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT  (0)
+#define FLASH_PCROP1BSR_PCROP1B_STRT_MASK   (0x1ff << FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT)
+
+/* Flash PCROP area B end address register (PCROP1BER) */
+
+#define FLASH_PCROP1BER_PCROP1B_END_SHIFT   (0)
+#define FLASH_PCROP1BER_PCROP1B_END_MASK    (0x1ff << FLASH_PCROP1BER_PCROP1B_END_SHIFT)
+
+/* Flash Security register (SECR) */
+
+#define FLASH_SECR_SEC_SIZE_SHIFT           (0)       /* Bits 0-7: Securable memory area size */
+#define FLASH_SECR_SEC_SIZE_MASK            (0xff << FLASH_SECR_SEC_SIZE_SHIFT)
+                                                      /* Bits 8-15: Reserved */
+#define FLASH_SECR_BOOT_LOCK                (1 << 16) /* Bit 16: Used to force boot from user area */
+                                                      /* Bits 20-31: Reserved */
 
 #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */

arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h

@@ -41,26 +41,22 @@
 #define STM32_PWR_CR1_OFFSET   0x0000  /* Power control register 1 */
 #define STM32_PWR_CR2_OFFSET   0x0004  /* Power control register 2 */
 #define STM32_PWR_CR3_OFFSET   0x0008  /* Power control register 3 */
-#define STM32_PWR_CR4_OFFSET   0x000C  /* Power control register 4 */
+#define STM32_PWR_CR4_OFFSET   0x000c  /* Power control register 4 */
 #define STM32_PWR_SR1_OFFSET   0x0010  /* Power status register 1 */
 #define STM32_PWR_SR2_OFFSET   0x0014  /* Power status register 2 */
 #define STM32_PWR_SCR_OFFSET   0x0018  /* Power status clear register */
 #define STM32_PWR_PUCRA_OFFSET 0x0020  /* Power Port A pull-up control register */
 #define STM32_PWR_PDCRA_OFFSET 0x0024  /* Power Port A pull-down control register */
 #define STM32_PWR_PUCRB_OFFSET 0x0028  /* Power Port B pull-up control register */
-#define STM32_PWR_PDCRB_OFFSET 0x002C  /* Power Port B pull-down control register */
+#define STM32_PWR_PDCRB_OFFSET 0x002c  /* Power Port B pull-down control register */
 #define STM32_PWR_PUCRC_OFFSET 0x0030  /* Power Port C pull-up control register */
 #define STM32_PWR_PDCRC_OFFSET 0x0034  /* Power Port C pull-down control register */
 #define STM32_PWR_PUCRD_OFFSET 0x0038  /* Power Port D pull-up control register */
-#define STM32_PWR_PDCRD_OFFSET 0x003C  /* Power Port D pull-down control register */
+#define STM32_PWR_PDCRD_OFFSET 0x003c  /* Power Port D pull-down control register */
-#define STM32_PWR_PUCRF_OFFSET 0x0048  /* Power Port F pull-up control register */
+#define STM32_PWR_BKP0R_OFFSET 0x0070  /* PWR backup 0 register  */
-#define STM32_PWR_PDCRF_OFFSET 0x004C  /* Power Port F pull-down control register */
+#define STM32_PWR_BKP1R_OFFSET 0x0074  /* PWR backup 1 register  */
-#define STM32_PWR_PUCRG_OFFSET 0x0050  /* Power Port G pull-up control register */
+#define STM32_PWR_BKP2R_OFFSET 0x0078  /* PWR backup 2 register  */
-#define STM32_PWR_PDCRG_OFFSET 0x0054  /* Power Port G pull-down control register */
+#define STM32_PWR_BKP3R_OFFSET 0x007c  /* PWR backup 3 register  */
-#define STM32_PWR_PUCRH_OFFSET 0x0058  /* Power Port H pull-up control register */
-#define STM32_PWR_PDCRH_OFFSET 0x005C  /* Power Port H pull-down control register */
-#define STM32_PWR_PUCRI_OFFSET 0x0060  /* Power Port I pull-up control register */
-#define STM32_PWR_PDCRI_OFFSET 0x0064  /* Power Port I pull-down control register */
 
 /* Register Addresses *******************************************************/
 
@@ -79,16 +75,10 @@
 #define STM32_PWR_PDCRC        (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
 #define STM32_PWR_PUCRD        (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET)
 #define STM32_PWR_PDCRD        (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET)
-#define STM32_PWR_PUCRE        (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET)
+#define STM32_PWR_BKP0R        (STM32_PWR_BASE+STM32_PWR_BKP0R_OFFSET)
-#define STM32_PWR_PDCRE        (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET)
+#define STM32_PWR_BKP1R        (STM32_PWR_BASE+STM32_PWR_BKP1R_OFFSET)
-#define STM32_PWR_PUCRF        (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET)
+#define STM32_PWR_BKP2R        (STM32_PWR_BASE+STM32_PWR_BKP2R_OFFSET)
-#define STM32_PWR_PDCRF        (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET)
+#define STM32_PWR_BKP3R        (STM32_PWR_BASE+STM32_PWR_BKP3R_OFFSET)
-#define STM32_PWR_PUCRG        (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET)
-#define STM32_PWR_PDCRG        (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET)
-#define STM32_PWR_PUCRH        (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
-#define STM32_PWR_PDCRH        (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
-#define STM32_PWR_PUCRI        (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET)
-#define STM32_PWR_PDCRI        (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET)
 
 /* Register Bitfield Definitions ********************************************/
 
@@ -156,4 +146,8 @@
 #define PWR_SCR_CWUF5            (1 << 4) /* Bit 4: Clear wakeup flag 5 */
 #define PWR_SCR_CSBF             (1 << 8) /* Bit 8: Clear standby flag */
 
+/* Backup registers */
+
+#define PWR_BKPR_MASK            (0xffff) /* Bits 0-16: Backup bitfield */
+
 #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H */

arch/arm/src/stm32f0l0g0/stm32_flash.c

@@ -26,8 +26,8 @@
 
 #include <nuttx/config.h>
 
-#if defined(CONFIG_STM32F0L0G0_STM32G0)
+#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0)
-#  include "stm32g0_flash.c"
+#  include "stm32g0c0_flash.c"
 #else
 #  error "Flash driver unsupported on selected chip."
 #endif

arch/arm/src/stm32f0l0g0/stm32_pwr.c

@@ -33,7 +33,7 @@
 
 #if defined(CONFIG_STM32F0L0G0_STM32G0)
 #  include "stm32g0_pwr.c"
-#else
+#elif defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0)
 #  include "stm32f0l0_pwr.c"
 #endif