PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- Committing initial code for DTS. Missing ISR. Works for PCLK1. Cannot get to work for LSE.
- Pushing everything. Working with LSE now.
- Many fixes. Fixed interrupt setting. Added data structures.
- Changed interrupt handling. Removed FARs. Added Kconfig options for selecting interrupts.
- Updated info and formatting.
- Formatting fixes.
- Formatting.
- Changed iten to regval.
- Removed Triggger
- Formatting fixes per Pull request.
- Changed private_types to have stm32_ prefix. Used depends on for DTS Kconfig Menu. Fixed formatting per PR.
- Fixed spacing of function prototypes.
- Fixed indent on line
- Added documentation for STM32H5 and Nucleo-H563ZI regarding DTS. Also added GPDMA support to STM32H5 documentation (previous PR). Made stm32_dts.c more modular. stm32_dts_activate is now much more readable. Added comments/descriptions to private functions. Lastly, added a nucleo-h563zi:dts configuration.
Set level high for unused interrupt trigger to avoid waking up from cold sleeping.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Sim use coroutine base on one thread in host to do switch context. but if we allow switch context with in one API (host-API and errno get), maybe the switch context from coroutine cause re-enter host-API call. Make the errno get behavior not work as expected.
Signed-off-by: guanyi3 <guanyi3@xiaomi.com>
1. -target should be in front, otherwise clang will not be able to find the corresponding libgcc.a
2. When using clang++ compiler to link, you also need to specify the corresponding arch, otherwise ld.lld will report an error due to arch mismatch.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
return early due to signal interruption (EINTR). This makes the
main thread think the async operation is done, but the background
worker thread is still running—risking access to freed memory,
race conditions, crashes or undefined behavior.
Using nxsem_wait_uninterruptible():the main thread waits until the
worker thread finishes, preventing these issues.
Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
Align the writing style of arm cmake, and each compiler defines its own find library
function, otherwise use the default
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
In the toolchain, ARCH_TOOLCHAIN_XXX is used to select the compiler to be used. If clang is selected here, subsequent errors will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ
Signed-off-by: chao an <anchao.archer@bytedance.com>
AVR uses Hardward architecture with separate address space for program
memory (flash) and data memory (RAM). Normal program flow can only
access data memory which means that all variables - including const
variables - have to be copied into RAM to be accessible. (This happens
automatically during startup.)
It is possible to work around this limitation in software but that
can have severe impact on performance and/or API complexity. It is hardly
feasible to change NuttX interfaces in a way that would allow to make use
of this workaround.
On newer AVR families, there is an alternative option enabled by this patch.
These chips map part of their program memory (a 32kB window) into data
memory address space. This patch leverages this feature and adds support
for placing const variables into the mapped window. No copy to RAM is done
for them.
Const variables are therefore loaded directly from flash (not consuming
RAM) while still being available to be used by any NuttX interface.
Linker script of breadxavr board is changed to make use of these changes.
Tested by verifying string addresses - parameters in printf call
in a custom application (and also by running the application and verifying
its output.)
Documentation tested by build.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
Added logic to set hasdma to false. This is needed to enable or not enable interrupts on a per ADC basis. Made other minor formatting changes.
Fixed build issues with non ADC/DMA configurations.
The architecture defines maximum of 128 interrupts, whereas previous
code only supported 32 interrupts. For every 32 interrupts added,
there are three additional registers: INTERRUPT, INTCLEAR, and INTENABLE.
This patch adds support for handling these registers.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
GICD_ICFGR requires full 32-bit RMW operations.
Each interrupt uses 2 bits; thus updates must be synchronized
to avoid losing configuration in concurrent environments.
RMW conflict on GICD_ICFGRn (without lock)
CPU0 (set IRQ32 edge) CPU1 (set IRQ33 level)
--------------------- -----------------------
val0 = read(ICFGRn) │ val1 = read(ICFGRn)
│
val0 |= (edge << 4) │
│ val1 &= ~(3 << 6)
│
write(ICFGRn, val0) │
│ write(ICFGRn, val1)
=> IRQ32 config lost OR IRQ33 config lost
(depends on which write finishes last)
Concurrent RMW on ICFGRn causes lost config.
Protect with spinlock to avoid data race.
Since interrupt type configuration is infrequent,
a single global GIC lock is sufficient (no need for
fine-grained locking per ICFGR register).
Signed-off-by: Shen Cao <caoshen3@lixiang.com>
Previous code was failing to disable error interrupts which
due to standard CAN retransmissions might trigger continusouly
(for example, with a disconnected CAN interface) flooding the
system and preventing other operations to continue.
Fixes: https://github.com/apache/nuttx/issues/16668
Signed-off-by: Carlos Sanchez <carlossanchez@geotab.com>
